1/**
2 * Copyright (c) 2021-2024 MUNIC SA
3 * Copyright (c) 2024 Renesas Electronics Corporation
4 *
5 * Renesas RA2L1 MCU series device tree
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9
10#include <freq.h>
11#include <mem.h>
12#include <arm/armv8-m.dtsi>
13#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
14#include <zephyr/dt-bindings/clock/ra_clock.h>
15
16/ {
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-m23";
24			reg = <0>;
25			#address-cells = <1>;
26			#size-cells = <1>;
27
28			mpu: mpu@e000ed90 {
29				compatible = "arm,armv8m-mpu";
30				reg = <0xe000ed90 0x40>;
31			};
32		};
33	};
34
35	soc {
36		interrupt-parent = <&nvic>;
37
38		sram0: memory@20000000 {
39			compatible = "mmio-sram";
40			reg = <0x20000000 0x8000>;
41		};
42
43		system: system@4001e000 {
44			compatible = "renesas,ra-system";
45			reg = <0x4001e000 0x1000>;
46			status = "okay";
47		};
48
49		flcn: flash-controller@407ec000 {
50			reg = <0x407ec000 0x10000>;
51
52			#address-cells = <1>;
53			#size-cells = <1>;
54
55			flash0: code@0 {
56				compatible = "soc-nv-flash";
57				/* "reg" property should be defined in the
58				 * chip specific .dtsi file
59				 */
60			};
61
62			flash1: data@40100000 {
63				compatible = "soc-nv-flash";
64				reg = <0x40100000 DT_SIZE_K(8)>;
65			};
66		};
67
68		ioport0: gpio@40040000 {
69			compatible = "renesas,ra-gpio-ioport";
70			reg = <0x40040000 0x20>;
71			port = <0>;
72			gpio-controller;
73			#gpio-cells = <2>;
74			ngpios = <16>;
75			status = "disabled";
76		};
77
78		ioport1: gpio@40040020 {
79			compatible = "renesas,ra-gpio-ioport";
80			reg = <0x40040020 0x20>;
81			port = <1>;
82			gpio-controller;
83			#gpio-cells = <2>;
84			ngpios = <16>;
85			status = "disabled";
86		};
87
88		ioport2: gpio@40040040 {
89			compatible = "renesas,ra-gpio-ioport";
90			reg = <0x40040040 0x20>;
91			port = <2>;
92			gpio-controller;
93			#gpio-cells = <2>;
94			ngpios = <16>;
95			status = "disabled";
96		};
97
98		ioport3: gpio@40040060 {
99			compatible = "renesas,ra-gpio-ioport";
100			reg = <0x40040060 0x20>;
101			port = <3>;
102			gpio-controller;
103			#gpio-cells = <2>;
104			ngpios = <16>;
105			status = "disabled";
106		};
107
108		ioport4: gpio@40040080 {
109			compatible = "renesas,ra-gpio-ioport";
110			reg = <0x40040080 0x20>;
111			port = <4>;
112			gpio-controller;
113			#gpio-cells = <2>;
114			ngpios = <16>;
115			status = "disabled";
116		};
117
118		ioport5: gpio@400400a0 {
119			compatible = "renesas,ra-gpio-ioport";
120			reg = <0x400400a0 0x20>;
121			port = <5>;
122			gpio-controller;
123			#gpio-cells = <2>;
124			ngpios = <16>;
125			status = "disabled";
126		};
127
128		ioport6: gpio@400400c0 {
129			compatible = "renesas,ra-gpio-ioport";
130			reg = <0x400400c0 0x20>;
131			port = <6>;
132			gpio-controller;
133			#gpio-cells = <2>;
134			ngpios = <16>;
135			status = "disabled";
136		};
137
138		ioport7: gpio@400400e0 {
139			compatible = "renesas,ra-gpio-ioport";
140			reg = <0x400400e0 0x20>;
141			port = <7>;
142			gpio-controller;
143			#gpio-cells = <2>;
144			ngpios = <16>;
145			status = "disabled";
146		};
147
148		pinctrl: pin-controller@40040800 {
149			compatible = "renesas,ra-pinctrl-pfs";
150			reg = <0x40040800 0x3c0>;
151			status = "okay";
152		};
153
154		sci0: sci0@40070000 {
155			compatible = "renesas,ra-sci";
156			interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
157			interrupt-names = "rxi", "txi", "tei", "eri";
158			reg = <0x40070000 0x100>;
159			clocks = <&pclkb MSTPB 31>;
160			status = "disabled";
161
162			uart {
163				compatible = "renesas,ra-sci-uart";
164				channel = <0>;
165				status = "disabled";
166			};
167		};
168
169		sci1: sci1@40070020 {
170			compatible = "renesas,ra-sci";
171			reg = <0x40070020 0x100>;
172			clocks = <&pclkb MSTPB 30>;
173			status = "disabled";
174
175			uart {
176				compatible = "renesas,ra-sci-uart";
177				channel = <1>;
178				status = "disabled";
179			};
180		};
181
182		sci2: sci2@40070040 {
183			compatible = "renesas,ra-sci";
184			reg = <0x40070040 0x100>;
185			clocks = <&pclkb MSTPB 29>;
186			status = "disabled";
187
188			uart {
189				compatible = "renesas,ra-sci-uart";
190				channel = <2>;
191				status = "disabled";
192			};
193		};
194
195		sci3: sci3@40070060 {
196			compatible = "renesas,ra-sci";
197			reg = <0x40070060 0x100>;
198			clocks = <&pclkb MSTPB 28>;
199			status = "disabled";
200
201			uart {
202				compatible = "renesas,ra-sci-uart";
203				channel = <3>;
204				status = "disabled";
205			};
206		};
207
208		sci9: sci9@40070120 {
209			compatible = "renesas,ra-sci";
210			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
211			interrupt-names = "rxi", "txi", "tei", "eri";
212			reg = <0x40070120 0x100>;
213			clocks = <&pclkb MSTPB 22>;
214			status = "disabled";
215
216			uart {
217				compatible = "renesas,ra-sci-uart";
218				channel = <9>;
219				status = "disabled";
220			};
221		};
222
223		id_code: id_code@1010018 {
224			compatible = "zephyr,memory-region";
225			reg = <0x01010018 0x20>;
226			zephyr,memory-region = "ID_CODE";
227			status = "okay";
228		};
229
230		wdt: wdt@40044200 {
231			compatible = "renesas,ra-wdt";
232			reg = <0x40044200 0x200>;
233			clocks = <&pclkb 0 0>;
234			status = "disabled";
235		};
236	};
237};
238
239&nvic {
240	arm,num-irq-priority-bits = <2>;
241};
242