1 /* 2 * Copyright (c) 2020 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADX345_ADX345_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADX345_ADX345_H_ 9 10 #include <zephyr/drivers/sensor.h> 11 #include <zephyr/types.h> 12 #include <zephyr/device.h> 13 #include <zephyr/drivers/gpio.h> 14 #include <zephyr/kernel.h> 15 #include <zephyr/sys/util.h> 16 17 #ifdef CONFIG_ADXL345_STREAM 18 #include <zephyr/rtio/rtio.h> 19 #endif /* CONFIG_ADXL345_STREAM */ 20 21 #define DT_DRV_COMPAT adi_adxl345 22 23 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 24 #include <zephyr/drivers/i2c.h> 25 #endif 26 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 27 #include <zephyr/drivers/spi.h> 28 #endif 29 #include <zephyr/sys/util.h> 30 31 /* ADXL345 communication commands */ 32 #define ADXL345_WRITE_CMD 0x00 33 #define ADXL345_READ_CMD 0x80 34 #define ADXL345_MULTIBYTE_FLAG 0x40 35 36 #define ADXL345_REG_READ(x) ((x & 0xFF) | ADXL345_READ_CMD) 37 38 #define SAMPLE_SIZE 6 39 #define SAMPLE_MASK 0x3F 40 #define SAMPLE_NUM 0x1F 41 42 /* Registers */ 43 #define ADXL345_DEVICE_ID_REG 0x00 44 #define ADXL345_RATE_REG 0x2c 45 #define ADXL345_POWER_CTL_REG 0x2d 46 #define ADXL345_DATA_FORMAT_REG 0x31 47 #define ADXL345_DATA_FORMAT_FULL_RES 0x08 48 #define ADXL345_X_AXIS_DATA_0_REG 0x32 49 #define ADXL345_FIFO_CTL_REG 0x38 50 #define ADXL345_FIFO_STATUS_REG 0x39 51 52 #define ADXL345_PART_ID 0xe5 53 54 #define ADXL345_RANGE_2G 0x0 55 #define ADXL345_RANGE_4G 0x1 56 #define ADXL345_RANGE_8G 0x2 57 #define ADXL345_RANGE_16G 0x3 58 #define ADXL345_RATE_25HZ 0x8 59 #define ADXL345_ENABLE_MEASURE_BIT (1 << 3) 60 #define ADXL345_FIFO_STREAM_MODE (1 << 7) 61 #define ADXL345_FIFO_COUNT_MASK 0x3f 62 #define ADXL345_COMPLEMENT_MASK(x) GENMASK(15, (x)) 63 #define ADXL345_COMPLEMENT 0xfc00 64 65 #define ADXL345_MAX_FIFO_SIZE 32 66 67 #define ADXL345_INT_ENABLE 0x2Eu 68 #define ADXL345_INT_MAP 0x2Fu 69 #define ADXL345_INT_SOURCE 0x30u 70 71 /* ADXL345_STATUS_1 */ 72 #define ADXL345_STATUS_DOUBLE_TAP(x) (((x) >> 5) & 0x1) 73 #define ADXL345_STATUS_SINGLE_TAP(x) (((x) >> 6) & 0x1) 74 #define ADXL345_STATUS_DATA_RDY(x) (((x) >> 7) & 0x1) 75 76 /* ADXL345_INT_MAP */ 77 #define ADXL345_INT_MAP_OVERRUN_MSK BIT(0) 78 #define ADXL345_INT_MAP_OVERRUN_MODE(x) (((x) & 0x1) << 0) 79 #define ADXL345_INT_MAP_WATERMARK_MSK BIT(1) 80 #define ADXL345_INT_MAP_WATERMARK_MODE(x) (((x) & 0x1) << 1) 81 #define ADXL345_INT_MAP_FREE_FALL_MSK BIT(2) 82 #define ADXL345_INT_MAP_FREE_FALL_MODE(x) (((x) & 0x1) << 2) 83 #define ADXL345_INT_MAP_INACT_MSK BIT(3) 84 #define ADXL345_INT_MAP_INACT_MODE(x) (((x) & 0x1) << 3) 85 #define ADXL345_INT_MAP_ACT_MSK BIT(4) 86 #define ADXL345_INT_MAP_ACT_MODE(x) (((x) & 0x1) << 4) 87 #define ADXL345_INT_MAP_DOUBLE_TAP_MSK BIT(5) 88 #define ADXL345_INT_MAP_DOUBLE_TAP_MODE(x) (((x) & 0x1) << 5) 89 #define ADXL345_INT_MAP_SINGLE_TAP_MSK BIT(6) 90 #define ADXL345_INT_MAP_SINGLE_TAP_MODE(x) (((x) & 0x1) << 6) 91 #define ADXL345_INT_MAP_DATA_RDY_MSK BIT(7) 92 #define ADXL345_INT_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 7) 93 94 /* POWER_CTL */ 95 #define ADXL345_POWER_CTL_WAKEUP_4HZ BIT(0) 96 #define ADXL345_POWER_CTL_WAKEUP_4HZ_MODE(x) (((x) & 0x1) << 0) 97 #define ADXL345_POWER_CTL_WAKEUP_2HZ BIT(1) 98 #define ADXL345_POWER_CTL_WAKEUP_2HZ_MODE(x) (((x) & 0x1) << 1) 99 #define ADXL345_POWER_CTL_SLEEP BIT(2) 100 #define ADXL345_POWER_CTL_SLEEP_MODE(x) (((x) & 0x1) << 2) 101 #define ADXL345_POWER_CTL_MEASURE_MSK GENMASK(3, 3) 102 #define ADXL345_POWER_CTL_MEASURE_MODE(x) (((x) & 0x1) << 3) 103 #define ADXL345_POWER_CTL_STANDBY_MODE(x) (((x) & 0x0) << 3) 104 105 /* ADXL345_FIFO_CTL */ 106 #define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6) 107 #define ADXL345_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 6) 108 #define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5) 109 #define ADXL345_FIFO_CTL_TRIGGER_MODE(x) (((x) & 0x1) << 5) 110 #define ADXL345_FIFO_CTL_SAMPLES_MSK BIT(0) 111 #define ADXL345_FIFO_CTL_SAMPLES_MODE(x) ((x) & 0x1F) 112 113 #define ADXL345_ODR_MSK GENMASK(3, 0) 114 #define ADXL345_ODR_MODE(x) ((x) & 0xF) 115 116 #define ADXL345_BUS_I2C 0 117 #define ADXL345_BUS_SPI 1 118 119 enum adxl345_odr { 120 ADXL345_ODR_12HZ = 0x7, 121 ADXL345_ODR_25HZ, 122 ADXL345_ODR_50HZ, 123 ADXL345_ODR_100HZ, 124 ADXL345_ODR_200HZ, 125 ADXL345_ODR_400HZ 126 }; 127 128 enum adxl345_fifo_trigger { 129 ADXL345_INT1, 130 ADXL345_INT2 131 }; 132 133 enum adxl345_fifo_mode { 134 ADXL345_FIFO_BYPASSED, 135 ADXL345_FIFO_OLD_SAVED, 136 ADXL345_FIFO_STREAMED, 137 ADXL345_FIFO_TRIGGERED 138 }; 139 140 struct adxl345_fifo_config { 141 enum adxl345_fifo_mode fifo_mode; 142 enum adxl345_fifo_trigger fifo_trigger; 143 uint16_t fifo_samples; 144 }; 145 146 enum adxl345_op_mode { 147 ADXL345_STANDBY, 148 ADXL345_MEASURE 149 }; 150 151 struct adxl345_dev_data { 152 unsigned int sample_number; 153 int16_t bufx[ADXL345_MAX_FIFO_SIZE]; 154 int16_t bufy[ADXL345_MAX_FIFO_SIZE]; 155 int16_t bufz[ADXL345_MAX_FIFO_SIZE]; 156 struct adxl345_fifo_config fifo_config; 157 uint8_t is_full_res; 158 uint8_t selected_range; 159 #ifdef CONFIG_ADXL345_TRIGGER 160 struct gpio_callback gpio_cb; 161 162 sensor_trigger_handler_t th_handler; 163 const struct sensor_trigger *th_trigger; 164 sensor_trigger_handler_t drdy_handler; 165 const struct sensor_trigger *drdy_trigger; 166 const struct device *dev; 167 168 #if defined(CONFIG_ADXL345_TRIGGER_OWN_THREAD) 169 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL345_THREAD_STACK_SIZE); 170 struct k_sem gpio_sem; 171 struct k_thread thread; 172 #elif defined(CONFIG_ADXL345_TRIGGER_GLOBAL_THREAD) 173 struct k_work work; 174 #endif 175 #endif /* CONFIG_ADXL345_TRIGGER */ 176 #ifdef CONFIG_ADXL345_STREAM 177 struct rtio_iodev_sqe *sqe; 178 struct rtio *rtio_ctx; 179 struct rtio_iodev *iodev; 180 uint8_t status1; 181 uint8_t fifo_ent[1]; 182 uint64_t timestamp; 183 struct rtio *r_cb; 184 uint8_t fifo_watermark_irq; 185 uint8_t fifo_samples; 186 uint16_t fifo_total_bytes; 187 #endif /* CONFIG_ADXL345_STREAM */ 188 }; 189 190 struct adxl345_fifo_data { 191 uint8_t is_fifo: 1; 192 uint8_t is_full_res: 1; 193 uint8_t selected_range: 2; 194 uint8_t sample_set_size: 4; 195 uint8_t int_status; 196 uint16_t accel_odr: 4; 197 uint16_t fifo_byte_count: 12; 198 uint64_t timestamp; 199 } __attribute__((__packed__)); 200 201 struct adxl345_sample { 202 #ifdef CONFIG_ADXL345_STREAM 203 uint8_t is_fifo: 1; 204 uint8_t res: 7; 205 #endif /* CONFIG_ADXL345_STREAM */ 206 uint8_t selected_range; 207 int16_t x; 208 int16_t y; 209 int16_t z; 210 }; 211 212 union adxl345_bus { 213 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 214 struct i2c_dt_spec i2c; 215 #endif 216 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 217 struct spi_dt_spec spi; 218 #endif 219 }; 220 221 typedef bool (*adxl345_bus_is_ready_fn)(const union adxl345_bus *bus); 222 typedef int (*adxl345_reg_access_fn)(const struct device *dev, uint8_t cmd, 223 uint8_t reg_addr, uint8_t *data, size_t length); 224 225 struct adxl345_dev_config { 226 const union adxl345_bus bus; 227 adxl345_bus_is_ready_fn bus_is_ready; 228 adxl345_reg_access_fn reg_access; 229 enum adxl345_odr odr; 230 bool op_mode; 231 struct adxl345_fifo_config fifo_config; 232 uint8_t bus_type; 233 #ifdef CONFIG_ADXL345_TRIGGER 234 struct gpio_dt_spec interrupt; 235 #endif 236 }; 237 238 void adxl345_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 239 void adxl345_stream_irq_handler(const struct device *dev); 240 241 #ifdef CONFIG_ADXL345_TRIGGER 242 int adxl345_get_status(const struct device *dev, 243 uint8_t *status, uint16_t *fifo_entries); 244 245 int adxl345_trigger_set(const struct device *dev, 246 const struct sensor_trigger *trig, 247 sensor_trigger_handler_t handler); 248 249 int adxl345_init_interrupt(const struct device *dev); 250 251 #endif /* CONFIG_ADXL345_TRIGGER */ 252 253 int adxl345_reg_write_mask(const struct device *dev, 254 uint8_t reg_addr, 255 uint8_t mask, 256 uint8_t data); 257 258 int adxl345_reg_access(const struct device *dev, uint8_t cmd, uint8_t addr, 259 uint8_t *data, size_t len); 260 261 int adxl345_reg_write(const struct device *dev, uint8_t addr, uint8_t *data, 262 uint8_t len); 263 264 int adxl345_reg_read(const struct device *dev, uint8_t addr, uint8_t *data, 265 uint8_t len); 266 267 int adxl345_reg_write_byte(const struct device *dev, uint8_t addr, uint8_t val); 268 269 int adxl345_reg_read_byte(const struct device *dev, uint8_t addr, uint8_t *buf); 270 271 int adxl345_set_op_mode(const struct device *dev, enum adxl345_op_mode op_mode); 272 #ifdef CONFIG_SENSOR_ASYNC_API 273 int adxl345_read_sample(const struct device *dev, struct adxl345_sample *sample); 274 void adxl345_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 275 int adxl345_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); 276 void adxl345_accel_convert(struct sensor_value *val, int16_t sample); 277 #endif /* CONFIG_SENSOR_ASYNC_API */ 278 279 #ifdef CONFIG_ADXL345_STREAM 280 int adxl345_configure_fifo(const struct device *dev, enum adxl345_fifo_mode mode, 281 enum adxl345_fifo_trigger trigger, uint16_t fifo_samples); 282 size_t adxl345_get_packet_size(const struct adxl345_dev_config *cfg); 283 #endif /* CONFIG_ADXL345_STREAM */ 284 #endif /* ZEPHYR_DRIVERS_SENSOR_ADX345_ADX345_H_ */ 285
