1 /*
2 * Copyright (c) 2024 Analog Devices Inc.
3 * Copyright (c) 2024 Baylibre SAS
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT adi_max22190_gpio
9
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/drivers/spi.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/sys/byteorder.h>
14
15 #define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
16 #include <zephyr/logging/log.h>
17
18 LOG_MODULE_REGISTER(gpio_max22190);
19
20 #include <zephyr/drivers/gpio/gpio_utils.h>
21
22 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
23 #warning "GPIO MAX22190 driver enabled without any devices"
24 #endif
25
26 #define MAX22190_ENABLE 1
27 #define MAX22190_DISABLE 0
28
29 #define MAX22190_READ 0
30 #define MAX22190_WRITE 1
31
32 #define MAX22190_MAX_PKT_SIZE 3
33 #define MAX22190_CHANNELS 8
34 #define MAX22190_FAULT2_ENABLES 5
35
36 #define MAX22190_WB_REG 0x0
37 #define MAX22190_DI_REG 0x2
38 #define MAX22190_FAULT1_REG 0x4
39 #define MAX22190_FILTER_IN_REG(x) (0x6 + (2 * (x)))
40 #define MAX22190_CFG_REG 0x18
41 #define MAX22190_IN_EN_REG 0x1A
42 #define MAX22190_FAULT2_REG 0x1C
43 #define MAX22190_FAULT2_EN_REG 0x1E
44 #define MAX22190_GPO_REG 0x22
45 #define MAX22190_FAULT1_EN_REG 0x24
46 #define MAX22190_NOP_REG 0x26
47
48 #define MAX22190_CH_STATE_MASK(x) BIT(x)
49 #define MAX22190_DELAY_MASK GENMASK(2, 0)
50 #define MAX22190_FBP_MASK BIT(3)
51 #define MAX22190_WBE_MASK BIT(4)
52 #define MAX22190_RW_MASK BIT(7)
53 #define MAX22190_ADDR_MASK GENMASK(6, 0)
54 #define MAX22190_ALARM_MASK GENMASK(4, 3)
55 #define MAX22190_POR_MASK BIT(6)
56
57 #define MAX22190_FAULT_MASK(x) BIT(x)
58 #define MAX22190_FAULT2_WBE_MASK BIT(4)
59
60 #define MAX22190_FAULT2_EN_MASK GENMASK(5, 0)
61
62 #define MAX22190_CFG_REFDI_MASK BIT(0)
63 #define MAX22190_CFG_CLRF_MASK BIT(3)
64 #define MAX22190_CFG_24VF_MASK BIT(4)
65
66 #define PRINT_ERR_BIT(bit1, bit2) \
67 if (bit1 & bit2) { \
68 LOG_ERR("[%s] %d", #bit1, bit1); \
69 }
70
71 #define MAX22190_CLEAN_POR(dev) \
72 max22190_reg_update(dev, MAX22190_FAULT1_REG, MAX22190_POR_MASK, \
73 FIELD_PREP(MAX22190_POR_MASK, 0))
74
75 enum max22190_ch_state {
76 MAX22190_CH_OFF,
77 MAX22190_CH_ON
78 };
79
80 enum max22190_ch_wb_state {
81 MAX22190_CH_NO_WB_BREAK,
82 MAX22190_CH_WB_COND_DET
83 };
84
85 enum max22190_mode {
86 MAX22190_MODE_0,
87 MAX22190_MODE_1,
88 MAX22190_MODE_2,
89 MAX22190_MODE_3,
90 };
91
92 union max22190_fault1 {
93 uint8_t reg_raw;
94 struct {
95 uint8_t max22190_WBG: 1; /* BIT 0 */
96 uint8_t max22190_24VM: 1;
97 uint8_t max22190_24VL: 1;
98 uint8_t max22190_ALRMT1: 1;
99 uint8_t max22190_ALRMT2: 1;
100 uint8_t max22190_FAULT2: 1;
101 uint8_t max22190_POR: 1;
102 uint8_t max22190_CRC: 1; /* BIT 7 */
103 } reg_bits;
104 };
105
106 union max22190_fault1_en {
107 uint8_t reg_raw;
108 struct {
109 uint8_t max22190_WBGE: 1; /* BIT 0 */
110 uint8_t max22190_24VME: 1;
111 uint8_t max22190_24VLE: 1;
112 uint8_t max22190_ALRMT1E: 1;
113 uint8_t max22190_ALRMT2E: 1;
114 uint8_t max22190_FAULT2E: 1;
115 uint8_t max22190_PORE: 1;
116 uint8_t max22190_CRCE: 1; /* BIT 7 */
117 } reg_bits;
118 };
119
120 union max22190_fault2 {
121 uint8_t reg_raw;
122 struct {
123 uint8_t max22190_RFWBS: 1; /* BIT 0 */
124 uint8_t max22190_RFWBO: 1;
125 uint8_t max22190_RFDIS: 1;
126 uint8_t max22190_RFDIO: 1;
127 uint8_t max22190_OTSHDN: 1;
128 uint8_t max22190_FAULT8CK: 1;
129 uint8_t max22190_DUMMY: 2; /* BIT 7 */
130 } reg_bits;
131 };
132
133 union max22190_fault2_en {
134 uint8_t reg_raw;
135 struct {
136 uint8_t max22190_RFWBSE: 1; /* BIT 0 */
137 uint8_t max22190_RFWBOE: 1;
138 uint8_t max22190_RFDISE: 1;
139 uint8_t max22190_RFDIOE: 1;
140 uint8_t max22190_OTSHDNE: 1;
141 uint8_t max22190_FAULT8CKE: 1;
142 uint8_t max22190_DUMMY: 2; /* BIT 7 */
143 } reg_bits;
144 };
145
146 union max22190_cfg {
147 uint8_t reg_raw;
148 struct {
149 uint8_t max22190_DUMMY1: 3; /* BIT 0 */
150 uint8_t max22190_24VF: 1;
151 uint8_t max22190_CLRF: 1;
152 uint8_t max22190_DUMMY2: 2;
153 uint8_t max22190_REFDI_SH_EN: 1; /* BIT 7 */
154 } reg_bits;
155 };
156
157 union max22190_filter {
158 uint8_t reg_raw;
159 struct {
160 uint8_t max22190_DELAY: 3; /* BIT 0 */
161 uint8_t max22190_FBP: 1;
162 uint8_t max22190_WBE: 1;
163 uint8_t max22190_DUMMY: 2; /* BIT 7 */
164 } reg_bits;
165 };
166
167 enum max22190_delay {
168 MAX22190_DELAY_50US,
169 MAX22190_DELAY_100US,
170 MAX22190_DELAY_400US,
171 MAX22190_DELAY_800US,
172 MAX22190_DELAY_1800US,
173 MAX22190_DELAY_3200US,
174 MAX22190_DELAY_12800US,
175 MAX22190_DELAY_20000US
176 };
177
178 struct max22190_config {
179 struct spi_dt_spec spi;
180 struct gpio_dt_spec fault_gpio;
181 struct gpio_dt_spec ready_gpio;
182 struct gpio_dt_spec latch_gpio;
183 union max22190_filter filter[8];
184 bool crc_en;
185 enum max22190_mode mode;
186 uint8_t pkt_size;
187 };
188
189 struct max22190_data {
190 struct gpio_driver_data common;
191 enum max22190_ch_state channels[MAX22190_CHANNELS];
192 enum max22190_ch_wb_state wb[MAX22190_CHANNELS];
193 union max22190_cfg cfg;
194 union max22190_fault1 fault1;
195 union max22190_fault1_en fault1_en;
196 union max22190_fault2 fault2;
197 union max22190_fault2_en fault2_en;
198 };
199
200 /*
201 * @brief Compute the CRC5 value for MAX22190
202 * @param data - Data array to calculate CRC for.
203 * @return CRC result.
204 */
max22190_crc(uint8_t * data)205 static uint8_t max22190_crc(uint8_t *data)
206 {
207 int length = 19;
208 uint8_t crc_step, tmp;
209 uint8_t crc_init = 0x7;
210 uint8_t crc_poly = 0x35;
211 int i;
212
213 /*
214 * This is the C custom implementation of CRC function for MAX22190, and
215 * can be found here:
216 * https://www.analog.com/en/design-notes/guidelines-to-implement-crc-algorithm.html
217 */
218 uint32_t datainput = (uint32_t)((data[0] << 16) + (data[1] << 8) + data[2]);
219
220 datainput = (datainput & 0xFFFFE0) + crc_init;
221
222 tmp = (uint8_t)((datainput & 0xFC0000) >> 18);
223
224 if ((tmp & 0x20) == 0x20) {
225 crc_step = (uint8_t)(tmp ^ crc_poly);
226 } else {
227 crc_step = tmp;
228 }
229
230 for (i = 0; i < length - 1; i++) {
231 tmp = (uint8_t)(((crc_step & 0x1F) << 1) +
232 ((datainput >> (length - 2 - i)) & 0x01));
233
234 if ((tmp & 0x20) == 0x20) {
235 crc_step = (uint8_t)(tmp ^ crc_poly);
236 } else {
237 crc_step = tmp;
238 }
239 }
240
241 return (uint8_t)(crc_step & 0x1F);
242 }
243
244 /*
245 * @brief Update chan WB state in max22190_data
246 *
247 * @param dev - MAX22190 device.
248 * @param val - value to be set.
249 */
max22190_update_wb_stat(const struct device * dev,uint8_t val)250 static void max22190_update_wb_stat(const struct device *dev, uint8_t val)
251 {
252 struct max22190_data *data = dev->data;
253
254 for (int ch_n = 0; ch_n < 8; ch_n++) {
255 data->wb[ch_n] = (val >> ch_n) & 0x1;
256 }
257 }
258
259 /*
260 * @brief Update chan IN state in max22190_data
261 *
262 * @param dev - MAX22190 device.
263 * @param val - value to be set.
264 */
max22190_update_in_stat(const struct device * dev,uint8_t val)265 static void max22190_update_in_stat(const struct device *dev, uint8_t val)
266 {
267 struct max22190_data *data = dev->data;
268
269 for (int ch_n = 0; ch_n < 8; ch_n++) {
270 data->channels[ch_n] = (val >> ch_n) & 0x1;
271 }
272 }
273
274 /*
275 * @brief Register write function for MAX22190
276 *
277 * @param dev - MAX22190 device config.
278 * @param addr - Register value to which data is written.
279 * @param val - Value which is to be written to requested register.
280 * @return 0 in case of success, negative error code otherwise.
281 */
max22190_reg_transceive(const struct device * dev,uint8_t addr,uint8_t val,uint8_t rw)282 static int max22190_reg_transceive(const struct device *dev, uint8_t addr, uint8_t val, uint8_t rw)
283 {
284 uint8_t crc;
285 int ret;
286
287 uint8_t local_rx_buff[MAX22190_MAX_PKT_SIZE] = {0};
288 uint8_t local_tx_buff[MAX22190_MAX_PKT_SIZE] = {0};
289
290 const struct max22190_config *config = dev->config;
291
292 struct spi_buf tx_buf = {
293 .buf = &local_tx_buff,
294 .len = config->pkt_size,
295 };
296 const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
297
298 struct spi_buf rx_buf = {
299 .buf = &local_rx_buff,
300 .len = config->pkt_size,
301 };
302 const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
303
304 local_tx_buff[0] =
305 FIELD_PREP(MAX22190_ADDR_MASK, addr) | FIELD_PREP(MAX22190_RW_MASK, rw & 0x1);
306 local_tx_buff[1] = val;
307
308 /* If CRC enabled calculate it */
309 if (config->crc_en) {
310 local_tx_buff[2] = max22190_crc(&local_tx_buff[0]);
311 }
312
313 /* write cmd & read resp at once */
314 ret = spi_transceive_dt(&config->spi, &tx, &rx);
315
316 if (ret) {
317 LOG_ERR("Err spi_transcieve_dt [%d]\n", ret);
318 return ret;
319 }
320
321 /* if CRC enabled check readed */
322 if (config->crc_en) {
323 crc = max22190_crc(&local_rx_buff[0]);
324 if (crc != (local_rx_buff[2] & 0x1F)) {
325 LOG_ERR("READ CRC ERR (%d)-(%d)\n", crc, (local_rx_buff[2] & 0x1F));
326 return -EINVAL;
327 }
328 }
329
330 /* always (R/W) get DI reg in first byte */
331 max22190_update_in_stat(dev, local_rx_buff[0]);
332
333 /* in case of writing register we get as second byte WB reg */
334 if (rw == MAX22190_WRITE) {
335 max22190_update_wb_stat(dev, local_rx_buff[1]);
336 } else {
337 /* in case of READ second byte is value we are looking for */
338 ret = local_rx_buff[1];
339 }
340
341 return ret;
342 }
343
344 #define max22190_reg_read(dev, addr) max22190_reg_transceive(dev, addr, 0, MAX22190_READ)
345 #define max22190_reg_write(dev, addr, val) max22190_reg_transceive(dev, addr, val, MAX22190_WRITE)
346
347 /*
348 * @brief Register update function for MAX22190
349 *
350 * @param dev - MAX22190 device.
351 * @param addr - Register valueto wich data is updated.
352 * @param mask - Corresponding mask to the data that will be updated.
353 * @param val - Updated value to be written in the register at update.
354 * @return 0 in case of success, negative error code otherwise.
355 */
max22190_reg_update(const struct device * dev,uint8_t addr,uint8_t mask,uint8_t val)356 static int max22190_reg_update(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
357 {
358 int ret;
359 uint32_t reg_val = 0;
360
361 ret = max22190_reg_read(dev, addr);
362
363 reg_val = ret;
364 reg_val &= ~mask;
365 reg_val |= mask & val;
366
367 return max22190_reg_write(dev, addr, reg_val);
368 }
369
370 /*
371 * @brief Check FAULT1 and FAULT2
372 *
373 * @param dev - MAX22190 device
374 */
max22190_fault_check(const struct device * dev)375 static void max22190_fault_check(const struct device *dev)
376 {
377 struct max22190_data *data = dev->data;
378
379 /* FAULT1 */
380 data->fault1.reg_raw = max22190_reg_read(dev, MAX22190_FAULT1_REG);
381
382 if (data->fault1.reg_raw) {
383 /* FAULT1_EN */
384 data->fault1_en.reg_raw = max22190_reg_read(dev, MAX22190_FAULT1_EN_REG);
385
386 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_CRC,
387 data->fault1_en.reg_bits.max22190_CRCE);
388 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_POR,
389 data->fault1_en.reg_bits.max22190_PORE);
390 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_FAULT2,
391 data->fault1_en.reg_bits.max22190_FAULT2E);
392 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_ALRMT2,
393 data->fault1_en.reg_bits.max22190_ALRMT2E);
394 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_ALRMT1,
395 data->fault1_en.reg_bits.max22190_ALRMT1E);
396 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_24VL,
397 data->fault1_en.reg_bits.max22190_24VLE);
398 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_24VM,
399 data->fault1_en.reg_bits.max22190_24VME);
400 PRINT_ERR_BIT(data->fault1.reg_bits.max22190_WBG,
401 data->fault1_en.reg_bits.max22190_WBGE);
402
403 if (data->fault1.reg_bits.max22190_WBG & data->fault1_en.reg_bits.max22190_WBGE) {
404 uint8_t wb_val = max22190_reg_read(dev, MAX22190_WB_REG);
405
406 max22190_update_wb_stat(dev, (uint8_t)wb_val);
407 }
408
409 if (data->fault1.reg_bits.max22190_FAULT2) {
410 /* FAULT2 */
411 data->fault2.reg_raw = max22190_reg_read(dev, MAX22190_FAULT2_REG);
412
413 /* FAULT2_EN */
414 data->fault2_en.reg_raw = max22190_reg_read(dev, MAX22190_FAULT2_EN_REG);
415
416 PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFWBS,
417 data->fault2_en.reg_bits.max22190_RFWBSE);
418 PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFWBO,
419 data->fault2_en.reg_bits.max22190_RFWBOE);
420 PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFDIS,
421 data->fault2_en.reg_bits.max22190_RFDISE);
422 PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFDIO,
423 data->fault2_en.reg_bits.max22190_RFDIOE);
424 PRINT_ERR_BIT(data->fault2.reg_bits.max22190_OTSHDN,
425 data->fault2_en.reg_bits.max22190_OTSHDNE);
426 PRINT_ERR_BIT(data->fault2.reg_bits.max22190_FAULT8CK,
427 data->fault2_en.reg_bits.max22190_FAULT8CKE);
428 }
429 }
430 }
431
max22190_state_get(const struct device * dev)432 static void max22190_state_get(const struct device *dev)
433 {
434 const struct max22190_config *config = dev->config;
435
436 if (gpio_pin_get_dt(&config->fault_gpio)) {
437 max22190_fault_check(dev);
438 }
439
440 /* We are reading WB reg because on first byte will be clocked out DI reg
441 * on second byte we will ge WB value.
442 */
443 uint8_t wb_val = max22190_reg_read(dev, MAX22190_WB_REG);
444
445 max22190_update_wb_stat(dev, (uint8_t)wb_val);
446 }
447
gpio_max22190_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)448 static int gpio_max22190_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
449 {
450 int err = 0;
451
452 if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
453 return -ENOTSUP;
454 }
455
456 if ((flags & GPIO_SINGLE_ENDED) != 0) {
457 return -ENOTSUP;
458 }
459
460 if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
461 return -ENOTSUP;
462 }
463
464 if (flags & GPIO_INT_ENABLE) {
465 return -ENOTSUP;
466 }
467
468 switch (flags & GPIO_DIR_MASK) {
469 case GPIO_INPUT:
470 LOG_INF("Nothing to do, only INPUT supported");
471 break;
472 default:
473 LOG_ERR("On MAX22190 only input option is available!");
474 return -ENOTSUP;
475 }
476
477 return err;
478 }
479
max22190_filter_set(const struct device * dev)480 static void max22190_filter_set(const struct device *dev)
481 {
482 const struct max22190_config *config = dev->config;
483
484 for (int ch_n = 0; ch_n < 8; ch_n++) {
485 max22190_reg_write(dev, MAX22190_FILTER_IN_REG(ch_n), config->filter[ch_n].reg_raw);
486 }
487 }
488
max22190_fault_set(const struct device * dev)489 static int max22190_fault_set(const struct device *dev)
490 {
491 const struct max22190_data *data = dev->data;
492 int ret = 0;
493
494 ret = max22190_reg_write(dev, MAX22190_FAULT1_EN_REG, data->fault1_en.reg_raw);
495 if (ret) {
496 goto exit_fault_set;
497 }
498
499 ret = max22190_reg_write(dev, MAX22190_FAULT1_REG, data->fault1.reg_raw);
500 if (ret) {
501 goto exit_fault_set;
502 }
503
504 ret = max22190_reg_write(dev, MAX22190_FAULT2_EN_REG, data->fault2_en.reg_raw);
505 if (ret) {
506 goto exit_fault_set;
507 }
508
509 ret = max22190_reg_write(dev, MAX22190_FAULT2_REG, data->fault2.reg_raw);
510 if (ret) {
511 goto exit_fault_set;
512 }
513
514 return ret;
515
516 exit_fault_set:
517 LOG_ERR("Err spi_transcieve_dt [%d]\n", ret);
518 return ret;
519 }
520
gpio_max22190_port_get_raw(const struct device * dev,gpio_port_value_t * value)521 static int gpio_max22190_port_get_raw(const struct device *dev, gpio_port_value_t *value)
522 {
523 const struct max22190_data *data = dev->data;
524
525 max22190_state_get(dev);
526 *value = 0;
527 for (int ch_n = 0; ch_n < 8; ch_n++) {
528 /* IN ch state */
529 *value |= data->channels[ch_n] << ch_n;
530 }
531
532 return 0;
533 }
534
gpio_max22190_init(const struct device * dev)535 static int gpio_max22190_init(const struct device *dev)
536 {
537 const struct max22190_config *config = dev->config;
538 struct max22190_data *data = dev->data;
539
540 LOG_DBG("GPIO MAX22190 init IN\n");
541
542 int err = 0;
543
544 if (!spi_is_ready_dt(&config->spi)) {
545 LOG_ERR("SPI bus is not ready\n");
546 return -ENODEV;
547 }
548
549 /* setup READY gpio - normal low */
550 if (!gpio_is_ready_dt(&config->ready_gpio)) {
551 LOG_ERR("READY GPIO device not ready");
552 return -ENODEV;
553 }
554
555 err = gpio_pin_configure_dt(&config->ready_gpio, GPIO_INPUT);
556 if (err < 0) {
557 LOG_ERR("Failed to configure reset GPIO");
558 return err;
559 }
560
561 /* setup FAULT gpio - normal high */
562 if (!gpio_is_ready_dt(&config->fault_gpio)) {
563 LOG_ERR("FAULT GPIO device not ready");
564 return -ENODEV;
565 }
566
567 err = gpio_pin_configure_dt(&config->fault_gpio, GPIO_INPUT | GPIO_PULL_UP);
568 if (err < 0) {
569 LOG_ERR("Failed to configure DC GPIO");
570 return err;
571 }
572
573 /* setup LATCH gpio - normal high */
574 if (!gpio_is_ready_dt(&config->latch_gpio)) {
575 LOG_ERR("LATCH GPIO device not ready");
576 return -ENODEV;
577 }
578
579 err = gpio_pin_configure_dt(&config->latch_gpio, GPIO_OUTPUT_INACTIVE);
580 if (err < 0) {
581 LOG_ERR("Failed to configure busy GPIO");
582 return err;
583 }
584
585 for (int i = 0; i < 8; i++) {
586 LOG_DBG("IN%d WBE [%d] FBP[%d] DELAY[%d]\n", i,
587 config->filter[i].reg_bits.max22190_WBE,
588 config->filter[i].reg_bits.max22190_FBP,
589 config->filter[i].reg_bits.max22190_DELAY);
590 }
591
592 LOG_DBG(" > MAX22190 MODE: %x", config->mode);
593 LOG_DBG(" > MAX22190 PKT SIZE: %dbits (%dbytes)", config->pkt_size * 8, config->pkt_size);
594 LOG_DBG(" > MAX22190 CRC: %s", config->crc_en ? "enable" : "disable");
595
596 data->fault1_en.reg_bits.max22190_WBGE = 1;
597 data->fault1_en.reg_bits.max22190_PORE = 1;
598
599 /* Set all FAULT and FAULT_EN regs */
600 max22190_fault_set(dev);
601
602 /* Set channels filters */
603 max22190_filter_set(dev);
604
605 /* POR bit need to be cleared after start */
606 MAX22190_CLEAN_POR(dev);
607
608 LOG_DBG("GPIO MAX22190 init OUT\n");
609 return 0;
610 }
611
612 static DEVICE_API(gpio, gpio_max22190_api) = {
613 .pin_configure = gpio_max22190_config,
614 .port_get_raw = gpio_max22190_port_get_raw,
615 };
616
617 /* Assign appropriate value for FILTER delay*/
618 #define MAX22190_FILTER_SET_DELAY(delay) \
619 delay == 20000 ? MAX22190_DELAY_20000US \
620 : delay == 12800 ? MAX22190_DELAY_12800US \
621 : delay == 3200 ? MAX22190_DELAY_3200US \
622 : delay == 1600 ? MAX22190_DELAY_1800US \
623 : delay == 800 ? MAX22190_DELAY_800US \
624 : delay == 400 ? MAX22190_DELAY_400US \
625 : delay == 100 ? MAX22190_DELAY_100US \
626 : delay == 50 ? MAX22190_DELAY_50US \
627 : MAX22190_DELAY_20000US
628
629 /* Set FILTERx reg */
630 #define MAX22190_FILTER_BY_IDX(id, idx) \
631 { \
632 .reg_bits.max22190_DELAY = \
633 MAX22190_FILTER_SET_DELAY(DT_INST_PROP_BY_IDX(id, filter_delays, idx)), \
634 .reg_bits.max22190_FBP = DT_INST_PROP_BY_IDX(id, filter_fbps, idx), \
635 .reg_bits.max22190_WBE = DT_INST_PROP_BY_IDX(id, filter_wbes, idx), \
636 }
637
638 #define GPIO_MAX22190_DEVICE(id) \
639 static const struct max22190_config max22190_##id##_cfg = { \
640 .spi = SPI_DT_SPEC_INST_GET(id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U), \
641 .ready_gpio = GPIO_DT_SPEC_INST_GET(id, drdy_gpios), \
642 .fault_gpio = GPIO_DT_SPEC_INST_GET(id, fault_gpios), \
643 .latch_gpio = GPIO_DT_SPEC_INST_GET(id, latch_gpios), \
644 .mode = DT_INST_PROP(id, max22190_mode), \
645 .crc_en = !(DT_INST_PROP(id, max22190_mode) & 0x1), \
646 .pkt_size = !(DT_INST_PROP(id, max22190_mode) & 0x1) ? 3 : 2, \
647 .filter = \
648 { \
649 MAX22190_FILTER_BY_IDX(id, 0), \
650 MAX22190_FILTER_BY_IDX(id, 1), \
651 MAX22190_FILTER_BY_IDX(id, 2), \
652 MAX22190_FILTER_BY_IDX(id, 3), \
653 MAX22190_FILTER_BY_IDX(id, 4), \
654 MAX22190_FILTER_BY_IDX(id, 5), \
655 MAX22190_FILTER_BY_IDX(id, 6), \
656 MAX22190_FILTER_BY_IDX(id, 7), \
657 }, \
658 }; \
659 \
660 static struct max22190_data max22190_##id##_data; \
661 \
662 DEVICE_DT_INST_DEFINE(id, &gpio_max22190_init, NULL, &max22190_##id##_data, \
663 &max22190_##id##_cfg, POST_KERNEL, \
664 CONFIG_GPIO_MAX22190_INIT_PRIORITY, &gpio_max22190_api);
665
666 DT_INST_FOREACH_STATUS_OKAY(GPIO_MAX22190_DEVICE)
667
