1 /*
2 * Copyright (c) 2024 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @brief Microchip MEC5 ns16550 compatible UART Serial Driver
9 */
10
11 #define DT_DRV_COMPAT microchip_mec5_uart
12
13 #include <errno.h>
14 #include <zephyr/devicetree.h>
15 #include <zephyr/drivers/gpio.h>
16 #include <zephyr/drivers/uart.h>
17 #include <zephyr/drivers/pinctrl.h>
18 #include <zephyr/irq.h>
19 #include <zephyr/kernel.h>
20 #include <zephyr/logging/log.h>
21 #include <zephyr/spinlock.h>
22 #include <zephyr/sys/byteorder.h>
23
24 LOG_MODULE_REGISTER(uart_mec5, CONFIG_UART_LOG_LEVEL);
25
26 /* MEC5 HAL */
27 #include <device_mec5.h>
28 #include <mec_ecia_api.h>
29 #include <mec_uart_api.h>
30
31 #define UART_MEC_DFLT_CLK_FREQ 1843200u
32 #define UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_POS 0
33 #define UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_MSK 0x3u
34 #define UART_MEC_DEVCFG_FLAG_FIFO_DIS_POS 4
35 #define UART_MEC_DEVCFG_FLAG_USE_EXTCLK_POS 5
36
37 struct uart_mec5_devcfg {
38 struct mec_uart_regs *regs;
39 const struct pinctrl_dev_config *pcfg;
40 uint32_t clock_freq;
41 uint32_t flags;
42 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
43 void (*irq_config_func)(const struct device *dev);
44 #endif
45 };
46
47 struct uart_mec5_dev_data {
48 const struct device *dev;
49 struct uart_config current_config;
50 struct uart_config ucfg;
51 struct k_spinlock lock;
52 enum mec_uart_ipend ipend;
53 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
54 uart_irq_callback_user_data_t cb; /* Callback function pointer */
55 void *cb_data; /* Callback function arg */
56 uint32_t flags;
57 uint8_t rx_enabled;
58 uint8_t tx_enabled;
59 #endif
60 };
61
62 static const uint8_t mec5_xlat_word_len[4] = {
63 MEC_UART_WORD_LEN_5,
64 MEC_UART_WORD_LEN_6,
65 MEC_UART_WORD_LEN_7,
66 MEC_UART_WORD_LEN_8,
67 };
68
69 static const uint8_t mec5_xlat_stop_bits[4] = {
70 MEC_UART_STOP_BITS_1,
71 MEC_UART_STOP_BITS_1,
72 MEC_UART_STOP_BITS_2,
73 MEC_UART_STOP_BITS_2,
74 };
75
76 static const uint8_t mec5_xlat_parity[5] = {
77 (uint8_t)(MEC5_UART_CFG_PARITY_NONE >> MEC5_UART_CFG_PARITY_POS),
78 (uint8_t)(MEC5_UART_CFG_PARITY_ODD >> MEC5_UART_CFG_PARITY_POS),
79 (uint8_t)(MEC5_UART_CFG_PARITY_EVEN >> MEC5_UART_CFG_PARITY_POS),
80 (uint8_t)(MEC5_UART_CFG_PARITY_MARK >> MEC5_UART_CFG_PARITY_POS),
81 (uint8_t)(MEC5_UART_CFG_PARITY_SPACE >> MEC5_UART_CFG_PARITY_POS),
82 };
83
uart_mec5_xlat_cfg(const struct uart_config * cfg,uint32_t * cfg_word)84 static int uart_mec5_xlat_cfg(const struct uart_config *cfg, uint32_t *cfg_word)
85 {
86 uint32_t temp;
87
88 if (!cfg || !cfg_word) {
89 return -EINVAL;
90 }
91
92 *cfg_word = 0u;
93
94 if (cfg->data_bits > UART_CFG_DATA_BITS_8) {
95 return -EINVAL;
96 }
97 temp = mec5_xlat_word_len[cfg->data_bits];
98 *cfg_word |= ((temp << MEC5_UART_CFG_WORD_LEN_POS) & MEC5_UART_CFG_WORD_LEN_MSK);
99
100 if (cfg->stop_bits > UART_CFG_STOP_BITS_2) {
101 return -EINVAL;
102 }
103 temp = mec5_xlat_stop_bits[cfg->stop_bits];
104 *cfg_word |= ((temp << MEC5_UART_CFG_STOP_BITS_POS) & MEC5_UART_CFG_STOP_BITS_MSK);
105
106 if (cfg->parity > UART_CFG_PARITY_SPACE) {
107 return -EINVAL;
108 }
109 temp = mec5_xlat_parity[cfg->parity];
110 *cfg_word |= ((temp << MEC5_UART_CFG_PARITY_POS) & MEC5_UART_CFG_PARITY_MSK);
111
112 return 0;
113 }
114
115 /* Configure UART TX and RX FIFOs based on device tree.
116 * Both FIFOs are fixed 16-byte.
117 * RX FIFO has a configurable interrupt trigger level of 1, 4, 8, or 14 bytes.
118 */
uart_mec5_fifo_config(uint32_t mcfg,uint32_t cfg_flags)119 static uint32_t uart_mec5_fifo_config(uint32_t mcfg, uint32_t cfg_flags)
120 {
121 uint32_t new_mcfg = mcfg;
122 uint32_t temp = 0;
123
124 if (!(cfg_flags & BIT(UART_MEC_DEVCFG_FLAG_FIFO_DIS_POS))) {
125 new_mcfg |= BIT(MEC5_UART_CFG_FIFO_EN_POS);
126 temp = (cfg_flags & UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_MSK) >>
127 UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_POS;
128 switch (temp) {
129 case 0:
130 new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_1;
131 break;
132 case 1:
133 new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_4;
134 break;
135 case 2:
136 new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_8;
137 break;
138 default:
139 new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_14;
140 break;
141 }
142 }
143
144 return new_mcfg;
145 }
146
config_mec5_uart(const struct device * dev,const struct uart_config * cfg)147 static int config_mec5_uart(const struct device *dev, const struct uart_config *cfg)
148 {
149 const struct uart_mec5_devcfg *devcfg = dev->config;
150 struct mec_uart_regs *const regs = devcfg->regs;
151 struct uart_mec5_dev_data *const data = dev->data;
152 int ret = 0;
153 uint32_t mcfg = 0, extclk = 0;
154
155 data->ipend = MEC_UART_IPEND_NONE;
156
157 ret = uart_mec5_xlat_cfg(cfg, &mcfg);
158 if (ret) {
159 return ret;
160 }
161
162 mcfg = uart_mec5_fifo_config(mcfg, devcfg->flags);
163 mcfg |= BIT(MEC5_UART_CFG_GIRQ_EN_POS);
164
165 if (devcfg->flags & BIT(UART_MEC_DEVCFG_FLAG_USE_EXTCLK_POS)) {
166 extclk = devcfg->clock_freq;
167 }
168
169 ret = mec_hal_uart_init(regs, cfg->baudrate, mcfg, extclk);
170 if (ret != MEC_RET_OK) {
171 return -EIO;
172 }
173
174 memcpy(&data->ucfg, cfg, sizeof(struct uart_config));
175
176 return ret;
177 };
178
179 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
180 /* run-time driver configuration API */
uart_mec5_configure(const struct device * dev,const struct uart_config * cfg)181 static int uart_mec5_configure(const struct device *dev, const struct uart_config *cfg)
182 {
183 const struct uart_mec5_devcfg *devcfg = dev->config;
184 struct uart_mec5_dev_data *const data = dev->data;
185 int ret = 0;
186 k_spinlock_key_t key = k_spin_lock(&data->lock);
187
188 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
189 if (ret) {
190 LOG_ERR("MEC5 UART pinctrl error (%d)", ret);
191 }
192
193 ret = config_mec5_uart(dev, cfg);
194 if (ret) {
195 LOG_ERR("MEC5 UART config error (%d)", ret);
196 return ret;
197 }
198
199 data->current_config = *cfg;
200
201 k_spin_unlock(&data->lock, key);
202
203 return ret;
204 }
205
uart_mec5_config_get(const struct device * dev,struct uart_config * cfg)206 static int uart_mec5_config_get(const struct device *dev, struct uart_config *cfg)
207 {
208 struct uart_mec5_dev_data *const data = dev->data;
209
210 if (!cfg) {
211 return -EINVAL;
212 }
213
214 k_spinlock_key_t key = k_spin_lock(&data->lock);
215
216 *cfg = data->current_config;
217
218 k_spin_unlock(&data->lock, key);
219
220 return 0;
221 }
222 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
223
224 /* Called by kernel during driver initialization phase */
uart_mec5_init(const struct device * dev)225 static int uart_mec5_init(const struct device *dev)
226 {
227 const struct uart_mec5_devcfg *devcfg = dev->config;
228 struct uart_mec5_dev_data *data = dev->data;
229 int ret = 0;
230
231 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
232 if (ret) {
233 LOG_ERR("MEC5 UART init pinctrl error (%d)", ret);
234 return ret;
235 }
236
237 ret = config_mec5_uart(dev, &data->ucfg);
238 if (ret != 0) {
239 return -EIO;
240 }
241
242 return ret;
243 }
244
245 /*
246 * Poll the UART for input.
247 * return 0 is a byte arrived else -1 if no data.
248 */
uart_mec5_poll_in(const struct device * dev,unsigned char * cptr)249 static int uart_mec5_poll_in(const struct device *dev, unsigned char *cptr)
250 {
251 const struct uart_mec5_devcfg *devcfg = dev->config;
252 struct mec_uart_regs *const regs = devcfg->regs;
253 struct uart_mec5_dev_data *data = dev->data;
254 k_spinlock_key_t key = k_spin_lock(&data->lock);
255 int ret = 0;
256
257 ret = mec_hal_uart_rx_byte(regs, (uint8_t *)cptr);
258 if (ret == MEC_RET_ERR_NO_DATA) {
259 k_spin_unlock(&data->lock, key);
260 return -1;
261 }
262
263 k_spin_unlock(&data->lock, key);
264
265 return 0;
266 }
267
268 /* Block until UART can accept data byte. */
uart_mec5_poll_out(const struct device * dev,unsigned char out_data)269 static void uart_mec5_poll_out(const struct device *dev, unsigned char out_data)
270 {
271 const struct uart_mec5_devcfg *devcfg = dev->config;
272 struct mec_uart_regs *const regs = devcfg->regs;
273 struct uart_mec5_dev_data *data = dev->data;
274 k_spinlock_key_t key = k_spin_lock(&data->lock);
275 int ret = 0;
276
277 do {
278 ret = mec_hal_uart_tx_byte(regs, (uint8_t)out_data);
279 } while (ret == MEC_RET_ERR_BUSY);
280
281 k_spin_unlock(&data->lock, key);
282 }
283
284 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
irq_tx_enable(const struct device * dev)285 static inline void irq_tx_enable(const struct device *dev)
286 {
287 const struct uart_mec5_devcfg *devcfg = dev->config;
288 struct mec_uart_regs *const regs = devcfg->regs;
289 struct uart_mec5_dev_data *data = dev->data;
290 k_spinlock_key_t key = k_spin_lock(&data->lock);
291
292 mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ETHREI, MEC_UART_IEN_FLAG_ETHREI);
293
294 k_spin_unlock(&data->lock, key);
295 }
296
irq_tx_disable(const struct device * dev)297 static inline void irq_tx_disable(const struct device *dev)
298 {
299 const struct uart_mec5_devcfg *devcfg = dev->config;
300 struct uart_mec5_dev_data *data = dev->data;
301 struct mec_uart_regs *const regs = devcfg->regs;
302 k_spinlock_key_t key = k_spin_lock(&data->lock);
303
304 mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ETHREI, 0);
305
306 k_spin_unlock(&data->lock, key);
307 }
308
irq_rx_enable(const struct device * dev)309 static inline void irq_rx_enable(const struct device *dev)
310 {
311 const struct uart_mec5_devcfg *const devcfg = dev->config;
312 struct uart_mec5_dev_data *data = dev->data;
313 struct mec_uart_regs *const regs = devcfg->regs;
314 k_spinlock_key_t key = k_spin_lock(&data->lock);
315
316 mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ERDAI, MEC_UART_IEN_FLAG_ERDAI);
317
318 k_spin_unlock(&data->lock, key);
319 }
320
irq_rx_disable(const struct device * dev)321 static inline void irq_rx_disable(const struct device *dev)
322 {
323 const struct uart_mec5_devcfg *const devcfg = dev->config;
324 struct uart_mec5_dev_data *data = dev->data;
325 struct mec_uart_regs *const regs = devcfg->regs;
326 k_spinlock_key_t key = k_spin_lock(&data->lock);
327
328 mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ERDAI, 0);
329
330 k_spin_unlock(&data->lock, key);
331 }
332
uart_mec5_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)333 static int uart_mec5_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
334 {
335 const struct uart_mec5_devcfg *const devcfg = dev->config;
336 struct uart_mec5_dev_data *data = dev->data;
337 struct mec_uart_regs *const regs = devcfg->regs;
338 int num_tx = 0, ret = 0;
339
340 if (len < 0) {
341 return 0;
342 }
343
344 k_spinlock_key_t key = k_spin_lock(&data->lock);
345
346 while (num_tx < len) {
347 ret = mec_hal_uart_tx_byte(regs, tx_data[num_tx]);
348 if (ret == MEC_RET_ERR_BUSY) {
349 break;
350 }
351 num_tx++;
352 }
353
354 if (data->tx_enabled) {
355 irq_tx_enable(dev);
356 }
357
358 k_spin_unlock(&data->lock, key);
359
360 return num_tx;
361 }
362
uart_mec5_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)363 static int uart_mec5_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
364 {
365 const struct uart_mec5_devcfg *const devcfg = dev->config;
366 struct uart_mec5_dev_data *data = dev->data;
367 struct mec_uart_regs *const regs = devcfg->regs;
368 int num_rx = 0, ret = 0;
369
370 if (size < 0) {
371 return 0;
372 }
373
374 k_spinlock_key_t key = k_spin_lock(&data->lock);
375 uint8_t *pdata = rx_data;
376
377 while (num_rx < size) {
378 ret = mec_hal_uart_rx_byte(regs, pdata);
379 if (ret != MEC_RET_OK) {
380 break;
381 }
382 pdata++;
383 num_rx++;
384 }
385
386 if (data->rx_enabled) {
387 irq_rx_enable(dev);
388 }
389
390 k_spin_unlock(&data->lock, key);
391
392 return num_rx;
393 }
394
uart_mec5_irq_tx_enable(const struct device * dev)395 static void uart_mec5_irq_tx_enable(const struct device *dev)
396 {
397 struct uart_mec5_dev_data *data = dev->data;
398 k_spinlock_key_t key = k_spin_lock(&data->lock);
399
400 data->tx_enabled = 1;
401 irq_tx_enable(dev);
402
403 k_spin_unlock(&data->lock, key);
404 }
405
uart_mec5_irq_tx_disable(const struct device * dev)406 static void uart_mec5_irq_tx_disable(const struct device *dev)
407 {
408 struct uart_mec5_dev_data *data = dev->data;
409 k_spinlock_key_t key = k_spin_lock(&data->lock);
410
411 irq_tx_disable(dev);
412 data->tx_enabled = 0;
413
414 k_spin_unlock(&data->lock, key);
415 }
416
uart_mec5_irq_tx_ready(const struct device * dev)417 static int uart_mec5_irq_tx_ready(const struct device *dev)
418 {
419 struct uart_mec5_dev_data *data = dev->data;
420 k_spinlock_key_t key = k_spin_lock(&data->lock);
421 int ret = 0;
422
423 if (data->ipend == MEC_UART_IPEND_TX) {
424 ret = 1;
425 }
426
427 k_spin_unlock(&data->lock, key);
428
429 return ret;
430 }
431
uart_mec5_irq_rx_enable(const struct device * dev)432 static void uart_mec5_irq_rx_enable(const struct device *dev)
433 {
434 struct uart_mec5_dev_data *data = dev->data;
435 k_spinlock_key_t key = k_spin_lock(&data->lock);
436
437 data->rx_enabled = 1;
438 irq_rx_enable(dev);
439
440 k_spin_unlock(&data->lock, key);
441 }
442
uart_mec5_irq_rx_disable(const struct device * dev)443 static void uart_mec5_irq_rx_disable(const struct device *dev)
444 {
445 struct uart_mec5_dev_data *data = dev->data;
446 k_spinlock_key_t key = k_spin_lock(&data->lock);
447
448 irq_rx_disable(dev);
449 data->rx_enabled = 0;
450
451 k_spin_unlock(&data->lock, key);
452 }
453
454 /* check if UART TX shift register is empty. Empty TX shift register indicates
455 * the UART does not need clocks and can be put into a low power state.
456 * return 1 nothing remains to be transmitted, 0 otherwise.
457 */
uart_mec5_irq_tx_complete(const struct device * dev)458 static int uart_mec5_irq_tx_complete(const struct device *dev)
459 {
460 const struct uart_mec5_devcfg *const devcfg = dev->config;
461 struct mec_uart_regs *const regs = devcfg->regs;
462 struct uart_mec5_dev_data *data = dev->data;
463 k_spinlock_key_t key = k_spin_lock(&data->lock);
464 int ret = mec_hal_uart_is_tx_empty(regs);
465
466 k_spin_unlock(&data->lock, key);
467
468 return ret;
469 }
470
uart_mec5_irq_rx_ready(const struct device * dev)471 static int uart_mec5_irq_rx_ready(const struct device *dev)
472 {
473 struct uart_mec5_dev_data *data = dev->data;
474 int ret = 0;
475 k_spinlock_key_t key = k_spin_lock(&data->lock);
476
477 if (data->ipend == MEC_UART_IPEND_RX_DATA) {
478 ret = 1;
479 }
480
481 k_spin_unlock(&data->lock, key);
482
483 return ret;
484 }
485
irq_error_enable(const struct device * dev,uint8_t enable)486 static void irq_error_enable(const struct device *dev, uint8_t enable)
487 {
488 const struct uart_mec5_devcfg *const devcfg = dev->config;
489 struct mec_uart_regs *const regs = devcfg->regs;
490 uint8_t msk = 0;
491
492 if (enable) {
493 msk = MEC_UART_IEN_FLAG_ELSI;
494 }
495
496 mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ELSI, msk);
497 }
498
499 /*
500 * Enable received line status interrupt active when one or more of the following errors
501 * occur: overrun, parity, framing, or break.
502 */
uart_mec5_irq_err_enable(const struct device * dev)503 static void uart_mec5_irq_err_enable(const struct device *dev)
504 {
505 struct uart_mec5_dev_data *data = dev->data;
506 k_spinlock_key_t key = k_spin_lock(&data->lock);
507
508 irq_error_enable(dev, 1u);
509
510 k_spin_unlock(&data->lock, key);
511 }
512
uart_mec5_irq_err_disable(const struct device * dev)513 static void uart_mec5_irq_err_disable(const struct device *dev)
514 {
515 struct uart_mec5_dev_data *data = dev->data;
516 k_spinlock_key_t key = k_spin_lock(&data->lock);
517
518 irq_error_enable(dev, 0);
519
520 k_spin_unlock(&data->lock, key);
521 }
522
uart_mec5_irq_is_pending(const struct device * dev)523 static int uart_mec5_irq_is_pending(const struct device *dev)
524 {
525 struct uart_mec5_dev_data *data = dev->data;
526 k_spinlock_key_t key = k_spin_lock(&data->lock);
527 int ret = 0;
528
529 if (data->ipend != MEC_UART_IPEND_NONE) {
530 ret = 1;
531 }
532
533 k_spin_unlock(&data->lock, key);
534
535 return ret;
536 }
537
uart_mec5_irq_update(const struct device * dev)538 static int uart_mec5_irq_update(const struct device *dev)
539 {
540 const struct uart_mec5_devcfg *const devcfg = dev->config;
541 struct mec_uart_regs *const regs = devcfg->regs;
542 struct uart_mec5_dev_data *data = dev->data;
543 k_spinlock_key_t key = k_spin_lock(&data->lock);
544
545 data->ipend = MEC_UART_IPEND_NONE;
546 mec_hal_uart_pending_status(regs, &data->ipend);
547
548 switch (data->ipend) {
549 case MEC_UART_IPEND_NONE:
550 break;
551 case MEC_UART_IPEND_TX:
552 irq_tx_disable(dev);
553 break;
554 case MEC_UART_IPEND_RX_DATA:
555 irq_rx_disable(dev);
556 break;
557 case MEC_UART_IPEND_RX_ERR:
558 irq_error_enable(dev, 0);
559 break;
560 case MEC_UART_IPEND_MODEM:
561 __fallthrough; /* fall through */
562 default:
563 k_panic();
564 break;
565 }
566
567 k_spin_unlock(&data->lock, key);
568
569 return 1;
570 }
571
uart_mec5_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)572 static void uart_mec5_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
573 void *cb_data)
574 {
575 struct uart_mec5_dev_data *data = dev->data;
576 k_spinlock_key_t key = k_spin_lock(&data->lock);
577
578 data->cb = cb;
579 data->cb_data = cb_data;
580
581 k_spin_unlock(&data->lock, key);
582 }
583
uart_mec5_isr(const struct device * dev)584 static void uart_mec5_isr(const struct device *dev)
585 {
586 struct uart_mec5_dev_data *data = dev->data;
587
588 if (data->cb) {
589 data->cb(dev, data->cb_data);
590 }
591 }
592 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
593
594 static DEVICE_API(uart, uart_mec5_driver_api) = {
595 .poll_in = uart_mec5_poll_in,
596 .poll_out = uart_mec5_poll_out,
597 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
598 .configure = uart_mec5_configure,
599 .config_get = uart_mec5_config_get,
600 #endif
601 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
602 .fifo_fill = uart_mec5_fifo_fill,
603 .fifo_read = uart_mec5_fifo_read,
604 .irq_tx_enable = uart_mec5_irq_tx_enable,
605 .irq_tx_disable = uart_mec5_irq_tx_disable,
606 .irq_tx_ready = uart_mec5_irq_tx_ready,
607 .irq_rx_enable = uart_mec5_irq_rx_enable,
608 .irq_rx_disable = uart_mec5_irq_rx_disable,
609 .irq_tx_complete = uart_mec5_irq_tx_complete,
610 .irq_rx_ready = uart_mec5_irq_rx_ready,
611 .irq_err_enable = uart_mec5_irq_err_enable,
612 .irq_err_disable = uart_mec5_irq_err_disable,
613 .irq_is_pending = uart_mec5_irq_is_pending,
614 .irq_update = uart_mec5_irq_update,
615 .irq_callback_set = uart_mec5_irq_callback_set,
616 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
617 };
618
619 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
620 #define UART_MEC5_CONFIGURE(n) \
621 do { \
622 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_mec5_isr, \
623 DEVICE_DT_INST_GET(n), 0); \
624 \
625 irq_enable(DT_INST_IRQN(n)); \
626 } while (0)
627 #else
628 #define UART_MEC5_CONFIGURE(n)
629 #endif
630
631 #define UART_MEC5_DCFG_FLAGS(i) \
632 ((DT_INST_ENUM_IDX_OR(i, rx_fifo_trig, 2) & 0x3u) | \
633 ((DT_INST_PROP_OR(i, fifo_mode_disable, 0) & 0x1u) << 4) | \
634 ((DT_INST_PROP_OR(i, use_extclk, 0) & 0x1u) << 5))
635
636 #define DEV_DATA_FLOW_CTRL(n) DT_INST_PROP_OR(n, hw_flow_control, UART_CFG_FLOW_CTRL_NONE)
637
638 #define UART_MEC5_DEVICE(i) \
639 PINCTRL_DT_INST_DEFINE(i); \
640 static const struct uart_mec5_devcfg uart_mec5_##i##_devcfg = { \
641 .regs = (struct mec_uart_regs *)DT_INST_REG_ADDR(i), \
642 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
643 .clock_freq = DT_INST_PROP_OR(i, clock_frequency, UART_MEC_DFLT_CLK_FREQ), \
644 .flags = UART_MEC5_DCFG_FLAGS(i), \
645 }; \
646 static struct uart_mec5_dev_data uart_mec5_##i##_dev_data = { \
647 .ucfg.baudrate = DT_INST_PROP_OR(i, current_speed, 0), \
648 .ucfg.parity = UART_CFG_PARITY_NONE, \
649 .ucfg.stop_bits = UART_CFG_STOP_BITS_1, \
650 .ucfg.data_bits = UART_CFG_DATA_BITS_8, \
651 .ucfg.flow_ctrl = DEV_DATA_FLOW_CTRL(i), \
652 }; \
653 static int uart_mec5_##i##_init(const struct device *dev) \
654 { \
655 UART_MEC5_CONFIGURE(i); \
656 return uart_mec5_init(dev); \
657 } \
658 DEVICE_DT_INST_DEFINE(i, uart_mec5_##i##_init, NULL, &uart_mec5_##i##_dev_data, \
659 &uart_mec5_##i##_devcfg, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
660 &uart_mec5_driver_api);
661
662 DT_INST_FOREACH_STATUS_OKAY(UART_MEC5_DEVICE)
663
