1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #define DT_DRV_COMPAT ite_it8xxx2_timer
7
8 #include <zephyr/init.h>
9 #include <zephyr/drivers/timer/system_timer.h>
10 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
11 #include <soc.h>
12 #include <zephyr/spinlock.h>
13 #include <zephyr/sys_clock.h>
14
15 #include <zephyr/logging/log.h>
16 #include <zephyr/irq.h>
17 LOG_MODULE_REGISTER(timer, LOG_LEVEL_ERR);
18
19 #define COUNT_1US (EC_FREQ / USEC_PER_SEC - 1)
20
21 BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
22 "ITE RTOS timer HW frequency is fixed at 32768Hz");
23
24 /* Event timer configurations */
25 #define EVENT_TIMER EXT_TIMER_3
26 #define EVENT_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 0, irq)
27 #define EVENT_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 0, flags)
28 /* Event timer max count is 512 sec (base on clock source 32768Hz) */
29 #define EVENT_TIMER_MAX_CNT 0x00FFFFFFUL
30
31 /* Busy wait low timer configurations */
32 #define BUSY_WAIT_L_TIMER EXT_TIMER_5
33 #define BUSY_WAIT_L_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 2, irq)
34 #define BUSY_WAIT_L_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 2, flags)
35
36 /* Busy wait high timer configurations */
37 #define BUSY_WAIT_H_TIMER EXT_TIMER_6
38 #define BUSY_WAIT_H_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 3, irq)
39 #define BUSY_WAIT_H_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 3, flags)
40 /* Busy wait high timer max count is 71.58min (base on clock source 1MHz) */
41 #define BUSY_WAIT_TIMER_H_MAX_CNT 0xFFFFFFFFUL
42
43 #if defined(CONFIG_TEST)
44 const int32_t z_sys_timer_irq_for_test = DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, irq);
45 #endif
46
47 #ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
48 /*
49 * One shot timer configurations
50 *
51 * NOTE: Timer1/2 register address isn't regular like timer3/4/5/6/7/8, and
52 * timer1 is used for printing watchdog warning message. So now we use
53 * timer2 only one shot to wake up chip and change pll.
54 */
55 #define WDT_BASE DT_REG_ADDR(DT_NODELABEL(twd0))
56 #define WDT_REG (struct wdt_it8xxx2_regs *)(WDT_BASE)
57 #define ONE_SHOT_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, irq)
58 #define ONE_SHOT_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, flags)
59 #endif
60
61 #define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
62 /*
63 * One system (kernel) tick is as how much HW timer counts
64 *
65 * NOTE: Event and free run timer individually select the same clock source
66 * frequency, so they can use the same HW_CNT_PER_SYS_TICK to transform
67 * unit between HW count and system tick. If clock source frequency is
68 * different, then we should define another to transform.
69 */
70 #define HW_CNT_PER_SYS_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
71 / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
72 /* Event timer max count is as how much system (kernel) tick */
73 #define EVEN_TIMER_MAX_CNT_SYS_TICK (EVENT_TIMER_MAX_CNT \
74 / HW_CNT_PER_SYS_TICK)
75
76 static struct k_spinlock lock;
77 /* Last HW count that we called sys_clock_announce() */
78 static volatile uint32_t last_announced_hw_cnt;
79 /* Last system (kernel) elapse and ticks */
80 static volatile uint32_t last_elapsed;
81 static volatile uint32_t last_ticks;
82
83 enum ext_timer_raw_cnt {
84 EXT_NOT_RAW_CNT = 0,
85 EXT_RAW_CNT,
86 };
87
88 enum ext_timer_init {
89 EXT_NOT_FIRST_TIME_ENABLE = 0,
90 EXT_FIRST_TIME_ENABLE,
91 };
92
93 enum ext_timer_int {
94 EXT_WITHOUT_TIMER_INT = 0,
95 EXT_WITH_TIMER_INT,
96 };
97
98 enum ext_timer_start {
99 EXT_NOT_START_TIMER = 0,
100 EXT_START_TIMER,
101 };
102
103 #ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
timer_5ms_one_shot_isr(const void * unused)104 static void timer_5ms_one_shot_isr(const void *unused)
105 {
106 ARG_UNUSED(unused);
107
108 /*
109 * We are here because we have completed changing PLL sequence,
110 * so disabled one shot timer interrupt.
111 */
112 irq_disable(ONE_SHOT_TIMER_IRQ);
113 }
114
115 /*
116 * This timer is used to wake up chip from sleep mode to complete
117 * changing PLL sequence.
118 */
timer_5ms_one_shot(void)119 void timer_5ms_one_shot(void)
120 {
121 struct wdt_it8xxx2_regs *const timer2_reg = WDT_REG;
122 uint32_t hw_cnt;
123
124 /* Initialize interrupt handler of one shot timer */
125 IRQ_CONNECT(ONE_SHOT_TIMER_IRQ, 0, timer_5ms_one_shot_isr, NULL,
126 ONE_SHOT_TIMER_FLAG);
127
128 /* Set rising edge triggered of one shot timer */
129 ite_intc_irq_polarity_set(ONE_SHOT_TIMER_IRQ, ONE_SHOT_TIMER_FLAG);
130
131 /* Clear interrupt status of one shot timer */
132 ite_intc_isr_clear(ONE_SHOT_TIMER_IRQ);
133
134 /* Set clock source of one shot timer */
135 timer2_reg->ET2PSR = EXT_PSR_32P768K;
136
137 /*
138 * Set count of one shot timer,
139 * and after write ET2CNTLLR timer will start
140 */
141 hw_cnt = MS_TO_COUNT(32768, 5/*ms*/);
142 timer2_reg->ET2CNTLH2R = (uint8_t)((hw_cnt >> 16) & 0xff);
143 timer2_reg->ET2CNTLHR = (uint8_t)((hw_cnt >> 8) & 0xff);
144 timer2_reg->ET2CNTLLR = (uint8_t)(hw_cnt & 0xff);
145
146 irq_enable(ONE_SHOT_TIMER_IRQ);
147 }
148 #endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
149
150 #ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
arch_busy_wait(uint32_t usec_to_wait)151 void arch_busy_wait(uint32_t usec_to_wait)
152 {
153 uint32_t start = IT8XXX2_EXT_CNTOX(BUSY_WAIT_H_TIMER);
154
155 if (!usec_to_wait) {
156 return;
157 }
158
159 /* Decrease 1us here to calibrate our access registers latency */
160 usec_to_wait--;
161
162 for (;;) {
163 if ((IT8XXX2_EXT_CNTOX(BUSY_WAIT_H_TIMER) - start) >= usec_to_wait) {
164 break;
165 }
166 }
167 }
168 #endif
169
evt_timer_enable(void)170 static void evt_timer_enable(void)
171 {
172 /* Enable and re-start event timer */
173 IT8XXX2_EXT_CTRLX(EVENT_TIMER) |= (IT8XXX2_EXT_ETXEN |
174 IT8XXX2_EXT_ETXRST);
175 }
176
evt_timer_isr(const void * unused)177 static void evt_timer_isr(const void *unused)
178 {
179 ARG_UNUSED(unused);
180
181 /* Disable event timer */
182 IT8XXX2_EXT_CTRLX(EVENT_TIMER) &= ~IT8XXX2_EXT_ETXEN;
183 /* W/C event timer interrupt status */
184 ite_intc_isr_clear(EVENT_TIMER_IRQ);
185
186 if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
187 /*
188 * Get free run observer count from last time announced and
189 * transform unit to system tick
190 */
191 uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
192 last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
193 last_announced_hw_cnt += (dticks * HW_CNT_PER_SYS_TICK);
194 last_ticks += dticks;
195 last_elapsed = 0;
196
197 sys_clock_announce(dticks);
198 } else {
199 /* enable event timer */
200 evt_timer_enable();
201 /* Informs kernel that one system tick has elapsed */
202 sys_clock_announce(1);
203 }
204 }
205
free_run_timer_overflow_isr(const void * unused)206 static void free_run_timer_overflow_isr(const void *unused)
207 {
208 ARG_UNUSED(unused);
209
210 /* Read to clear terminal count flag */
211 __unused uint8_t rc_tc = IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER);
212
213 /*
214 * TODO: to increment 32-bit "top half" here for software 64-bit
215 * timer emulation.
216 */
217 }
218
sys_clock_set_timeout(int32_t ticks,bool idle)219 void sys_clock_set_timeout(int32_t ticks, bool idle)
220 {
221 uint32_t hw_cnt;
222
223 ARG_UNUSED(idle);
224
225 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
226 /* Always return for non-tickless kernel system */
227 return;
228 }
229
230 /* Critical section */
231 k_spinlock_key_t key = k_spin_lock(&lock);
232
233 /* Disable event timer */
234 IT8XXX2_EXT_CTRLX(EVENT_TIMER) &= ~IT8XXX2_EXT_ETXEN;
235
236 if (ticks == K_TICKS_FOREVER) {
237 /*
238 * If kernel doesn't have a timeout:
239 * 1.CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE = y (no future timer interrupts
240 * are expected), kernel pass K_TICKS_FOREVER (0xFFFF FFFF FFFF FFFF),
241 * we handle this case in here.
242 * 2.CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE = n (schedule timeout as far
243 * into the future as possible), kernel pass INT_MAX (0x7FFF FFFF),
244 * we handle it in later else {}.
245 */
246 k_spin_unlock(&lock, key);
247 return;
248 } else {
249 uint32_t next_cycs;
250 uint32_t now;
251 uint32_t dcycles;
252
253 /*
254 * If ticks <= 1 means the kernel wants the tick announced
255 * as soon as possible, ideally no more than one system tick
256 * in the future. So set event timer count to 1 HW tick.
257 */
258 ticks = CLAMP(ticks, 1, (int32_t)EVEN_TIMER_MAX_CNT_SYS_TICK);
259
260 next_cycs = (last_ticks + last_elapsed + ticks) * HW_CNT_PER_SYS_TICK;
261 now = ~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER));
262 if (unlikely(next_cycs <= now)) {
263 hw_cnt = 1;
264 } else {
265 dcycles = next_cycs - now;
266 hw_cnt = MIN(dcycles, EVENT_TIMER_MAX_CNT);
267 }
268 }
269
270 /* Set event timer 24-bit count */
271 IT8XXX2_EXT_CNTX(EVENT_TIMER) = hw_cnt;
272
273 /* W/C event timer interrupt status */
274 ite_intc_isr_clear(EVENT_TIMER_IRQ);
275
276 /* enable event timer */
277 evt_timer_enable();
278
279 k_spin_unlock(&lock, key);
280
281 LOG_DBG("timeout is 0x%x, set hw count 0x%x", ticks, hw_cnt);
282 }
283
sys_clock_elapsed(void)284 uint32_t sys_clock_elapsed(void)
285 {
286 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
287 /* Always return 0 for non-tickless kernel system */
288 return 0;
289 }
290
291 /* Critical section */
292 k_spinlock_key_t key = k_spin_lock(&lock);
293 /*
294 * Get free run observer count from last time announced and transform
295 * unit to system tick
296 */
297 uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
298 last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
299 last_elapsed = dticks;
300
301 k_spin_unlock(&lock, key);
302
303 return dticks;
304 }
305
sys_clock_cycle_get_32(void)306 uint32_t sys_clock_cycle_get_32(void)
307 {
308 /*
309 * Get free run observer count
310 *
311 * NOTE: Timer is counting down from 0xffffffff. In not combined
312 * mode, the observer count value is the same as count, so after
313 * NOT count operation we can get counting up value; In
314 * combined mode, the observer count value is the same as NOT
315 * count operation.
316 */
317 uint32_t dticks = ~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER));
318
319 return dticks;
320 }
321
timer_init(enum ext_timer_idx ext_timer,enum ext_clk_src_sel clock_source_sel,enum ext_timer_raw_cnt raw,uint32_t ms,enum ext_timer_init first_time_enable,uint32_t irq_num,uint32_t irq_flag,enum ext_timer_int with_int,enum ext_timer_start start)322 static int timer_init(enum ext_timer_idx ext_timer,
323 enum ext_clk_src_sel clock_source_sel,
324 enum ext_timer_raw_cnt raw,
325 uint32_t ms,
326 enum ext_timer_init first_time_enable,
327 uint32_t irq_num,
328 uint32_t irq_flag,
329 enum ext_timer_int with_int,
330 enum ext_timer_start start)
331 {
332 uint32_t hw_cnt;
333
334 if (raw == EXT_RAW_CNT) {
335 hw_cnt = ms;
336 } else {
337 if (clock_source_sel == EXT_PSR_32P768K) {
338 hw_cnt = MS_TO_COUNT(32768, ms);
339 } else if (clock_source_sel == EXT_PSR_1P024K) {
340 hw_cnt = MS_TO_COUNT(1024, ms);
341 } else if (clock_source_sel == EXT_PSR_32) {
342 hw_cnt = MS_TO_COUNT(32, ms);
343 } else if (clock_source_sel == EXT_PSR_EC_CLK) {
344 hw_cnt = MS_TO_COUNT(EC_FREQ, ms);
345 } else {
346 LOG_ERR("Timer %d clock source error !", ext_timer);
347 return -1;
348 }
349 }
350
351 if (hw_cnt == 0) {
352 LOG_ERR("Timer %d count shouldn't be 0 !", ext_timer);
353 return -1;
354 }
355
356 if (first_time_enable == EXT_FIRST_TIME_ENABLE) {
357 /* Enable and re-start external timer x */
358 IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
359 IT8XXX2_EXT_ETXRST);
360 /* Disable external timer x */
361 IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
362 }
363
364 /* Set rising edge triggered of external timer x */
365 ite_intc_irq_polarity_set(irq_num, irq_flag);
366
367 /* Clear interrupt status of external timer x */
368 ite_intc_isr_clear(irq_num);
369
370 /* Set clock source of external timer x */
371 IT8XXX2_EXT_PSRX(ext_timer) = clock_source_sel;
372
373 /* Set count of external timer x */
374 IT8XXX2_EXT_CNTX(ext_timer) = hw_cnt;
375
376 /* Disable external timer x */
377 IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
378 if (start == EXT_START_TIMER) {
379 /* Enable and re-start external timer x */
380 IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
381 IT8XXX2_EXT_ETXRST);
382 }
383
384 if (with_int == EXT_WITH_TIMER_INT) {
385 irq_enable(irq_num);
386 } else {
387 irq_disable(irq_num);
388 }
389
390 return 0;
391 }
392
sys_clock_driver_init(void)393 static int sys_clock_driver_init(void)
394 {
395 int ret;
396
397
398 /* Enable 32-bit free run timer overflow interrupt */
399 IRQ_CONNECT(FREE_RUN_TIMER_IRQ, 0, free_run_timer_overflow_isr, NULL,
400 FREE_RUN_TIMER_FLAG);
401 /* Set 32-bit timer4 for free run*/
402 ret = timer_init(FREE_RUN_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
403 FREE_RUN_TIMER_MAX_CNT, EXT_FIRST_TIME_ENABLE,
404 FREE_RUN_TIMER_IRQ, FREE_RUN_TIMER_FLAG,
405 EXT_WITH_TIMER_INT, EXT_START_TIMER);
406 if (ret < 0) {
407 LOG_ERR("Init free run timer failed");
408 return ret;
409 }
410
411 /* Set 24-bit timer3 for timeout event */
412 IRQ_CONNECT(EVENT_TIMER_IRQ, 0, evt_timer_isr, NULL, EVENT_TIMER_FLAG);
413 if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
414 ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
415 EVENT_TIMER_MAX_CNT, EXT_FIRST_TIME_ENABLE,
416 EVENT_TIMER_IRQ, EVENT_TIMER_FLAG,
417 EXT_WITH_TIMER_INT, EXT_NOT_START_TIMER);
418 } else {
419 /* Start a event timer in one system tick */
420 ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
421 MAX((1 * HW_CNT_PER_SYS_TICK), 1),
422 EXT_FIRST_TIME_ENABLE, EVENT_TIMER_IRQ,
423 EVENT_TIMER_FLAG, EXT_WITH_TIMER_INT,
424 EXT_START_TIMER);
425 }
426 if (ret < 0) {
427 LOG_ERR("Init event timer failed");
428 return ret;
429 }
430
431 if (IS_ENABLED(CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT)) {
432 /* Set timer5 and timer6 combinational mode for busy wait */
433 IT8XXX2_EXT_CTRLX(BUSY_WAIT_L_TIMER) |= IT8XXX2_EXT_ETXCOMB;
434
435 /* Set 32-bit timer6 to count-- every 1us */
436 ret = timer_init(BUSY_WAIT_H_TIMER, EXT_PSR_EC_CLK, EXT_RAW_CNT,
437 BUSY_WAIT_TIMER_H_MAX_CNT, EXT_FIRST_TIME_ENABLE,
438 BUSY_WAIT_H_TIMER_IRQ, BUSY_WAIT_H_TIMER_FLAG,
439 EXT_WITHOUT_TIMER_INT, EXT_START_TIMER);
440 if (ret < 0) {
441 LOG_ERR("Init busy wait high timer failed");
442 return ret;
443 }
444
445 /*
446 * Set 24-bit timer5 to overflow every 1us
447 * NOTE: When the timer5 count down to overflow in combinational
448 * mode, timer6 counter will automatically decrease one count
449 * and timer5 will automatically re-start counting down
450 * from COUNT_1US. Timer5 clock source is EC_FREQ, so the
451 * time period from COUNT_1US to overflow is
452 * (1 / EC_FREQ) * (EC_FREQ / USEC_PER_SEC) = 1us.
453 */
454 ret = timer_init(BUSY_WAIT_L_TIMER, EXT_PSR_EC_CLK, EXT_RAW_CNT,
455 COUNT_1US, EXT_FIRST_TIME_ENABLE,
456 BUSY_WAIT_L_TIMER_IRQ, BUSY_WAIT_L_TIMER_FLAG,
457 EXT_WITHOUT_TIMER_INT, EXT_START_TIMER);
458 if (ret < 0) {
459 LOG_ERR("Init busy wait low timer failed");
460 return ret;
461 }
462 }
463
464 return 0;
465 }
466
467 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
468 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
469
