1 /*
2  * Copyright (c) 2017 Intel Corporation
3  * Copyright (c) 2025 Espressif Systems (Shanghai) CO LTD.
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #include <soc.h>
9 #include <soc_init.h>
10 #include <flash_init.h>
11 #include <esp_private/cache_utils.h>
12 #include <esp_private/system_internal.h>
13 #include <esp_timer.h>
14 #include <psram.h>
15 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
16 #include <zephyr/sys/printk.h>
17 
18 extern void z_prep_c(void);
19 extern void esp_reset_reason_init(void);
20 
esp_errata(void)21 static void IRAM_ATTR esp_errata(void)
22 {
23 	/* Handle the clock gating fix */
24 	REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
25 	/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
26 	 * signals to ensure that the App core stops running in single-core mode.
27 	 */
28 	REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
29 	REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
30 
31 	/* Handle the Dcache case following the IDF startup code */
32 #if CONFIG_ESP32S3_DATA_CACHE_16KB
33 	Cache_Invalidate_DCache_All();
34 	Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
35 #endif
36 }
37 
__esp_platform_app_start(void)38 void IRAM_ATTR __esp_platform_app_start(void)
39 {
40 	/* Configure the mode of instruction cache : cache size, cache line size. */
41 	esp_config_instruction_cache_mode();
42 
43 	/* If we need use SPIRAM, we should use data cache.
44 	 * Configure the mode of data : cache size, cache line size.
45 	 */
46 	esp_config_data_cache_mode();
47 
48 	/* Apply SoC patches */
49 	esp_errata();
50 
51 	esp_reset_reason_init();
52 
53 	esp_timer_early_init();
54 
55 	esp_flash_config();
56 
57 	esp_intr_initialize();
58 
59 #if CONFIG_ESP_SPIRAM
60 	esp_init_psram();
61 
62 	int err = esp_psram_smh_init();
63 
64 	if (err) {
65 		printk("Failed to initialize PSRAM shared multi heap (%d)\n", err);
66 	}
67 #endif
68 
69 	/* Start Zephyr */
70 	z_prep_c();
71 
72 	CODE_UNREACHABLE;
73 }
74 
__esp_platform_mcuboot_start(void)75 void IRAM_ATTR __esp_platform_mcuboot_start(void)
76 {
77 	esp_intr_initialize();
78 
79 	/* Start Zephyr */
80 	z_prep_c();
81 
82 	CODE_UNREACHABLE;
83 }
84 
85 /* Boot-time static default printk handler, possibly to be overridden later. */
arch_printk_char_out(int c)86 int IRAM_ATTR arch_printk_char_out(int c)
87 {
88 	if (c == '\n') {
89 		esp_rom_uart_tx_one_char('\r');
90 	}
91 	esp_rom_uart_tx_one_char(c);
92 	return 0;
93 }
94 
sys_arch_reboot(int type)95 void sys_arch_reboot(int type)
96 {
97 	esp_restart_noos();
98 }
99