1 /*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <errno.h>
8 #include <zephyr/kernel.h>
9 #include <zephyr/device.h>
10 #include <soc.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/espi.h>
13 #include <zephyr/drivers/spi.h>
14 #include <zephyr/logging/log_ctrl.h>
15 #include <zephyr/logging/log.h>
16 /* OOB operations will be attempted regardless of channel enabled or not */
17 #include "espi_oob_handler.h"
18
19 #ifdef CONFIG_ESPI_TAF
20 #include <zephyr/drivers/espi_saf.h>
21 #endif
22
23 LOG_MODULE_DECLARE(espi, CONFIG_ESPI_LOG_LEVEL);
24
25 /* eSPI flash parameters */
26 #define MAX_TEST_BUF_SIZE 1024u
27 #define MAX_FLASH_REQUEST 64u
28 #define TARGET_FLASH_REGION 0x72000ul
29
30 #define ESPI_FREQ_20MHZ 20u
31 #define ESPI_FREQ_25MHZ 25u
32 #define ESPI_FREQ_66MHZ 66u
33
34 #define K_WAIT_DELAY 100u
35
36 /* eSPI event */
37 #define EVENT_MASK 0x0000FFFFu
38 #define EVENT_DETAILS_MASK 0xFFFF0000u
39 #define EVENT_DETAILS_POS 16u
40 #define EVENT_TYPE(x) (x & EVENT_MASK)
41 #define EVENT_DETAILS(x) ((x & EVENT_DETAILS_MASK) >> EVENT_DETAILS_POS)
42
43 #define PWR_SEQ_TIMEOUT 3000u
44
45 /* The devicetree node identifier for the board power rails pins. */
46 #define BRD_PWR_NODE DT_NODELABEL(board_power)
47
48 #if DT_NODE_HAS_STATUS(BRD_PWR_NODE, okay)
49 static const struct gpio_dt_spec pwrgd_gpio = GPIO_DT_SPEC_GET(BRD_PWR_NODE, pwrg_gpios);
50 static const struct gpio_dt_spec rsm_gpio = GPIO_DT_SPEC_GET(BRD_PWR_NODE, rsm_gpios);
51 #endif
52
53 static const struct device *const espi_dev = DEVICE_DT_GET(DT_NODELABEL(espi0));
54 static struct espi_callback espi_bus_cb;
55 static struct espi_callback vw_rdy_cb;
56 static struct espi_callback vw_cb;
57 static struct espi_callback p80_cb;
58 static uint8_t espi_rst_sts;
59 #ifdef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
60 static struct espi_callback oob_cb;
61 #endif
62
63 #ifdef CONFIG_ESPI_FLASH_CHANNEL
64 static uint8_t flash_write_buf[MAX_TEST_BUF_SIZE];
65 static uint8_t flash_read_buf[MAX_TEST_BUF_SIZE];
66 #endif
67
68 #ifdef CONFIG_ESPI_TAF
69 #define SAF_BASE_ADDR DT_REG_ADDR(DT_NODELABEL(espi_saf0))
70
71 #define SAF_TEST_FREQ_HZ 24000000U
72 #define SAF_TEST_BUF_SIZE 4096U
73
74 /* SPI address of 4KB sector modified by test */
75 #define SAF_SPI_TEST_ADDRESS 0x1000U
76
77 #define SPI_WRITE_STATUS1 0x01U
78 #define SPI_WRITE_STATUS2 0x31U
79 #define SPI_WRITE_DISABLE 0x04U
80 #define SPI_READ_STATUS1 0x05U
81 #define SPI_WRITE_ENABLE 0x06U
82 #define SPI_READ_STATUS2 0x35U
83 #define SPI_WRITE_ENABLE_VS 0x50U
84 #define SPI_READ_JEDEC_ID 0x9FU
85
86 #define SPI_STATUS1_BUSY 0x80U
87 #define SPI_STATUS2_QE 0x02U
88
89 #define W25Q128_JEDEC_ID 0x001840efU
90
91 enum saf_erase_size {
92 SAF_ERASE_4K = 0,
93 SAF_ERASE_32K = 1,
94 SAF_ERASE_64K = 2,
95 SAF_ERASE_MAX
96 };
97
98 struct saf_addr_info {
99 uintptr_t saf_struct_addr;
100 uintptr_t saf_exp_addr;
101 };
102 static const struct device *const qspi_dev = DEVICE_DT_GET(DT_NODELABEL(spi0));
103 static const struct device *const espi_saf_dev = DEVICE_DT_GET(DT_NODELABEL(espi_saf0));
104 static uint8_t safbuf[SAF_TEST_BUF_SIZE] __aligned(4);
105 static uint8_t safbuf2[SAF_TEST_BUF_SIZE] __aligned(4);
106
107 /*
108 * W25Q128 SPI flash SAF configuration.
109 * Size is 16Mbytes, it requires no continuous mode prefix, or
110 * other special SAF configuration.
111 */
112 static const struct espi_saf_flash_cfg flash_w25q128 = {
113 .flashsz = 0x1000000U,
114 .opa = MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U),
115 .opb = MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U),
116 .opc = MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U),
117 .poll2_mask = MCHP_W25Q128_POLL2_MASK,
118 .cont_prefix = 0U,
119 .cs_cfg_descr_ids = MCHP_CS0_CFG_DESCR_IDX_REG_VAL,
120 .flags = 0,
121 .descr = {MCHP_W25Q128_CM_RD_D0, MCHP_W25Q128_CM_RD_D1, MCHP_W25Q128_CM_RD_D2,
122 MCHP_W25Q128_ENTER_CM_D0, MCHP_W25Q128_ENTER_CM_D1, MCHP_W25Q128_ENTER_CM_D2}};
123
124 /*
125 * SAF driver configuration.
126 * One SPI flash device.
127 * Use QMSPI frequency, chip select timing, and signal sampling configured
128 * by QMSPI driver.
129 * Use SAF hardware default TAG map.
130 */
131 #ifdef CONFIG_ESPI_TAF_XEC_V2
132 static const struct espi_saf_cfg saf_cfg1 = {
133 .nflash_devices = 1U,
134 .hwcfg = {.version = 2U, /* TODO */
135 .flags = 0U, /* TODO */
136 .qmspi_cpha = 0U, /* TODO */
137 .qmspi_cs_timing = 0U, /* TODO */
138 .flash_pd_timeout = 0U, /* TODO */
139 .flash_pd_min_interval = 0U, /* TODO */
140 .generic_descr = {MCHP_SAF_EXIT_CM_DESCR12, MCHP_SAF_EXIT_CM_DESCR13,
141 MCHP_SAF_POLL_DESCR14, MCHP_SAF_POLL_DESCR15},
142 .tag_map = {0U, 0U, 0U}},
143 .flash_cfgs = (struct espi_saf_flash_cfg *)&flash_w25q128};
144 #else
145 static const struct espi_saf_cfg saf_cfg1 = {
146 .nflash_devices = 1U,
147 .hwcfg = {.qmspi_freq_hz = 0U,
148 .qmspi_cs_timing = 0U,
149 .qmspi_cpha = 0U,
150 .flags = 0U,
151 .generic_descr = {MCHP_SAF_EXIT_CM_DESCR12, MCHP_SAF_EXIT_CM_DESCR13,
152 MCHP_SAF_POLL_DESCR14, MCHP_SAF_POLL_DESCR15},
153 .tag_map = {0U, 0U, 0U}},
154 .flash_cfgs = (struct espi_saf_flash_cfg *)&flash_w25q128};
155 #endif
156
157 /*
158 * Example for SAF driver set protection regions API.
159 */
160 static const struct espi_saf_pr w25q128_protect_regions[2] = {
161 {
162 .start = 0xe00000U,
163 .size = 0x100000U,
164 .master_bm_we = (1U << MCHP_SAF_MSTR_HOST_PCH_ME),
165 .master_bm_rd = (1U << MCHP_SAF_MSTR_HOST_PCH_ME),
166 .pr_num = 1U,
167 .flags = MCHP_SAF_PR_FLAG_ENABLE | MCHP_SAF_PR_FLAG_LOCK,
168 },
169 {
170 .start = 0xf00000U,
171 .size = 0x100000U,
172 .master_bm_we = (1U << MCHP_SAF_MSTR_HOST_PCH_LAN),
173 .master_bm_rd = (1U << MCHP_SAF_MSTR_HOST_PCH_LAN),
174 .pr_num = 2U,
175 .flags = MCHP_SAF_PR_FLAG_ENABLE | MCHP_SAF_PR_FLAG_LOCK,
176 },
177 };
178
179 static const struct espi_saf_protection saf_pr_w25q128 = {.nregions = 2U,
180 .pregions = w25q128_protect_regions};
181
182 /*
183 * Initialize the local attached SPI flash.
184 * 1. Get SPI driver binding
185 * 2. Read JEDEC ID and verify its a W25Q128
186 * 3. Read STATUS2 and check QE bit
187 * 4. If QE bit is not set
188 * Send volatile status write enable
189 * Set volatile QE bit
190 * Check STATUS1 BUSY, not expected to be set for volatile status write.
191 * Read STATUS2 and check QE
192 * Returns 0 if QE was already set or this routine successfully set volatile
193 * QE. Returns < 0 on SPI driver error or unexpected BUSY or STATUS values.
194 * NOTE: SPI driver transceive API will configure the SPI controller to the
195 * settings passed in the struct spi_config. We set the frequency to the
196 * frequency we will be using for SAF.
197 */
spi_saf_init(void)198 int spi_saf_init(void)
199 {
200 struct spi_config spi_cfg;
201 struct spi_buf_set tx_bufs;
202 struct spi_buf_set rx_bufs;
203 struct spi_buf txb;
204 struct spi_buf rxb;
205 uint8_t spi_status1, spi_status2;
206 uint32_t jedec_id;
207 int ret;
208
209 /* Read JEDEC ID command and fill read buffer */
210 safbuf[0] = SPI_READ_JEDEC_ID;
211 memset(safbuf2, 0x55, 4U);
212
213 spi_cfg.frequency = SAF_TEST_FREQ_HZ;
214 spi_cfg.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8);
215
216 /*
217 * Use SPI master mode and inform driver the SPI controller hardware
218 * controls chip select.
219 */
220 jedec_id = 0U;
221 spi_cfg.slave = 0;
222 spi_cfg.cs.delay = 0;
223 spi_cfg.cs.gpio.pin = 0;
224 spi_cfg.cs.gpio.dt_flags = 0;
225 spi_cfg.cs.gpio.port = NULL;
226
227 txb.buf = &safbuf;
228 txb.len = 1U;
229
230 tx_bufs.buffers = (const struct spi_buf *)&txb;
231 tx_bufs.count = 1U;
232
233 rxb.buf = &jedec_id;
234 rxb.len = 3U;
235
236 rx_bufs.buffers = (const struct spi_buf *)&rxb;
237 rx_bufs.count = 1U;
238
239 ret = spi_transceive(qspi_dev, (const struct spi_config *)&spi_cfg,
240 (const struct spi_buf_set *)&tx_bufs,
241 (const struct spi_buf_set *)&rx_bufs);
242 if (ret) {
243 LOG_ERR("Read JEDEC ID spi_transceive failure: error %d", ret);
244 return ret;
245 }
246
247 if (jedec_id != W25Q128_JEDEC_ID) {
248 LOG_ERR("JEDIC ID does not match W25Q128 %0x", safbuf2[0]);
249 return -1;
250 }
251
252 /* Read STATUS2 to get quad enable bit */
253 safbuf[0] = SPI_READ_STATUS2;
254 memset(safbuf2, 0, 4U);
255
256 txb.buf = &safbuf;
257 txb.len = 1U;
258
259 tx_bufs.buffers = (const struct spi_buf *)&txb;
260 tx_bufs.count = 1U;
261
262 rxb.buf = &safbuf2;
263 rxb.len = 1U;
264
265 rx_bufs.buffers = (const struct spi_buf *)&rxb;
266 rx_bufs.count = 1U;
267
268 ret = spi_transceive(qspi_dev, (const struct spi_config *)&spi_cfg,
269 (const struct spi_buf_set *)&tx_bufs,
270 (const struct spi_buf_set *)&rx_bufs);
271 if (ret) {
272 LOG_ERR("Read STATUS2 spi_transceive failure: error %d", ret);
273 return ret;
274 }
275
276 spi_status2 = safbuf2[0];
277
278 /*
279 * If QE not set then write the volatile QE bit.
280 * SAF test requires SPI flash quad enabled so the WP#/HOLD# signals
281 * will act as IO2/IO3. We will write the volatile QE bit for less
282 * wear of the STATUS2 register
283 */
284 if ((spi_status2 & SPI_STATUS2_QE) == 0U) {
285 safbuf[0] = SPI_WRITE_ENABLE_VS;
286
287 txb.buf = &safbuf;
288 txb.len = 1U;
289
290 tx_bufs.buffers = (const struct spi_buf *)&txb;
291 tx_bufs.count = 1U;
292
293 rx_bufs.buffers = NULL;
294 rx_bufs.count = 0U;
295
296 ret = spi_transceive(qspi_dev, (const struct spi_config *)&spi_cfg,
297 (const struct spi_buf_set *)&tx_bufs,
298 (const struct spi_buf_set *)&rx_bufs);
299 if (ret) {
300 LOG_ERR("Send write enable volatile spi_transceive"
301 " failure: error %d",
302 ret);
303 return ret;
304 }
305
306 safbuf[0] = SPI_WRITE_STATUS2;
307 safbuf[1] = spi_status2 | SPI_STATUS2_QE;
308
309 txb.buf = &safbuf;
310 txb.len = 2U;
311
312 tx_bufs.buffers = (const struct spi_buf *)&txb;
313 tx_bufs.count = 1U;
314
315 rx_bufs.buffers = NULL;
316 rx_bufs.count = 0U;
317
318 ret = spi_transceive(qspi_dev, (const struct spi_config *)&spi_cfg,
319 (const struct spi_buf_set *)&tx_bufs,
320 (const struct spi_buf_set *)&rx_bufs);
321 if (ret) {
322 LOG_ERR("Write SPI STATUS2 QE=1 spi_transceive"
323 " failure: error %d",
324 ret);
325 return ret;
326 }
327
328 /* Write to volatile status is fast, expect BUSY to be clear */
329 safbuf[0] = SPI_READ_STATUS1;
330 memset(safbuf2, 0, 4U);
331
332 txb.buf = &safbuf;
333 txb.len = 1U;
334
335 tx_bufs.buffers = (const struct spi_buf *)&txb;
336 tx_bufs.count = 1U;
337
338 rxb.buf = &safbuf2;
339 /* read 2 bytes both will be STATUS1 */
340 rxb.len = 2U;
341
342 rx_bufs.buffers = (const struct spi_buf *)&rxb;
343 rx_bufs.count = 1U;
344
345 ret = spi_transceive(qspi_dev, (const struct spi_config *)&spi_cfg,
346 (const struct spi_buf_set *)&tx_bufs,
347 (const struct spi_buf_set *)&rx_bufs);
348 if (ret) {
349 LOG_ERR("Read SPI STATUS1 spi_transceive"
350 " failure: error %d",
351 ret);
352 return ret;
353 }
354
355 spi_status1 = safbuf2[0];
356 if (spi_status1 & SPI_STATUS1_BUSY) {
357 LOG_ERR("SPI BUSY set after write to volatile STATUS2:"
358 " STATUS1=0x%02X",
359 spi_status1);
360 return ret;
361 }
362
363 /* Read STATUS2 to make sure QE is set */
364 safbuf[0] = SPI_READ_STATUS2;
365 memset(safbuf2, 0, 4U);
366
367 txb.buf = &safbuf;
368 txb.len = 1U;
369
370 tx_bufs.buffers = (const struct spi_buf *)&txb;
371 tx_bufs.count = 1U;
372
373 rxb.buf = &safbuf2;
374 /* read 2 bytes both will be STATUS2 */
375 rxb.len = 2U;
376
377 rx_bufs.buffers = (const struct spi_buf *)&rxb;
378 rx_bufs.count = 1U;
379
380 ret = spi_transceive(qspi_dev, (const struct spi_config *)&spi_cfg,
381 (const struct spi_buf_set *)&tx_bufs,
382 (const struct spi_buf_set *)&rx_bufs);
383 if (ret) {
384 LOG_ERR("Read 2 of SPI STATUS2 spi_transceive"
385 " failure: error %d",
386 ret);
387 return ret;
388 }
389
390 spi_status2 = safbuf2[0];
391 if (!(spi_status2 & SPI_STATUS2_QE)) {
392 LOG_ERR("Read back of SPI STATUS2 after setting "
393 "volatile QE bit shows QE not set: 0x%02X",
394 spi_status2);
395 return -1;
396 }
397 }
398
399 return 0;
400 }
401
espi_saf_init(void)402 int espi_saf_init(void)
403 {
404 int ret;
405
406 ret = espi_saf_config(espi_saf_dev, (struct espi_saf_cfg *)&saf_cfg1);
407 if (ret) {
408 LOG_ERR("Failed to configure eSPI SAF error %d", ret);
409 } else {
410 LOG_INF("eSPI SAF configured successfully!");
411 }
412
413 ret = espi_saf_set_protection_regions(espi_saf_dev, &saf_pr_w25q128);
414 if (ret) {
415 LOG_ERR("Failed to set SAF protection region(s) %d", ret);
416 } else {
417 LOG_INF("eSPI SAF protection regions(s) configured!");
418 }
419
420 return ret;
421 }
422
pr_check_range(struct mchp_espi_saf * regs,const struct espi_saf_pr * pr)423 static int pr_check_range(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr)
424 {
425 uint32_t limit;
426
427 limit = pr->start + pr->size - 1U;
428
429 /* registers b[19:0] = bits[31:12] (align on 4KB) */
430 if (regs->SAF_PROT_RG[pr->pr_num].START != (pr->start >> 12)) {
431 return -1;
432 }
433
434 if (regs->SAF_PROT_RG[pr->pr_num].LIMIT != (limit >> 12)) {
435 return -1;
436 }
437
438 return 0;
439 }
440
pr_check_enable(struct mchp_espi_saf * regs,const struct espi_saf_pr * pr)441 static int pr_check_enable(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr)
442 {
443 if (pr->flags & MCHP_SAF_PR_FLAG_ENABLE) {
444 if (regs->SAF_PROT_RG[pr->pr_num].LIMIT > regs->SAF_PROT_RG[pr->pr_num].START) {
445 return 0;
446 }
447 } else {
448 if (regs->SAF_PROT_RG[pr->pr_num].START > regs->SAF_PROT_RG[pr->pr_num].LIMIT) {
449 return 0;
450 }
451 }
452
453 return -2;
454 }
455
pr_check_lock(struct mchp_espi_saf * regs,const struct espi_saf_pr * pr)456 static int pr_check_lock(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr)
457 {
458 if (pr->flags & MCHP_SAF_PR_FLAG_LOCK) {
459 if (regs->SAF_PROT_LOCK & BIT(pr->pr_num)) {
460 return 0;
461 }
462 } else {
463 if (!(regs->SAF_PROT_LOCK & BIT(pr->pr_num))) {
464 return 0;
465 }
466 }
467
468 return -3;
469 }
470
471 /*
472 * NOTE: bit[0] of bit map registers is read-only = 1
473 */
pr_check_master_bm(struct mchp_espi_saf * regs,const struct espi_saf_pr * pr)474 static int pr_check_master_bm(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr)
475 {
476 if (regs->SAF_PROT_RG[pr->pr_num].WEBM != (pr->master_bm_we | BIT(0))) {
477 return -4;
478 }
479
480 if (regs->SAF_PROT_RG[pr->pr_num].RDBM != (pr->master_bm_rd | BIT(0))) {
481 return -4;
482 }
483
484 return 0;
485 }
486
espi_saf_test_pr1(const struct espi_saf_protection * spr)487 static int espi_saf_test_pr1(const struct espi_saf_protection *spr)
488 {
489 struct mchp_espi_saf *saf_regs;
490 const struct espi_saf_pr *pr;
491 int rc;
492
493 LOG_INF("espi_saf_test_pr1");
494
495 if (spr == NULL) {
496 return 0;
497 }
498
499 saf_regs = (struct mchp_espi_saf *)(SAF_BASE_ADDR);
500 pr = spr->pregions;
501
502 for (size_t n = 0U; n < spr->nregions; n++) {
503 rc = pr_check_range(saf_regs, pr);
504 if (rc) {
505 LOG_INF("SAF Protection region %u range fail", pr->pr_num);
506 return rc;
507 }
508
509 rc = pr_check_enable(saf_regs, pr);
510 if (rc) {
511 LOG_INF("SAF Protection region %u enable fail", pr->pr_num);
512 return rc;
513 }
514
515 rc = pr_check_lock(saf_regs, pr);
516 if (rc) {
517 LOG_INF("SAF Protection region %u lock check fail", pr->pr_num);
518 return rc;
519 }
520
521 rc = pr_check_master_bm(saf_regs, pr);
522 if (rc) {
523 LOG_INF("SAF Protection region %u Master select fail", pr->pr_num);
524 return rc;
525 }
526
527 pr++;
528 }
529
530 return 0;
531 }
532
533 /*
534 * SAF hardware limited to 1 to 64 byte read requests.
535 */
saf_read(uint32_t spi_addr,uint8_t * dest,int len)536 static int saf_read(uint32_t spi_addr, uint8_t *dest, int len)
537 {
538 int rc, chunk_len, n;
539 struct espi_saf_packet saf_pkt = {0};
540
541 if ((dest == NULL) || (len < 0)) {
542 return -EINVAL;
543 }
544
545 saf_pkt.flash_addr = spi_addr;
546 saf_pkt.buf = dest;
547
548 n = len;
549 while (n) {
550 chunk_len = 64;
551 if (n < 64) {
552 chunk_len = n;
553 }
554
555 saf_pkt.len = chunk_len;
556
557 rc = espi_saf_flash_read(espi_saf_dev, &saf_pkt);
558 if (rc != 0) {
559 LOG_INF("%s: error = %d: chunk_len = %d "
560 "spi_addr = %x",
561 __func__, rc, chunk_len, spi_addr);
562 return rc;
563 }
564
565 saf_pkt.flash_addr += chunk_len;
566 saf_pkt.buf += chunk_len;
567 n -= chunk_len;
568 }
569
570 return len;
571 }
572
573 /*
574 * SAF hardware limited to 4KB(mandatory), 32KB, and 64KB erase sizes.
575 * eSPI configuration has flags the Host can read specifying supported
576 * erase sizes.
577 */
saf_erase_block(uint32_t spi_addr,enum saf_erase_size ersz)578 static int saf_erase_block(uint32_t spi_addr, enum saf_erase_size ersz)
579 {
580 int rc;
581 struct espi_saf_packet saf_pkt = {0};
582
583 switch (ersz) {
584 case SAF_ERASE_4K:
585 saf_pkt.len = 4096U;
586 spi_addr &= ~(4096U - 1U);
587 break;
588 case SAF_ERASE_32K:
589 saf_pkt.len = (32U * 1024U);
590 spi_addr &= ~((32U * 1024U) - 1U);
591 break;
592 case SAF_ERASE_64K:
593 saf_pkt.len = (64U * 1024U);
594 spi_addr &= ~((64U * 1024U) - 1U);
595 break;
596 default:
597 return -EINVAL;
598 }
599
600 saf_pkt.flash_addr = spi_addr;
601
602 rc = espi_saf_flash_erase(espi_saf_dev, &saf_pkt);
603 if (rc != 0) {
604 LOG_INF("espi_saf_test1: erase fail = %d", rc);
605 return rc;
606 }
607
608 return 0;
609 }
610
611 /*
612 * SAF hardware limited to 1 to 64 byte programming within a 256 byte page.
613 */
saf_page_prog(uint32_t spi_addr,const uint8_t * src,int progsz)614 static int saf_page_prog(uint32_t spi_addr, const uint8_t *src, int progsz)
615 {
616 int rc, chunk_len, n;
617 struct espi_saf_packet saf_pkt = {0};
618
619 if ((src == NULL) || (progsz < 0) || (progsz > 256)) {
620 return -EINVAL;
621 }
622
623 if (progsz == 0) {
624 return 0;
625 }
626
627 saf_pkt.flash_addr = spi_addr;
628 saf_pkt.buf = (uint8_t *)src;
629
630 n = progsz;
631 while (n) {
632 chunk_len = 64;
633 if (n < 64) {
634 chunk_len = n;
635 }
636
637 saf_pkt.len = (uint32_t)chunk_len;
638
639 rc = espi_saf_flash_write(espi_saf_dev, &saf_pkt);
640 if (rc != 0) {
641 LOG_INF("%s: error = %d: erase fail spi_addr = 0x%X", __func__, rc,
642 spi_addr);
643 return rc;
644 }
645
646 saf_pkt.flash_addr += chunk_len;
647 saf_pkt.buf += chunk_len;
648 n -= chunk_len;
649 }
650
651 return progsz;
652 }
653
espi_saf_test1(uint32_t spi_addr)654 int espi_saf_test1(uint32_t spi_addr)
655 {
656 int rc, retries;
657 bool erased;
658 uint32_t n, saddr, progsz, chunksz;
659
660 rc = espi_saf_activate(espi_saf_dev);
661 LOG_INF("%s: activate = %d", __func__, rc);
662
663 if (spi_addr & 0xfffU) {
664 LOG_INF("%s: SPI address 0x%08x not 4KB aligned", __func__, spi_addr);
665 spi_addr &= ~(4096U - 1U);
666 LOG_INF("%s: Aligned SPI address to 0x%08x", __func__, spi_addr);
667 }
668
669 memset(safbuf, 0x55, sizeof(safbuf));
670 memset(safbuf2, 0, sizeof(safbuf2));
671
672 erased = false;
673 retries = 3;
674 while (!erased && (retries-- > 0)) {
675 /* read 4KB sector at 0 */
676 rc = saf_read(spi_addr, safbuf, 4096);
677 if (rc != 4096) {
678 LOG_INF("%s: error=%d Read 4K sector at 0x%X failed", __func__, rc,
679 spi_addr);
680 return rc;
681 }
682
683 rc = 0;
684 for (n = 0; n < 4096U; n++) {
685 if (safbuf[n] != 0xffUL) {
686 rc = -1;
687 break;
688 }
689 }
690
691 if (rc == 0) {
692 LOG_INF("4KB sector at 0x%x is in erased state. "
693 "Continue tests",
694 spi_addr);
695 erased = true;
696 } else {
697 LOG_INF("4KB sector at 0x%x not in erased state. "
698 "Send 4K erase.",
699 spi_addr);
700 rc = saf_erase_block(spi_addr, SAF_ERASE_4K);
701 if (rc != 0) {
702 LOG_INF("SAF erase block at 0x%x returned "
703 "error %d",
704 spi_addr, rc);
705 return rc;
706 }
707 }
708 }
709
710 if (!erased) {
711 LOG_INF("%s: Could not erase 4KB sector at 0x%08x", __func__, spi_addr);
712 return -1;
713 }
714
715 /*
716 * Page program test pattern every 256 bytes = 0,1,...,255
717 */
718 for (n = 0; n < 4096U; n++) {
719 safbuf[n] = n % 256U;
720 }
721
722 /* SPI flash sector erase size is 4KB, page program is 256 bytes */
723 progsz = 4096U;
724 chunksz = 256U;
725 saddr = spi_addr;
726 n = 0;
727 const uint8_t *src = (const uint8_t *)safbuf;
728
729 LOG_INF("%s: Program 4KB sector at 0x%X", __func__, saddr);
730
731 while (n < progsz) {
732 rc = saf_page_prog(saddr, (const uint8_t *)src, (int)chunksz);
733 if (rc != chunksz) {
734 LOG_INF("saf_page_prog error=%d at 0x%X", rc, saddr);
735 break;
736 }
737 saddr += chunksz;
738 n += chunksz;
739 src += chunksz;
740 }
741
742 /* read back and check */
743 LOG_INF("%s: Read back 4K sector at 0x%X", __func__, spi_addr);
744
745 rc = saf_read(spi_addr, safbuf2, progsz);
746 if (rc == progsz) {
747 rc = memcmp(safbuf, safbuf2, progsz);
748 if (rc == 0) {
749 LOG_INF("%s: Read back match: PASS", __func__);
750 } else {
751 LOG_INF("%s: Read back mismatch: FAIL", __func__);
752 }
753 } else {
754 LOG_INF("%s: Read back 4K error=%d", __func__, rc);
755 return rc;
756 }
757
758 return rc;
759 }
760 #endif /* CONFIG_ESPI_TAF */
761
host_warn_handler(uint32_t signal,uint32_t status)762 static void host_warn_handler(uint32_t signal, uint32_t status)
763 {
764 switch (signal) {
765 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
766 LOG_INF("Host reset warning %d", status);
767 if (!IS_ENABLED(CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE)) {
768 LOG_INF("HOST RST ACK %d", status);
769 espi_send_vwire(espi_dev, ESPI_VWIRE_SIGNAL_HOST_RST_ACK, status);
770 }
771 break;
772 case ESPI_VWIRE_SIGNAL_SUS_WARN:
773 LOG_INF("Host suspend warning %d", status);
774 if (!IS_ENABLED(CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE)) {
775 LOG_INF("SUS ACK %d", status);
776 espi_send_vwire(espi_dev, ESPI_VWIRE_SIGNAL_SUS_ACK, status);
777 }
778 break;
779 default:
780 break;
781 }
782 }
783
784 /* eSPI bus event handler */
espi_reset_handler(const struct device * dev,struct espi_callback * cb,struct espi_event event)785 static void espi_reset_handler(const struct device *dev, struct espi_callback *cb,
786 struct espi_event event)
787 {
788 if (event.evt_type == ESPI_BUS_RESET) {
789 espi_rst_sts = event.evt_data;
790 LOG_INF("eSPI BUS reset %d", event.evt_data);
791 }
792 }
793
794 /* eSPI logical channels enable/disable event handler */
espi_ch_handler(const struct device * dev,struct espi_callback * cb,struct espi_event event)795 static void espi_ch_handler(const struct device *dev, struct espi_callback *cb,
796 struct espi_event event)
797 {
798 if (event.evt_type == ESPI_BUS_EVENT_CHANNEL_READY) {
799 switch (event.evt_details) {
800 case ESPI_CHANNEL_VWIRE:
801 LOG_INF("VW channel event %x", event.evt_data);
802 break;
803 case ESPI_CHANNEL_FLASH:
804 LOG_INF("Flash channel event %d", event.evt_data);
805 break;
806 case ESPI_CHANNEL_OOB:
807 LOG_INF("OOB channel event %d", event.evt_data);
808 break;
809 default:
810 LOG_ERR("Unknown channel event");
811 }
812 }
813 }
814
815 /* eSPI vwire received event handler */
vwire_handler(const struct device * dev,struct espi_callback * cb,struct espi_event event)816 static void vwire_handler(const struct device *dev, struct espi_callback *cb,
817 struct espi_event event)
818 {
819 if (event.evt_type == ESPI_BUS_EVENT_VWIRE_RECEIVED) {
820 switch (event.evt_details) {
821 case ESPI_VWIRE_SIGNAL_PLTRST:
822 LOG_INF("PLT_RST changed %d", event.evt_data);
823 break;
824 case ESPI_VWIRE_SIGNAL_SLP_S3:
825 case ESPI_VWIRE_SIGNAL_SLP_S4:
826 case ESPI_VWIRE_SIGNAL_SLP_S5:
827 LOG_INF("SLP signal changed %d", event.evt_data);
828 break;
829 case ESPI_VWIRE_SIGNAL_SUS_WARN:
830 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
831 host_warn_handler(event.evt_details, event.evt_data);
832 break;
833 }
834 }
835 }
836
837 /* eSPI peripheral channel notifications handler */
periph_handler(const struct device * dev,struct espi_callback * cb,struct espi_event event)838 static void periph_handler(const struct device *dev, struct espi_callback *cb,
839 struct espi_event event)
840 {
841 uint8_t periph_type;
842 uint8_t periph_index;
843
844 periph_type = EVENT_TYPE(event.evt_details);
845 periph_index = EVENT_DETAILS(event.evt_details);
846
847 switch (periph_type) {
848 case ESPI_PERIPHERAL_DEBUG_PORT80:
849 LOG_INF("Postcode %x", event.evt_data);
850 break;
851 case ESPI_PERIPHERAL_HOST_IO:
852 LOG_INF("ACPI %x", event.evt_data);
853 espi_remove_callback(espi_dev, &p80_cb);
854 break;
855 default:
856 LOG_INF("%s periph 0x%x [%x]", __func__, periph_type, event.evt_data);
857 }
858 }
859
espi_init(void)860 int espi_init(void)
861 {
862 int ret;
863 /* Indicate to eSPI master simplest configuration: Single line,
864 * 20MHz frequency and only logical channel 0 and 1 are supported
865 */
866 struct espi_cfg cfg = {
867 .io_caps = ESPI_IO_MODE_SINGLE_LINE,
868 .channel_caps = ESPI_CHANNEL_VWIRE | ESPI_CHANNEL_PERIPHERAL,
869 .max_freq = ESPI_FREQ_20MHZ,
870 };
871
872 /* If eSPI driver supports additional capabilities use them */
873 #ifdef CONFIG_ESPI_OOB_CHANNEL
874 cfg.channel_caps |= ESPI_CHANNEL_OOB;
875 #endif
876 #ifdef CONFIG_ESPI_FLASH_CHANNEL
877 cfg.channel_caps |= ESPI_CHANNEL_FLASH;
878 cfg.io_caps |= ESPI_IO_MODE_QUAD_LINES;
879 cfg.max_freq = ESPI_FREQ_25MHZ;
880 #endif
881
882 ret = espi_config(espi_dev, &cfg);
883 if (ret) {
884 LOG_ERR("Failed to configure eSPI target channels:%x err: %d", cfg.channel_caps,
885 ret);
886 return ret;
887 } else {
888 LOG_INF("eSPI target configured successfully!");
889 }
890
891 LOG_INF("eSPI test - callbacks initialization... ");
892 espi_init_callback(&espi_bus_cb, espi_reset_handler, ESPI_BUS_RESET);
893 espi_init_callback(&vw_rdy_cb, espi_ch_handler, ESPI_BUS_EVENT_CHANNEL_READY);
894 espi_init_callback(&vw_cb, vwire_handler, ESPI_BUS_EVENT_VWIRE_RECEIVED);
895 espi_init_callback(&p80_cb, periph_handler, ESPI_BUS_PERIPHERAL_NOTIFICATION);
896 #ifdef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
897 espi_init_callback(&oob_cb, oob_rx_handler, ESPI_BUS_EVENT_OOB_RECEIVED);
898 #endif
899 LOG_INF("complete");
900
901 LOG_INF("eSPI test - callbacks registration... ");
902 espi_add_callback(espi_dev, &espi_bus_cb);
903 espi_add_callback(espi_dev, &vw_rdy_cb);
904 espi_add_callback(espi_dev, &vw_cb);
905 espi_add_callback(espi_dev, &p80_cb);
906 #ifdef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
907 espi_add_callback(espi_dev, &oob_cb);
908 #endif
909 LOG_INF("complete");
910
911 return ret;
912 }
913
914 #if DT_NODE_HAS_STATUS(BRD_PWR_NODE, okay)
wait_for_pin(const struct gpio_dt_spec * gpio,uint16_t timeout,int exp_level)915 static int wait_for_pin(const struct gpio_dt_spec *gpio, uint16_t timeout, int exp_level)
916 {
917 uint16_t loop_cnt = timeout;
918 int level;
919
920 do {
921 level = gpio_pin_get_dt(gpio);
922 if (level < 0) {
923 LOG_ERR("Failed to read %x %d", gpio->pin, level);
924 return -EIO;
925 }
926
927 if (exp_level == level) {
928 LOG_DBG("PIN %x = %x", gpio->pin, exp_level);
929 break;
930 }
931
932 k_usleep(K_WAIT_DELAY);
933 loop_cnt--;
934 } while (loop_cnt > 0);
935
936 if (loop_cnt == 0) {
937 LOG_ERR("Timeout for %x %x", gpio->pin, level);
938 return -ETIMEDOUT;
939 }
940
941 return 0;
942 }
943 #endif
944
wait_for_vwire(const struct device * espi_dev,enum espi_vwire_signal signal,uint16_t timeout,uint8_t exp_level)945 static int wait_for_vwire(const struct device *espi_dev, enum espi_vwire_signal signal,
946 uint16_t timeout, uint8_t exp_level)
947 {
948 int ret;
949 uint8_t level;
950 uint16_t loop_cnt = timeout;
951
952 do {
953 ret = espi_receive_vwire(espi_dev, signal, &level);
954 if (ret) {
955 LOG_ERR("Failed to read %x %d", signal, ret);
956 return -EIO;
957 }
958
959 if (exp_level == level) {
960 break;
961 }
962
963 k_usleep(K_WAIT_DELAY);
964 loop_cnt--;
965 } while (loop_cnt > 0);
966
967 if (loop_cnt == 0) {
968 LOG_ERR("VWIRE %d is %x", signal, level);
969 return -ETIMEDOUT;
970 }
971
972 return 0;
973 }
974
wait_for_espi_reset(uint8_t exp_sts)975 static int wait_for_espi_reset(uint8_t exp_sts)
976 {
977 uint16_t loop_cnt = CONFIG_ESPI_VIRTUAL_WIRE_TIMEOUT;
978
979 do {
980 if (exp_sts == espi_rst_sts) {
981 break;
982 }
983 k_usleep(K_WAIT_DELAY);
984 loop_cnt--;
985 } while (loop_cnt > 0);
986
987 if (loop_cnt == 0) {
988 return -ETIMEDOUT;
989 }
990
991 return 0;
992 }
993
espi_handshake(void)994 int espi_handshake(void)
995 {
996 int ret;
997
998 LOG_INF("eSPI test - Handshake with eSPI master...");
999 ret = wait_for_vwire(espi_dev, ESPI_VWIRE_SIGNAL_SUS_WARN, CONFIG_ESPI_VIRTUAL_WIRE_TIMEOUT,
1000 1);
1001 if (ret) {
1002 LOG_ERR("SUS_WARN Timeout");
1003 return ret;
1004 }
1005
1006 LOG_INF("1st phase completed");
1007 ret = wait_for_vwire(espi_dev, ESPI_VWIRE_SIGNAL_SLP_S5, CONFIG_ESPI_VIRTUAL_WIRE_TIMEOUT,
1008 1);
1009 if (ret) {
1010 LOG_ERR("SLP_S5 Timeout");
1011 return ret;
1012 }
1013
1014 ret = wait_for_vwire(espi_dev, ESPI_VWIRE_SIGNAL_SLP_S4, CONFIG_ESPI_VIRTUAL_WIRE_TIMEOUT,
1015 1);
1016 if (ret) {
1017 LOG_ERR("SLP_S4 Timeout");
1018 return ret;
1019 }
1020
1021 ret = wait_for_vwire(espi_dev, ESPI_VWIRE_SIGNAL_SLP_S3, CONFIG_ESPI_VIRTUAL_WIRE_TIMEOUT,
1022 1);
1023 if (ret) {
1024 LOG_ERR("SLP_S3 Timeout");
1025 return ret;
1026 }
1027
1028 LOG_INF("2nd phase completed");
1029
1030 ret = wait_for_vwire(espi_dev, ESPI_VWIRE_SIGNAL_PLTRST, CONFIG_ESPI_VIRTUAL_WIRE_TIMEOUT,
1031 1);
1032 if (ret) {
1033 LOG_ERR("PLT_RST Timeout");
1034 return ret;
1035 }
1036
1037 LOG_INF("3rd phase completed");
1038
1039 return 0;
1040 }
1041
1042 #ifdef CONFIG_ESPI_FLASH_CHANNEL
read_test_block(uint8_t * buf,uint32_t start_flash_adr,uint16_t block_len)1043 int read_test_block(uint8_t *buf, uint32_t start_flash_adr, uint16_t block_len)
1044 {
1045 uint8_t i = 0;
1046 uint32_t flash_addr = start_flash_adr;
1047 uint16_t transactions = block_len / MAX_FLASH_REQUEST;
1048 int ret = 0;
1049 struct espi_flash_packet pckt;
1050
1051 for (i = 0; i < transactions; i++) {
1052 pckt.buf = buf;
1053 pckt.flash_addr = flash_addr;
1054 pckt.len = MAX_FLASH_REQUEST;
1055
1056 ret = espi_read_flash(espi_dev, &pckt);
1057 if (ret) {
1058 LOG_ERR("espi_read_flash failed: %d", ret);
1059 return ret;
1060 }
1061
1062 buf += MAX_FLASH_REQUEST;
1063 flash_addr += MAX_FLASH_REQUEST;
1064 }
1065
1066 LOG_INF("%d read flash transactions completed", transactions);
1067 return 0;
1068 }
1069
write_test_block(uint8_t * buf,uint32_t start_flash_adr,uint16_t block_len)1070 int write_test_block(uint8_t *buf, uint32_t start_flash_adr, uint16_t block_len)
1071 {
1072 uint8_t i = 0;
1073 uint32_t flash_addr = start_flash_adr;
1074 uint16_t transactions = block_len / MAX_FLASH_REQUEST;
1075 int ret = 0;
1076 struct espi_flash_packet pckt;
1077
1078 /* Split operation in multiple MAX_FLASH_REQ transactions */
1079 for (i = 0; i < transactions; i++) {
1080 pckt.buf = buf;
1081 pckt.flash_addr = flash_addr;
1082 pckt.len = MAX_FLASH_REQUEST;
1083
1084 ret = espi_write_flash(espi_dev, &pckt);
1085 if (ret) {
1086 LOG_ERR("espi_write_flash failed: %d", ret);
1087 return ret;
1088 }
1089
1090 buf += MAX_FLASH_REQUEST;
1091 flash_addr += MAX_FLASH_REQUEST;
1092 }
1093
1094 LOG_INF("%d write flash transactions completed", transactions);
1095 return 0;
1096 }
1097
espi_flash_test(uint32_t start_flash_addr,uint8_t blocks)1098 static int espi_flash_test(uint32_t start_flash_addr, uint8_t blocks)
1099 {
1100 uint8_t i;
1101 uint8_t pattern;
1102 uint32_t flash_addr;
1103 int ret = 0;
1104
1105 LOG_INF("Test eSPI write flash");
1106 flash_addr = start_flash_addr;
1107 pattern = 0x99;
1108 for (i = 0; i <= blocks; i++) {
1109 memset(flash_write_buf, pattern++, sizeof(flash_write_buf));
1110 ret = write_test_block(flash_write_buf, flash_addr, sizeof(flash_write_buf));
1111 if (ret) {
1112 LOG_ERR("Failed to write to eSPI");
1113 return ret;
1114 }
1115
1116 flash_addr += sizeof(flash_write_buf);
1117 }
1118
1119 LOG_INF("Test eSPI read flash");
1120 flash_addr = start_flash_addr;
1121 pattern = 0x99;
1122 for (i = 0; i <= blocks; i++) {
1123 /* Set expected content */
1124 memset(flash_write_buf, pattern, sizeof(flash_write_buf));
1125 /* Clear last read content */
1126 memset(flash_read_buf, 0, sizeof(flash_read_buf));
1127 ret = read_test_block(flash_read_buf, flash_addr, sizeof(flash_read_buf));
1128 if (ret) {
1129 LOG_ERR("Failed to read from eSPI");
1130 return ret;
1131 }
1132
1133 /* Compare buffers */
1134 int cmp = memcmp(flash_write_buf, flash_read_buf, sizeof(flash_write_buf));
1135
1136 if (cmp != 0) {
1137 LOG_ERR("eSPI read mismmatch at %d expected %x", cmp, pattern);
1138 }
1139
1140 flash_addr += sizeof(flash_read_buf);
1141 pattern++;
1142 }
1143
1144 return 0;
1145 }
1146 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
1147
1148 #ifndef CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE
send_target_bootdone(void)1149 static void send_target_bootdone(void)
1150 {
1151 int ret;
1152 uint8_t boot_done;
1153
1154 ret = espi_receive_vwire(espi_dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, &boot_done);
1155 LOG_INF("%s boot_done: %d", __func__, boot_done);
1156 if (ret) {
1157 LOG_WRN("Fail to retrieve target boot done");
1158 } else if (!boot_done) {
1159 /* TARGET_BOOT_DONE & TARGET_LOAD_STS have to be sent together */
1160 espi_send_vwire(espi_dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS, 1);
1161 espi_send_vwire(espi_dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, 1);
1162 }
1163 }
1164 #endif
1165
espi_test(void)1166 int espi_test(void)
1167 {
1168 int ret;
1169
1170 /* Account for the time serial port is detected so log messages can
1171 * be seen
1172 */
1173 k_sleep(K_SECONDS(1));
1174
1175 #if DT_NODE_HAS_STATUS(BRD_PWR_NODE, okay)
1176 if (!gpio_is_ready_dt(&pwrgd_gpio)) {
1177 LOG_ERR("%s: device not ready.", pwrgd_gpio.port->name);
1178 return -ENODEV;
1179 }
1180 if (!gpio_is_ready_dt(&rsm_gpio)) {
1181 LOG_ERR("%s: device not ready.", rsm_gpio.port->name);
1182 return -ENODEV;
1183 }
1184 #endif
1185 if (!device_is_ready(espi_dev)) {
1186 LOG_ERR("%s: device not ready.", espi_dev->name);
1187 return -ENODEV;
1188 }
1189
1190 #ifdef CONFIG_ESPI_TAF
1191 if (!device_is_ready(qspi_dev)) {
1192 LOG_ERR("%s: device not ready.", qspi_dev->name);
1193 return -ENODEV;
1194 }
1195
1196 if (!device_is_ready(espi_saf_dev)) {
1197 LOG_ERR("%s: device not ready.", espi_saf_dev->name);
1198 return -ENODEV;
1199 }
1200 #endif
1201
1202 LOG_INF("Hello eSPI test %s", CONFIG_BOARD);
1203
1204 #if DT_NODE_HAS_STATUS(BRD_PWR_NODE, okay)
1205 ret = gpio_pin_configure_dt(&pwrgd_gpio, GPIO_INPUT);
1206 if (ret) {
1207 LOG_ERR("Unable to configure %d:%d", pwrgd_gpio.pin, ret);
1208 return ret;
1209 }
1210
1211 ret = gpio_pin_configure_dt(&rsm_gpio, GPIO_OUTPUT);
1212 if (ret) {
1213 LOG_ERR("Unable to config %d: %d", rsm_gpio.pin, ret);
1214 return ret;
1215 }
1216
1217 ret = gpio_pin_set_dt(&rsm_gpio, 0);
1218 if (ret) {
1219 LOG_ERR("Unable to initialize %d", rsm_gpio.pin);
1220 return -1;
1221 }
1222 #endif
1223
1224 espi_init();
1225
1226 #ifdef CONFIG_ESPI_TAF
1227 /*
1228 * eSPI SAF configuration must be after eSPI configuration.
1229 * eSPI SAF EC portal flash tests before EC releases RSMRST# and
1230 * Host de-asserts ESPI_RESET#.
1231 */
1232 ret = spi_saf_init();
1233 if (ret) {
1234 LOG_ERR("Unable to configure %d:%s", ret, qspi_dev->name);
1235 return ret;
1236 }
1237
1238 ret = espi_saf_init();
1239 if (ret) {
1240 LOG_ERR("Unable to configure %d:%s", ret, espi_saf_dev->name);
1241 return ret;
1242 }
1243
1244 ret = espi_saf_test_pr1(&saf_pr_w25q128);
1245 if (ret) {
1246 LOG_INF("eSPI SAF test pr1 returned error %d", ret);
1247 }
1248
1249 ret = espi_saf_test1(SAF_SPI_TEST_ADDRESS);
1250 if (ret) {
1251 LOG_INF("eSPI SAF test1 returned error %d", ret);
1252 }
1253 #endif
1254
1255 #if DT_NODE_HAS_STATUS(BRD_PWR_NODE, okay)
1256 ret = wait_for_pin(&pwrgd_gpio, PWR_SEQ_TIMEOUT, 1);
1257 if (ret) {
1258 LOG_ERR("RSMRST_PWRGD timeout");
1259 return ret;
1260 }
1261
1262 ret = gpio_pin_set_dt(&rsm_gpio, 1);
1263 if (ret) {
1264 LOG_ERR("Failed to set rsm err: %d", ret);
1265 return ret;
1266 }
1267 #endif
1268 ret = wait_for_espi_reset(1);
1269 if (ret) {
1270 LOG_INF("ESPI_RESET timeout");
1271 return ret;
1272 }
1273
1274 #ifndef CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE
1275 /* When automatic acknowledge is disabled to perform lengthy operations
1276 * in the eSPI target, need to explicitly send target boot virtual wires
1277 */
1278 bool vw_ch_sts;
1279
1280 /* Simulate lengthy operation during boot */
1281 k_sleep(K_SECONDS(2));
1282
1283 do {
1284 vw_ch_sts = espi_get_channel_status(espi_dev, ESPI_CHANNEL_VWIRE);
1285 k_busy_wait(100);
1286 } while (!vw_ch_sts);
1287
1288 send_target_bootdone();
1289 #endif
1290
1291 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1292 /* Flash operation need to be perform before VW handshake or
1293 * after eSPI host completes full initialization.
1294 * This sample code can't assume a full initialized eSPI host
1295 * so flash operations are perform here.
1296 */
1297 bool flash_sts;
1298
1299 do {
1300 flash_sts = espi_get_channel_status(espi_dev, ESPI_CHANNEL_FLASH);
1301 k_busy_wait(100);
1302 } while (!flash_sts);
1303
1304 /* eSPI flash test can fail and rest of operation can continue */
1305 ret = espi_flash_test(TARGET_FLASH_REGION, 1);
1306 if (ret) {
1307 LOG_INF("eSPI flash test failed %d", ret);
1308 }
1309 #endif
1310
1311 /* Showcase VW channel by exchanging virtual wires with eSPI host */
1312 ret = espi_handshake();
1313 if (ret) {
1314 LOG_ERR("eSPI VW handshake failed %d", ret);
1315 return ret;
1316 }
1317
1318 /* Attempt to use OOB channel to read temperature, regardless of
1319 * if is enabled or not.
1320 */
1321 #ifndef CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC
1322 /* System without host-initiated OOB Rx traffic */
1323 get_pch_temp_sync(espi_dev);
1324 #else
1325 /* System with host-initiated OOB Rx traffic */
1326 get_pch_temp_async(espi_dev);
1327 #endif
1328
1329 /* Cleanup */
1330 k_sleep(K_SECONDS(1));
1331 espi_remove_callback(espi_dev, &espi_bus_cb);
1332 espi_remove_callback(espi_dev, &vw_rdy_cb);
1333 espi_remove_callback(espi_dev, &vw_cb);
1334
1335 LOG_INF("eSPI sample completed err: %d", ret);
1336
1337 return ret;
1338 }
1339
main(void)1340 int main(void)
1341 {
1342 espi_test();
1343 return 0;
1344 }
1345
