1 /*
2 * Copyright (c) 2023 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_espi_taf
8
9 #include <soc.h>
10 #include <zephyr/drivers/espi.h>
11 #include <zephyr/drivers/espi_saf.h>
12 #include <zephyr/drivers/flash.h>
13 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
14 #include <zephyr/drivers/flash/npcx_flash_api_ex.h>
15 #endif
16 #include <zephyr/kernel.h>
17 #include <zephyr/logging/log.h>
18
19 LOG_MODULE_REGISTER(espi_taf, CONFIG_ESPI_LOG_LEVEL);
20
21 static const struct device *const spi_dev = DEVICE_DT_GET(DT_ALIAS(taf_flash));
22
23 enum ESPI_TAF_ERASE_LEN {
24 NPCX_ESPI_TAF_ERASE_LEN_4KB,
25 NPCX_ESPI_TAF_ERASE_LEN_32KB,
26 NPCX_ESPI_TAF_ERASE_LEN_64KB,
27 NPCX_ESPI_TAF_ERASE_LEN_128KB,
28 NPCX_ESPI_TAF_ERASE_LEN_MAX,
29 };
30
31 struct espi_taf_npcx_config {
32 uintptr_t base;
33 uintptr_t mapped_addr;
34 uintptr_t rx_plsz;
35 enum NPCX_ESPI_TAF_ERASE_BLOCK_SIZE erase_sz;
36 enum NPCX_ESPI_TAF_MAX_READ_REQ max_rd_sz;
37 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
38 uint8_t rpmc_cnt_num;
39 uint8_t rpmc_op1_code;
40 #endif
41 };
42
43 #define MAX_TX_PAYLOAD_SIZE DT_PROP(DT_INST_PARENT(0), tx_plsize)
44
45 struct espi_taf_npcx_data {
46 sys_slist_t *callbacks;
47 const struct device *host_dev;
48 uint8_t taf_type;
49 uint8_t taf_tag;
50 uint32_t address;
51 uint16_t length;
52 uint32_t src[16];
53 uint8_t read_buf[MAX_TX_PAYLOAD_SIZE];
54 struct k_work work;
55 };
56
57 static struct espi_taf_npcx_data npcx_espi_taf_data;
58 static struct espi_callback espi_taf_cb;
59
60 #define HAL_INSTANCE(dev) \
61 ((struct espi_reg *)((const struct espi_taf_npcx_config *) \
62 (dev)->config)->base)
63
64 #define FLBASE_ADDR ( \
65 GET_FIELD(inst->FLASHBASE, NPCX_FLASHBASE_FLBASE_ADDR) \
66 << GET_FIELD_POS(NPCX_FLASHBASE_FLBASE_ADDR))
67
68 #define PRTR_BADDR(i) ( \
69 GET_FIELD(inst->FLASH_PRTR_BADDR[i], NPCX_FLASH_PRTR_BADDR) \
70 << GET_FIELD_POS(NPCX_FLASH_PRTR_BADDR))
71
72 #define PRTR_HADDR(i) ( \
73 GET_FIELD(inst->FLASH_PRTR_HADDR[i], NPCX_FLASH_PRTR_HADDR) \
74 << GET_FIELD_POS(NPCX_FLASH_PRTR_HADDR)) | 0xFFF;
75
espi_taf_get_pckt(const struct device * dev,struct espi_taf_npcx_data * pckt,struct espi_event event)76 static void espi_taf_get_pckt(const struct device *dev, struct espi_taf_npcx_data *pckt,
77 struct espi_event event)
78 {
79 struct espi_taf_pckt *data_ptr;
80
81 data_ptr = (struct espi_taf_pckt *)event.evt_data;
82
83 pckt->taf_type = data_ptr->type;
84 pckt->length = data_ptr->len;
85 pckt->taf_tag = data_ptr->tag;
86 pckt->address = data_ptr->addr;
87 if ((data_ptr->type == NPCX_ESPI_TAF_REQ_WRITE) ||
88 (IS_ENABLED(CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT) &&
89 (data_ptr->type == NPCX_ESPI_TAF_REQ_RPMC_OP1))) {
90 memcpy(pckt->src, data_ptr->src, sizeof(pckt->src));
91 }
92 }
93
94 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
95 /* Check access region of read request is protected or not */
espi_taf_check_read_protect(const struct device * dev,uint32_t addr,uint32_t len,uint8_t tag)96 static bool espi_taf_check_read_protect(const struct device *dev, uint32_t addr, uint32_t len,
97 uint8_t tag)
98 {
99 struct espi_reg *const inst = HAL_INSTANCE(dev);
100 uint32_t flash_addr = addr;
101 uint8_t i;
102 uint16_t override_rd;
103 uint32_t base, high;
104 bool rdpr;
105
106 flash_addr += FLBASE_ADDR;
107
108 for (i = 0; i < CONFIG_ESPI_TAF_PR_NUM; i++) {
109 base = PRTR_BADDR(i);
110 high = PRTR_HADDR(i);
111
112 rdpr = IS_BIT_SET(inst->FLASH_PRTR_BADDR[i], NPCX_FRGN_RPR);
113 override_rd = GET_FIELD(inst->FLASH_RGN_TAG_OVR[i], NPCX_FLASH_TAG_OVR_RPR);
114
115 if (rdpr && !IS_BIT_SET(override_rd, tag) &&
116 (base <= flash_addr + len - 1 && flash_addr <= high)) {
117 return true;
118 }
119 }
120
121 return false;
122 }
123 #endif
124
125 /* Check access region of write request is protected or not */
espi_taf_check_write_protect(const struct device * dev,uint32_t addr,uint32_t len,uint8_t tag)126 static bool espi_taf_check_write_protect(const struct device *dev, uint32_t addr,
127 uint32_t len, uint8_t tag)
128 {
129 struct espi_reg *const inst = HAL_INSTANCE(dev);
130 uint32_t flash_addr = addr;
131 uint8_t i;
132 uint16_t override_wr;
133 uint32_t base, high;
134 bool wrpr;
135
136 flash_addr += FLBASE_ADDR;
137
138 for (i = 0; i < CONFIG_ESPI_TAF_PR_NUM; i++) {
139 base = PRTR_BADDR(i);
140 high = PRTR_HADDR(i);
141
142 wrpr = IS_BIT_SET(inst->FLASH_PRTR_BADDR[i], NPCX_FRGN_WPR);
143 override_wr = GET_FIELD(inst->FLASH_RGN_TAG_OVR[i], NPCX_FLASH_TAG_OVR_WPR);
144
145 if (wrpr && !IS_BIT_SET(override_wr, tag) &&
146 (base <= flash_addr + len - 1 && flash_addr <= high)) {
147 return true;
148 }
149 }
150
151 return false;
152 }
153
espi_taf_npcx_configure(const struct device * dev,const struct espi_saf_cfg * cfg)154 static int espi_taf_npcx_configure(const struct device *dev, const struct espi_saf_cfg *cfg)
155 {
156 struct espi_reg *const inst = HAL_INSTANCE(dev);
157
158 if (cfg->nflash_devices == 0U) {
159 return -EINVAL;
160 }
161
162 #if defined(CONFIG_ESPI_TAF_AUTO_MODE)
163 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
164 #else
165 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
166 #endif
167
168 return 0;
169 }
170
espi_taf_npcx_set_pr(const struct device * dev,const struct espi_saf_protection * pr)171 static int espi_taf_npcx_set_pr(const struct device *dev, const struct espi_saf_protection *pr)
172 {
173 struct espi_reg *const inst = HAL_INSTANCE(dev);
174 const struct espi_saf_pr *preg = pr->pregions;
175 size_t n = pr->nregions;
176 uint8_t regnum;
177 uint16_t bitmask, offset;
178 uint32_t rw_pr, override_rw;
179
180 if ((dev == NULL) || (pr == NULL)) {
181 return -EINVAL;
182 }
183
184 if (pr->nregions >= CONFIG_ESPI_TAF_PR_NUM) {
185 return -EINVAL;
186 }
187
188 while (n--) {
189 regnum = preg->pr_num;
190
191 if (regnum >= CONFIG_ESPI_TAF_PR_NUM) {
192 return -EINVAL;
193 }
194
195 rw_pr = preg->master_bm_we << NPCX_FRGN_WPR;
196 rw_pr = rw_pr | (preg->master_bm_rd << NPCX_FRGN_RPR);
197
198 if (preg->flags) {
199 bitmask = BIT_MASK(GET_FIELD_SZ(NPCX_FLASH_PRTR_BADDR));
200 offset = GET_FIELD_POS(NPCX_FLASH_PRTR_BADDR);
201 inst->FLASH_PRTR_BADDR[regnum] = ((preg->start & bitmask) << offset)
202 | rw_pr;
203 bitmask = BIT_MASK(GET_FIELD_SZ(NPCX_FLASH_PRTR_HADDR));
204 offset = GET_FIELD_POS(NPCX_FLASH_PRTR_HADDR);
205 inst->FLASH_PRTR_HADDR[regnum] = (preg->end & bitmask) << offset;
206 }
207
208 override_rw = (preg->override_r << 16) | preg->override_w;
209 inst->FLASH_RGN_TAG_OVR[regnum] = override_rw;
210 preg++;
211 }
212
213 return 0;
214 }
215
espi_taf_npcx_activate(const struct device * dev)216 static int espi_taf_npcx_activate(const struct device *dev)
217 {
218 struct espi_reg *const inst = HAL_INSTANCE(dev);
219
220 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
221 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_BLK_FLASH_NP_FREE);
222
223 return 0;
224 }
225
espi_taf_npcx_channel_ready(const struct device * dev)226 static bool espi_taf_npcx_channel_ready(const struct device *dev)
227 {
228 struct espi_reg *const inst = HAL_INSTANCE(dev);
229 uint8_t ret =
230 GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLCAPA) & NPCX_FLASH_SHARING_CAP_SUPP_TAF;
231
232 if (ret != NPCX_FLASH_SHARING_CAP_SUPP_TAF) {
233 return false;
234 }
235
236 if (!device_is_ready(spi_dev)) {
237 return false;
238 }
239
240 return true;
241 }
242
243 /* This routine set FLASH_C_AVAIL for standard request */
taf_set_flash_c_avail(const struct device * dev)244 static void taf_set_flash_c_avail(const struct device *dev)
245 {
246 struct espi_reg *const inst = HAL_INSTANCE(dev);
247 uint32_t tmp = inst->FLASHCTL;
248
249 /*
250 * Clear FLASHCTL_FLASH_NP_FREE to avoid host puts a flash
251 * standard request command at here.
252 */
253 tmp &= NPCX_FLASHCTL_ACCESS_MASK;
254
255 /* Set FLASHCTL_FLASH_TX_AVAIL */
256 tmp |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
257 inst->FLASHCTL = tmp;
258 }
259
260 /* This routine release FLASH_NP_FREE for standard request */
taf_release_flash_np_free(const struct device * dev)261 static void taf_release_flash_np_free(const struct device *dev)
262 {
263 struct espi_reg *const inst = HAL_INSTANCE(dev);
264 uint32_t tmp = inst->FLASHCTL;
265
266 /*
267 * Clear FLASHCTL_FLASH_TX_AVAIL to avoid host puts a
268 * GET_FLASH_C command at here.
269 */
270 tmp &= NPCX_FLASHCTL_ACCESS_MASK;
271
272 /* Release FLASH_NP_FREE */
273 tmp |= BIT(NPCX_FLASHCTL_FLASH_NP_FREE);
274 inst->FLASHCTL = tmp;
275 }
276
taf_npcx_completion_handler(const struct device * dev,uint8_t type,uint8_t tag,uint16_t len,uint32_t * buffer)277 static int taf_npcx_completion_handler(const struct device *dev, uint8_t type, uint8_t tag,
278 uint16_t len, uint32_t *buffer)
279 {
280 struct espi_reg *const inst = HAL_INSTANCE(dev);
281 struct npcx_taf_head taf_head;
282 uint16_t i, size;
283 uint32_t tx_buf[16];
284
285 taf_head.pkt_len = NPCX_TAF_CMP_HEADER_LEN + len;
286 taf_head.type = type;
287 taf_head.tag_hlen = (tag << 4) | ((len & 0xF00) >> 8);
288 taf_head.llen = len & 0xFF;
289
290 memcpy(&tx_buf[0], &taf_head, sizeof(struct npcx_taf_head));
291
292 if (type == CYC_SCS_CMP_WITH_DATA_ONLY || type == CYC_SCS_CMP_WITH_DATA_FIRST ||
293 type == CYC_SCS_CMP_WITH_DATA_MIDDLE || type == CYC_SCS_CMP_WITH_DATA_LAST) {
294 memcpy(&tx_buf[1], buffer, (uint8_t)(len));
295 }
296
297 /* Check the Flash Access TX Queue is empty by polling
298 * FLASH_TX_AVAIL.
299 */
300 if (WAIT_FOR(!IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL),
301 NPCX_FLASH_CHK_TIMEOUT, NULL) == false) {
302 LOG_ERR("Check TX Queue Is Empty Timeout");
303 return -EBUSY;
304 }
305
306 /* Write packet to FLASHTXBUF */
307 size = DIV_ROUND_UP((uint8_t)(tx_buf[0]) + 1, sizeof(uint32_t));
308 for (i = 0; i < size; i++) {
309 inst->FLASHTXBUF[i] = tx_buf[i];
310 }
311
312 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
313 taf_set_flash_c_avail(dev);
314
315 /* Release FLASH_NP_FREE here to ready get next TAF request */
316 if ((type != CYC_SCS_CMP_WITH_DATA_FIRST) && (type != CYC_SCS_CMP_WITH_DATA_MIDDLE)) {
317 taf_release_flash_np_free(dev);
318 }
319
320 return 0;
321 }
322
323 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
espi_taf_npcx_flash_read(const struct device * dev,struct espi_saf_packet * pckt)324 static int espi_taf_npcx_flash_read(const struct device *dev, struct espi_saf_packet *pckt)
325 {
326 struct espi_reg *const inst = HAL_INSTANCE(dev);
327 struct espi_taf_npcx_config *config = ((struct espi_taf_npcx_config *)(dev)->config);
328 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
329 uint8_t cycle_type = CYC_SCS_CMP_WITH_DATA_ONLY;
330 uint32_t total_len = pckt->len;
331 uint32_t len = total_len;
332 uint32_t addr = pckt->flash_addr;
333 uint8_t flash_req_size = GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLASHREQSIZE);
334 uint8_t target_max_size = GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLREQSUP);
335 uint16_t max_read_req = 32 << flash_req_size;
336 int rc;
337
338 if (flash_req_size > target_max_size) {
339 LOG_DBG("Exceeded the maximum supported length");
340 if (target_max_size == 0) {
341 target_max_size = 1;
342 }
343 max_read_req = 32 << target_max_size;
344 }
345
346 if (total_len > max_read_req) {
347 LOG_ERR("Exceeded the limitation of read length");
348 return -EINVAL;
349 }
350
351 if (espi_taf_check_read_protect(dev, addr, len, taf_data_ptr->tag)) {
352 LOG_ERR("Access protect region");
353 return -EINVAL;
354 }
355
356 if (total_len <= config->rx_plsz) {
357 cycle_type = CYC_SCS_CMP_WITH_DATA_ONLY;
358 len = total_len;
359 } else {
360 cycle_type = CYC_SCS_CMP_WITH_DATA_FIRST;
361 len = config->rx_plsz;
362 }
363
364 do {
365 rc = flash_read(spi_dev, addr, npcx_espi_taf_data.read_buf, len);
366 if (rc) {
367 LOG_ERR("flash read fail 0x%x", rc);
368 return -EIO;
369 }
370
371 rc = taf_npcx_completion_handler(dev, cycle_type, taf_data_ptr->tag, len,
372 (uint32_t *)npcx_espi_taf_data.read_buf);
373 if (rc) {
374 LOG_ERR("espi taf completion handler fail");
375 return rc;
376 }
377
378 total_len -= len;
379 addr += len;
380
381 if (total_len <= config->rx_plsz) {
382 cycle_type = CYC_SCS_CMP_WITH_DATA_LAST;
383 len = total_len;
384 } else {
385 cycle_type = CYC_SCS_CMP_WITH_DATA_MIDDLE;
386 }
387 } while (total_len);
388
389 return 0;
390 }
391 #endif
392
espi_taf_npcx_flash_write(const struct device * dev,struct espi_saf_packet * pckt)393 static int espi_taf_npcx_flash_write(const struct device *dev, struct espi_saf_packet *pckt)
394 {
395 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
396 uint8_t *data_ptr = (uint8_t *)(taf_data_ptr->data);
397 int rc;
398
399 if (espi_taf_check_write_protect(dev, pckt->flash_addr,
400 pckt->len, taf_data_ptr->tag)) {
401 LOG_ERR("Access protection region");
402 return -EINVAL;
403 }
404
405 rc = flash_write(spi_dev, pckt->flash_addr, data_ptr, pckt->len);
406 if (rc) {
407 LOG_ERR("flash write fail 0x%x", rc);
408 return -EIO;
409 }
410
411 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
412 NULL);
413 if (rc) {
414 LOG_ERR("espi taf completion handler fail");
415 return rc;
416 }
417
418 return 0;
419 }
420
espi_taf_npcx_flash_erase(const struct device * dev,struct espi_saf_packet * pckt)421 static int espi_taf_npcx_flash_erase(const struct device *dev, struct espi_saf_packet *pckt)
422 {
423 int erase_blk[] = {KB(4), KB(32), KB(64), KB(128)};
424 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
425 uint32_t addr = pckt->flash_addr;
426 uint32_t len;
427 int rc;
428
429 if ((pckt->len < 0) || (pckt->len >= NPCX_ESPI_TAF_ERASE_LEN_MAX)) {
430 LOG_ERR("Invalid erase block size");
431 return -EINVAL;
432 }
433
434 len = erase_blk[pckt->len];
435
436 if (espi_taf_check_write_protect(dev, addr, len, taf_data_ptr->tag)) {
437 LOG_ERR("Access protection region");
438 return -EINVAL;
439 }
440
441 rc = flash_erase(spi_dev, addr, len);
442 if (rc) {
443 LOG_ERR("flash erase fail");
444 return -EIO;
445 }
446
447 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
448 NULL);
449 if (rc) {
450 LOG_ERR("espi taf completion handler fail");
451 return rc;
452 }
453
454 return 0;
455 }
456
457 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
espi_taf_npcx_rpmc_op1(const struct device * dev,struct espi_saf_packet * pckt)458 static int espi_taf_npcx_rpmc_op1(const struct device *dev, struct espi_saf_packet *pckt)
459 {
460 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
461 uint8_t *data_ptr = taf_data_ptr->data;
462 struct npcx_ex_ops_uma_in op_in = {
463 .opcode = ESPI_TAF_RPMC_OP1_CMD,
464 .tx_buf = data_ptr + 1,
465 .tx_count = (pckt->len) - 1,
466 .rx_count = 0,
467 };
468 int rc;
469
470 rc = flash_ex_op(spi_dev, FLASH_NPCX_EX_OP_EXEC_UMA, (uintptr_t)&op_in, NULL);
471 if (rc) {
472 LOG_ERR("flash RPMC OP1 fail");
473 return -EIO;
474 }
475
476 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
477 NULL);
478 if (rc) {
479 LOG_ERR("espi taf completion handler fail");
480 return rc;
481 }
482
483 return 0;
484 }
485
espi_taf_npcx_rpmc_op2(const struct device * dev,struct espi_saf_packet * pckt)486 static int espi_taf_npcx_rpmc_op2(const struct device *dev, struct espi_saf_packet *pckt)
487 {
488 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
489 uint8_t dummy_byte = 0;
490 struct npcx_ex_ops_uma_in op_in = {
491 .opcode = ESPI_TAF_RPMC_OP2_CMD,
492 .tx_buf = &dummy_byte,
493 .tx_count = 1,
494 .rx_count = pckt->len,
495 };
496 struct npcx_ex_ops_uma_out op_out = {
497 .rx_buf = npcx_espi_taf_data.read_buf,
498 };
499
500 int rc;
501
502 if (pckt->len > MAX_TX_PAYLOAD_SIZE) {
503 LOG_ERR("Invalid size");
504 return -EINVAL;
505 }
506
507 rc = flash_ex_op(spi_dev, FLASH_NPCX_EX_OP_EXEC_UMA, (uintptr_t)&op_in, &op_out);
508 if (rc) {
509 LOG_ERR("flash RPMC OP2 fail");
510 return -EIO;
511 }
512
513 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITH_DATA_ONLY, taf_data_ptr->tag,
514 pckt->len, (uint32_t *)npcx_espi_taf_data.read_buf);
515 if (rc) {
516 LOG_ERR("espi taf completion handler fail");
517 return rc;
518 }
519
520 return 0;
521 }
522 #endif
523
espi_taf_npcx_flash_unsuccess(const struct device * dev,struct espi_saf_packet * pckt)524 static int espi_taf_npcx_flash_unsuccess(const struct device *dev, struct espi_saf_packet *pckt)
525 {
526 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
527 int rc;
528
529 rc = taf_npcx_completion_handler(dev, CYC_UNSCS_CMP_WITHOUT_DATA_ONLY, taf_data_ptr->tag,
530 0x0, NULL);
531 if (rc) {
532 LOG_ERR("espi taf completion handler fail");
533 return rc;
534 }
535
536 return 0;
537 }
538
espi_taf_work(struct k_work * item)539 static void espi_taf_work(struct k_work *item)
540 {
541 struct espi_taf_npcx_data *info = CONTAINER_OF(item, struct espi_taf_npcx_data, work);
542 int ret = 0;
543
544 struct espi_taf_npcx_pckt taf_data;
545 struct espi_saf_packet pckt_taf;
546
547 pckt_taf.flash_addr = info->address;
548 pckt_taf.len = info->length;
549 taf_data.tag = info->taf_tag;
550 if ((info->taf_type == NPCX_ESPI_TAF_REQ_WRITE) ||
551 (IS_ENABLED(CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT) &&
552 (info->taf_type == NPCX_ESPI_TAF_REQ_RPMC_OP1))) {
553 taf_data.data = (uint8_t *)info->src;
554 } else {
555 taf_data.data = NULL;
556 }
557 pckt_taf.buf = (uint8_t *)&taf_data;
558
559 switch (info->taf_type) {
560 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
561 case NPCX_ESPI_TAF_REQ_READ:
562 ret = espi_taf_npcx_flash_read(info->host_dev, &pckt_taf);
563 break;
564 #endif
565 case NPCX_ESPI_TAF_REQ_ERASE:
566 ret = espi_taf_npcx_flash_erase(info->host_dev, &pckt_taf);
567 break;
568 case NPCX_ESPI_TAF_REQ_WRITE:
569 ret = espi_taf_npcx_flash_write(info->host_dev, &pckt_taf);
570 break;
571 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
572 case NPCX_ESPI_TAF_REQ_RPMC_OP1:
573 ret = espi_taf_npcx_rpmc_op1(info->host_dev, &pckt_taf);
574 break;
575 case NPCX_ESPI_TAF_REQ_RPMC_OP2:
576 ret = espi_taf_npcx_rpmc_op2(info->host_dev, &pckt_taf);
577 break;
578 #endif
579 }
580
581 if (ret != 0) {
582 ret = espi_taf_npcx_flash_unsuccess(info->host_dev, &pckt_taf);
583 }
584 }
585
espi_taf_event_handler(const struct device * dev,struct espi_callback * cb,struct espi_event event)586 static void espi_taf_event_handler(const struct device *dev, struct espi_callback *cb,
587 struct espi_event event)
588 {
589 if ((event.evt_type != ESPI_BUS_TAF_NOTIFICATION) ||
590 (event.evt_details != ESPI_CHANNEL_FLASH)) {
591 return;
592 }
593
594 espi_taf_get_pckt(dev, &npcx_espi_taf_data, event);
595 k_work_submit(&npcx_espi_taf_data.work);
596 }
597
npcx_init_taf(const struct device * dev,sys_slist_t * callbacks)598 int npcx_init_taf(const struct device *dev, sys_slist_t *callbacks)
599 {
600 espi_init_callback(&espi_taf_cb, espi_taf_event_handler, ESPI_BUS_TAF_NOTIFICATION);
601 espi_add_callback(dev, &espi_taf_cb);
602
603 npcx_espi_taf_data.host_dev = dev;
604 npcx_espi_taf_data.callbacks = callbacks;
605 k_work_init(&npcx_espi_taf_data.work, espi_taf_work);
606
607 return 0;
608 }
609
espi_taf_npcx_init(const struct device * dev)610 static int espi_taf_npcx_init(const struct device *dev)
611 {
612 struct espi_reg *const inst = HAL_INSTANCE(dev);
613 struct espi_taf_npcx_config *config = ((struct espi_taf_npcx_config *)(dev)->config);
614
615 SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLCAPA,
616 NPCX_FLASH_SHARING_CAP_SUPP_TAF_AND_CAF);
617 SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_TRGFLEBLKSIZE,
618 BIT(config->erase_sz));
619 SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLREQSUP,
620 config->max_rd_sz);
621 inst->FLASHBASE = config->mapped_addr;
622
623 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
624 uint8_t count_num = 0;
625
626 /* RPMC_CFG1_CNTR is 0-based number, e.g. 0 indicates that 1 counter is supported, 1
627 * indicates 2 counters, etc.
628 */
629 if (config->rpmc_cnt_num > 0) {
630 count_num = config->rpmc_cnt_num - 1;
631 }
632
633 SET_FIELD(inst->FLASH_RPMC_CFG_1, NPCX_FLASH_RPMC_CFG1_CNTR, count_num);
634 SET_FIELD(inst->FLASH_RPMC_CFG_1, NPCX_FLASH_RPMC_CFG1_OP1, config->rpmc_op1_code);
635 SET_FIELD(inst->FLASH_RPMC_CFG_1, NPCX_FLASH_RPMC_CFG1_TRGRPMCSUP, config->rpmc_cnt_num);
636 #endif
637
638 return 0;
639 }
640
641 static DEVICE_API(espi_saf, espi_taf_npcx_driver_api) = {
642 .config = espi_taf_npcx_configure,
643 .set_protection_regions = espi_taf_npcx_set_pr,
644 .activate = espi_taf_npcx_activate,
645 .get_channel_status = espi_taf_npcx_channel_ready,
646 };
647
648 static const struct espi_taf_npcx_config espi_taf_npcx_config = {
649 .base = DT_INST_REG_ADDR(0),
650 .mapped_addr = DT_INST_PROP(0, mapped_addr),
651 .rx_plsz = DT_PROP(DT_INST_PARENT(0), rx_plsize),
652 .erase_sz = DT_INST_STRING_TOKEN(0, erase_sz),
653 .max_rd_sz = DT_INST_STRING_TOKEN(0, max_read_sz),
654 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
655 .rpmc_cnt_num = DT_INST_PROP(0, rpmc_cntr),
656 .rpmc_op1_code = DT_INST_PROP(0, rpmc_op1_code),
657 #endif
658 };
659
660 DEVICE_DT_INST_DEFINE(0, &espi_taf_npcx_init, NULL,
661 &npcx_espi_taf_data, &espi_taf_npcx_config,
662 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
663 &espi_taf_npcx_driver_api);
664