1 /* 2 * Copyright (c) 2017 comsuisse AG 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** @file 8 * @brief Atmel SAM MCU family Direct Memory Access (XDMAC) driver. 9 */ 10 11 #ifndef ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_ 12 #define ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_ 13 14 #include <stdint.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* XDMA_MBR_UBC */ 21 #define XDMA_UBC_NDE (0x1u << 24) 22 #define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24) 23 #define XDMA_UBC_NDE_FETCH_EN (0x1u << 24) 24 #define XDMA_UBC_NSEN (0x1u << 25) 25 #define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25) 26 #define XDMA_UBC_NSEN_UPDATED (0x1u << 25) 27 #define XDMA_UBC_NDEN (0x1u << 26) 28 #define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26) 29 #define XDMA_UBC_NDEN_UPDATED (0x1u << 26) 30 #define XDMA_UBC_NVIEW_SHIFT 27 31 #define XDMA_UBC_NVIEW_MASK (0x3u << XDMA_UBC_NVIEW_SHIFT) 32 #define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_SHIFT) 33 #define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_SHIFT) 34 #define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_SHIFT) 35 #define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_SHIFT) 36 37 /** DMA channel configuration parameters */ 38 struct sam_xdmac_channel_config { 39 /** Configuration Register */ 40 uint32_t cfg; 41 /** Data Stride / Memory Set Pattern Register */ 42 uint32_t ds_msp; 43 /** Source Microblock Stride */ 44 uint32_t sus; 45 /** Destination Microblock Stride */ 46 uint32_t dus; 47 /** Channel Interrupt Enable */ 48 uint32_t cie; 49 }; 50 51 /** DMA transfer configuration parameters */ 52 struct sam_xdmac_transfer_config { 53 /** Microblock length */ 54 uint32_t ublen; 55 /** Source Address */ 56 uint32_t sa; 57 /** Destination Address */ 58 uint32_t da; 59 /** Block length (The length of the block is (blen+1) microblocks) */ 60 uint32_t blen; 61 /** Next descriptor address */ 62 uint32_t nda; 63 /** Next descriptor configuration */ 64 uint32_t ndc; 65 }; 66 67 /** DMA Master transfer linked list view 0 structure */ 68 struct sam_xdmac_linked_list_desc_view0 { 69 /** Next Descriptor Address */ 70 uint32_t mbr_nda; 71 /** Microblock Control */ 72 uint32_t mbr_ubc; 73 /** Transfer Address */ 74 uint32_t mbr_ta; 75 }; 76 77 /** DMA Master transfer linked list view 1 structure */ 78 struct sam_xdmac_linked_list_desc_view1 { 79 /** Next Descriptor Address */ 80 uint32_t mbr_nda; 81 /** Microblock Control */ 82 uint32_t mbr_ubc; 83 /** Source Address */ 84 uint32_t mbr_sa; 85 /** Destination Address */ 86 uint32_t mbr_da; 87 }; 88 89 /** DMA Master transfer linked list view 2 structure */ 90 struct sam_xdmac_linked_list_desc_view2 { 91 /** Next Descriptor Address */ 92 uint32_t mbr_nda; 93 /** Microblock Control */ 94 uint32_t mbr_ubc; 95 /** Source Address */ 96 uint32_t mbr_sa; 97 /** Destination Address */ 98 uint32_t mbr_da; 99 /** Configuration Register */ 100 uint32_t mbr_cfg; 101 }; 102 103 /** DMA Master transfer linked list view 3 structure */ 104 struct sam_xdmac_linked_list_desc_view3 { 105 /** Next Descriptor Address */ 106 uint32_t mbr_nda; 107 /** Microblock Control */ 108 uint32_t mbr_ubc; 109 /** Source Address */ 110 uint32_t mbr_sa; 111 /** Destination Address */ 112 uint32_t mbr_da; 113 /** Configuration Register */ 114 uint32_t mbr_cfg; 115 /** Block Control */ 116 uint32_t mbr_bc; 117 /** Data Stride */ 118 uint32_t mbr_ds; 119 /** Source Microblock Stride */ 120 uint32_t mbr_sus; 121 /** Destination Microblock Stride */ 122 uint32_t mbr_dus; 123 }; 124 125 #ifdef __cplusplus 126 } 127 #endif 128 129 #endif /* ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_ */ 130
