1 /* 2 * Copyright (c) 2018 Linaro Limited 3 * Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. 4 * Copyright (c) 2023 Antmicro <www.antmicro.com> 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef ZEPHYR_DRIVERS_SERIAL_UART_PL011_REGISTERS_H_ 10 #define ZEPHYR_DRIVERS_SERIAL_UART_PL011_REGISTERS_H_ 11 12 #include <zephyr/device.h> 13 14 /* 15 * UART PL011 register map structure 16 */ 17 struct pl011_regs { 18 uint32_t dr; /* data register */ 19 union { 20 uint32_t rsr; 21 uint32_t ecr; 22 }; 23 uint32_t reserved_0[4]; 24 uint32_t fr; /* flags register */ 25 uint32_t reserved_1; 26 uint32_t ilpr; 27 uint32_t ibrd; 28 uint32_t fbrd; 29 uint32_t lcr_h; 30 uint32_t cr; 31 uint32_t ifls; 32 uint32_t imsc; 33 uint32_t ris; 34 uint32_t mis; 35 uint32_t icr; 36 uint32_t dmacr; 37 }; 38 39 static inline get_uart(const struct device * dev)40volatile struct pl011_regs *const get_uart(const struct device *dev) 41 { 42 return (volatile struct pl011_regs *const)DEVICE_MMIO_GET(dev); 43 } 44 45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y) 46 47 /* PL011 Uart Flags Register */ 48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */ 49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */ 50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */ 51 #define PL011_FR_BUSY BIT(3) /* busy transmitting data */ 52 #define PL011_FR_RXFE BIT(4) /* receive FIFO empty */ 53 #define PL011_FR_TXFF BIT(5) /* transmit FIFO full */ 54 #define PL011_FR_RXFF BIT(6) /* receive FIFO full */ 55 #define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */ 56 #define PL011_FR_RI BIT(8) /* ring indicator - inverted */ 57 58 /* PL011 Integer baud rate register */ 59 #define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */ 60 61 /* PL011 Fractional baud rate register */ 62 #define PL011_FBRD_BAUD_DIVFRAC 0x3f 63 #define PL011_FBRD_WIDTH 6u 64 65 /* PL011 Receive status register / error clear register */ 66 #define PL011_RSR_ECR_FE BIT(0) /* framing error */ 67 #define PL011_RSR_ECR_PE BIT(1) /* parity error */ 68 #define PL011_RSR_ECR_BE BIT(2) /* break error */ 69 #define PL011_RSR_ECR_OE BIT(3) /* overrun error */ 70 71 #define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \ 72 PL011_RSR_ECR_BE | PL011_RSR_ECR_OE) 73 74 /* PL011 Line Control Register */ 75 #define PL011_LCRH_BRK BIT(0) /* send break */ 76 #define PL011_LCRH_PEN BIT(1) /* enable parity */ 77 #define PL011_LCRH_EPS BIT(2) /* select even parity */ 78 #define PL011_LCRH_STP2 BIT(3) /* select two stop bits */ 79 #define PL011_LCRH_FEN BIT(4) /* enable FIFOs */ 80 #define PL011_LCRH_WLEN_SHIFT 5 /* word length */ 81 #define PL011_LCRH_WLEN_WIDTH 2 82 #define PL011_LCRH_SPS BIT(7) /* stick parity bit */ 83 84 #define PL011_LCRH_WLEN_SIZE(x) (x - 5) 85 86 #define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \ 87 PL011_LCRH_SPS | \ 88 PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, PL011_LCRH_WLEN_SHIFT)) 89 90 #define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS) 91 #define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN) 92 #define PL011_LCRH_PARITY_NONE (0) 93 94 /* PL011 Control Register */ 95 #define PL011_CR_UARTEN BIT(0) /* enable uart operations */ 96 #define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */ 97 #define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */ 98 #define PL011_CR_LBE BIT(7) /* loop back enable */ 99 #define PL011_CR_TXE BIT(8) /* transmit enable */ 100 #define PL011_CR_RXE BIT(9) /* receive enable */ 101 #define PL011_CR_DTR BIT(10) /* data transmit ready */ 102 #define PL011_CR_RTS BIT(11) /* request to send */ 103 #define PL011_CR_Out1 BIT(12) 104 #define PL011_CR_Out2 BIT(13) 105 #define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable */ 106 #define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable */ 107 108 /* PL011 Control Register - vendor-specific fields */ 109 #define PL011_CR_AMBIQ_CLKEN BIT(3) /* clock enable */ 110 #define PL011_CR_AMBIQ_CLKSEL GENMASK(6, 4) /* clock select */ 111 #define PL011_CR_AMBIQ_CLKSEL_NOCLK 0 112 #define PL011_CR_AMBIQ_CLKSEL_24MHZ 1 113 #define PL011_CR_AMBIQ_CLKSEL_12MHZ 2 114 #define PL011_CR_AMBIQ_CLKSEL_6MHZ 3 115 #define PL011_CR_AMBIQ_CLKSEL_3MHZ 4 116 #define PL011_CR_AMBIQ_CLKSEL_48MHZ 5 117 118 /* PL011 Interrupt Fifo Level Select Register */ 119 #define PL011_IFLS_RXIFLSEL_M GENMASK(5, 3) 120 #define RXIFLSEL_1_2_FULL 2UL 121 #define PL011_IFLS_TXIFLSEL_M GENMASK(2, 0) 122 #define TXIFLSEL_1_8_FULL 0UL 123 124 /* PL011 Interrupt Mask Set/Clear Register */ 125 #define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */ 126 #define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */ 127 #define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */ 128 #define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */ 129 #define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */ 130 #define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */ 131 #define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt mask */ 132 #define PL011_IMSC_FEIM BIT(7) /* framing error interrupt mask */ 133 #define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask */ 134 #define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask */ 135 #define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt mask */ 136 137 #define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \ 138 PL011_IMSC_PEIM | PL011_IMSC_BEIM | \ 139 PL011_IMSC_OEIM) 140 141 #define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \ 142 PL011_IMSC_PEIM | PL011_IMSC_FEIM | \ 143 PL011_IMSC_RIMIM | PL011_IMSC_CTSMIM | \ 144 PL011_IMSC_DCDMIM | PL011_IMSC_DSRMIM | \ 145 PL011_IMSC_RXIM | PL011_IMSC_TXIM | \ 146 PL011_IMSC_RTIM) 147 148 /* PL011 Raw Interrupt Status Register */ 149 #define PL011_RIS_TXRIS BIT(5) /* Transmit interrupt status */ 150 151 152 #endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_REGISTERS_H_ */ 153
