1 /*
2 * Copyright (c) 2020 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/ztest.h>
8 #include <zephyr/drivers/spi.h>
9
10 #define TEST_FREQ_HZ 24000000U
11 #define W25Q128_JEDEC_ID 0x001840efU
12
13 #define TEST_BUF_SIZE 4096U
14 /* #define MAX_SPI_BUF 8 */
15
16 #define SPI_STATUS1_BUSY 0x01U
17 #define SPI_STATUS1_WEL 0x02U
18 #define SPI_STATUS2_QE 0x02U
19 #define SPI_READ_JEDEC_ID 0x9FU
20 #define SPI_READ_STATUS1 0x05U
21 #define SPI_READ_STATUS2 0x35U
22 #define SPI_WRITE_STATUS2 0x31U
23 #define SPI_WRITE_ENABLE_VS 0x50U
24 #define SPI_WRITE_ENABLE 0x06U
25 #define SPI_SECTOR_ERASE 0x20U
26 #define SPI_SINGLE_WRITE_DATA 0x02U
27 #define SPI_QUAD_WRITE_DATA 0x32U
28
29 /* bits[7:0] = spi opcode,
30 * bits[15:8] = bytes number of clocks with data lines tri-stated
31 */
32 #define SPI_FAST_READ_DATA 0x080BU
33 #define SPI_DUAL_FAST_READ_DATA 0x083BU
34 #define SPI_QUAD_FAST_READ_DATA 0x086BU
35 #define SPI_OCTAL_QUAD_READ_DATA 0xE3U
36
37 #define BUF_SIZE 11
38 uint8_t buffer_tx[] = "0123456789\0";
39 #define BUF_SIZE_2 7
40 uint8_t buffer_tx_2[] = "abcdef\0";
41
42 #define SPI_TEST_ADDRESS 0x000010U
43 #define SPI_TEST_ADDRESS_2 0x000020U
44
45 static uint8_t safbuf[TEST_BUF_SIZE] __aligned(4);
46 static uint8_t safbuf2[TEST_BUF_SIZE] __aligned(4);
47 static const struct device *const spi_dev = DEVICE_DT_GET(DT_NODELABEL(spi0));
48
49 /* static struct spi_buf spi_bufs[MAX_SPI_BUF]; */
50
51 static const struct spi_config spi_cfg_single = {
52 .frequency = TEST_FREQ_HZ,
53 .operation = (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8)
54 | SPI_LINES_SINGLE),
55 };
56
57 static const struct spi_config spi_cfg_single_hold_cs = {
58 .frequency = TEST_FREQ_HZ,
59 .operation = (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8)
60 | SPI_LINES_SINGLE | SPI_HOLD_ON_CS),
61 };
62
63 static const struct spi_config spi_cfg_dual = {
64 .frequency = TEST_FREQ_HZ,
65 .operation = (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8)
66 | SPI_LINES_DUAL),
67 };
68
69 static const struct spi_config spi_cfg_quad = {
70 .frequency = TEST_FREQ_HZ,
71 .operation = (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8)
72 | SPI_LINES_QUAD),
73 };
74
spi_single_init(void)75 static void spi_single_init(void)
76 {
77 zassert_true(device_is_ready(spi_dev), "SPI controller device is not ready");
78 }
79
clear_buffers(void)80 static void clear_buffers(void)
81 {
82 memset(safbuf, 0, sizeof(safbuf));
83 memset(safbuf2, 0, sizeof(safbuf2));
84 }
85
86 /* Compute the number of bytes required to generate the requested number of
87 * SPI clocks based on single, dual, or quad mode.
88 * mode = 1(full-duplex), 2(dual), 4(quad)
89 * full-duplex: 8 clocks per byte
90 * dual: 4 clocks per byte
91 * quad: 2 clocks per byte
92 */
spi_clocks_to_bytes(uint32_t spi_clocks,uint8_t mode)93 static uint32_t spi_clocks_to_bytes(uint32_t spi_clocks, uint8_t mode)
94 {
95 uint32_t nbytes;
96
97 if (mode == 4u) {
98 nbytes = spi_clocks / 2U;
99 } else if (mode == 2u) {
100 nbytes = spi_clocks / 4U;
101 } else {
102 nbytes = spi_clocks / 8U;
103 }
104
105 return nbytes;
106 }
107
108
spi_flash_address_format(uint8_t * dest,size_t destsz,uint32_t spi_addr,size_t addrsz)109 static int spi_flash_address_format(uint8_t *dest, size_t destsz,
110 uint32_t spi_addr, size_t addrsz)
111 {
112 if (!dest || (addrsz == 0) || (addrsz > 4U) || (addrsz > destsz)) {
113 return -EINVAL;
114 }
115
116 for (size_t i = 0; i < addrsz; i++) {
117 dest[i] = (uint8_t)((spi_addr >> ((addrsz - (i + 1U)) * 8U)) & 0xffU);
118 }
119
120 return 0;
121 }
122
spi_flash_read_status(const struct device * dev,uint8_t opcode,uint8_t * status)123 static int spi_flash_read_status(const struct device *dev, uint8_t opcode, uint8_t *status)
124 {
125 struct spi_buf spi_bufs[2] = { 0 };
126 uint32_t txdata = 0;
127 uint32_t rxdata = 0;
128 int ret = 0;
129
130 txdata = opcode;
131
132 spi_bufs[0].buf = &txdata;
133 spi_bufs[0].len = 1U;
134 spi_bufs[1].buf = &rxdata;
135 spi_bufs[1].len = 1U;
136
137 const struct spi_buf_set txset = {
138 .buffers = &spi_bufs[0],
139 .count = 2U,
140 };
141 const struct spi_buf_set rxset = {
142 .buffers = &spi_bufs[0],
143 .count = 2U,
144 };
145
146 ret = spi_transceive(spi_dev, &spi_cfg_single, &txset, &rxset);
147 if (ret) {
148 return ret;
149 }
150
151 if (status) {
152 *status = (uint8_t)(rxdata & 0xffu);
153 }
154
155 return 0;
156 }
157
spi_flash_write_status(const struct device * dev,uint8_t opcode,uint8_t spi_status)158 static int spi_flash_write_status(const struct device *dev, uint8_t opcode, uint8_t spi_status)
159 {
160 struct spi_buf spi_bufs[1] = { 0 };
161 uint32_t txdata = 0;
162 int ret = 0;
163
164 txdata = spi_status;
165 txdata <<= 8U;
166 txdata |= opcode;
167
168 spi_bufs[0].buf = &txdata;
169 spi_bufs[0].len = 2U;
170
171 const struct spi_buf_set txset = {
172 .buffers = &spi_bufs[0],
173 .count = 1U,
174 };
175
176 ret = spi_transceive(spi_dev, &spi_cfg_single, &txset, NULL);
177 if (ret) {
178 return ret;
179 }
180
181 return 0;
182 }
183
spi_flash_tx_one_byte_cmd(const struct device * dev,uint8_t opcode)184 static int spi_flash_tx_one_byte_cmd(const struct device *dev, uint8_t opcode)
185 {
186 struct spi_buf spi_bufs[1] = { 0 };
187 uint32_t txdata = 0;
188 int ret = 0;
189
190 txdata = opcode;
191 spi_bufs[0].buf = &txdata;
192 spi_bufs[0].len = 1U;
193
194 const struct spi_buf_set txset = {
195 .buffers = &spi_bufs[0],
196 .count = 1U,
197 };
198
199 ret = spi_transceive(spi_dev, &spi_cfg_single, &txset, NULL);
200 if (ret) {
201 return ret;
202 }
203
204 return 0;
205 }
206
207 /**
208 * @brief Test spi device
209 * @details
210 * - Find spi device
211 * - Read flash jedec id
212 */
ZTEST_USER(spi,test_spi_device)213 ZTEST_USER(spi, test_spi_device)
214 {
215 struct spi_buf spi_bufs[2] = { 0 };
216 uint32_t txdata = 0;
217 uint32_t jedec_id = 0;
218 int ret = 0;
219
220 /* read jedec id */
221 txdata = SPI_READ_JEDEC_ID;
222
223 spi_bufs[0].buf = &txdata;
224 spi_bufs[0].len = 1U;
225 spi_bufs[1].buf = &jedec_id;
226 spi_bufs[1].len = 3U;
227
228 const struct spi_buf_set txset = {
229 .buffers = &spi_bufs[0],
230 .count = 2U,
231 };
232 const struct spi_buf_set rxset = {
233 .buffers = &spi_bufs[0],
234 .count = 2U,
235 };
236
237 ret = spi_transceive(spi_dev, &spi_cfg_single, &txset, &rxset);
238 zassert_true(ret == 0, "Read JEDEC ID spi_transceive failure: "
239 "error %d", ret);
240 zassert_true(jedec_id == W25Q128_JEDEC_ID,
241 "JEDEC ID doesn't match: expected 0x%08x, read 0x%08x",
242 W25Q128_JEDEC_ID, jedec_id);
243 }
244
245 /**
246 * @brief Test spi sector erase
247 * @details
248 * - write enable
249 * - erase data in flash device
250 * - read register1 and wait for erase operation completed
251 */
ZTEST_USER(spi_sector_erase,test_spi_sector_erase)252 ZTEST_USER(spi_sector_erase, test_spi_sector_erase)
253 {
254 struct spi_buf spi_bufs[2] = { 0 };
255 int ret = 0;
256 uint8_t spi_status = 0;
257
258 clear_buffers();
259
260 /* write enable */
261 ret = spi_flash_tx_one_byte_cmd(spi_dev, SPI_WRITE_ENABLE);
262 zassert_true(ret == 0, "Send write enable spi_transceive failure: error %d", ret);
263
264 /* erase data start from address SPI_TEST_ADDRESS */
265 safbuf[0] = SPI_SECTOR_ERASE;
266 spi_flash_address_format(&safbuf[1], 4U, SPI_TEST_ADDRESS, 3U);
267
268 spi_bufs[0].buf = &safbuf;
269 spi_bufs[0].len = 4;
270
271 const struct spi_buf_set txset = {
272 .buffers = &spi_bufs[0],
273 .count = 1U,
274 };
275
276 ret = spi_transceive(spi_dev, &spi_cfg_single, &txset, NULL);
277 zassert_true(ret == 0, "Send sector erase data spi_transceive failure: error %d", ret);
278
279 /* read SPI flash status register1 to check whether erase operation completed */
280 spi_status = SPI_STATUS1_BUSY;
281 while (spi_status & SPI_STATUS1_BUSY) {
282 ret = spi_flash_read_status(spi_dev, SPI_READ_STATUS1, &spi_status);
283 zassert_true(ret == 0, "Send read register1 spi_transceive "
284 "failure: error %d", ret);
285 }
286 }
287
288 /**
289 * @brief Write data into flash using spi api
290 * @details
291 * - flash write enable
292 * - write data into flash using spi api
293 */
test_spi_single_write(void)294 static void test_spi_single_write(void)
295 {
296 struct spi_buf spi_bufs[1] = { 0 };
297 int ret = 0;
298 uint8_t spi_status = 0;
299
300 clear_buffers();
301
302 ret = spi_flash_tx_one_byte_cmd(spi_dev, SPI_WRITE_ENABLE);
303 zassert_true(ret == 0, "Send write enable spi_transceive failure: "
304 "error %d", ret);
305
306 /* write data start from address SPI_TEST_ADDRESS */
307 safbuf[0] = SPI_SINGLE_WRITE_DATA;
308 spi_flash_address_format(&safbuf[1], 4U, SPI_TEST_ADDRESS, 3U);
309
310 memcpy(&safbuf[4], buffer_tx, BUF_SIZE);
311
312 spi_bufs[0].buf = &safbuf;
313 spi_bufs[0].len = 4U + BUF_SIZE;
314
315 const struct spi_buf_set txset = {
316 .buffers = &spi_bufs[0],
317 .count = 1U,
318 };
319
320 ret = spi_transceive(spi_dev, &spi_cfg_single, &txset, NULL);
321 zassert_true(ret == 0, "Send write data spi_transceive failure: error %d", ret);
322
323 /* read register1 to check whether program operation completed */
324 spi_status = SPI_STATUS1_BUSY;
325 while (spi_status & SPI_STATUS1_BUSY) {
326 ret = spi_flash_read_status(spi_dev, SPI_READ_STATUS1, &spi_status);
327 zassert_true(ret == 0, "Read SPI flash STATUS opcode 0x%02x error: %d",
328 SPI_READ_STATUS1, ret);
329 }
330 }
331
332 /**
333 * @brief Read data from flash using spi single mode
334 * @details
335 * - read data using spi single mode
336 * - check read buffer data whether correct
337 * @note SPI flash fast instructions require a certain number of SPI clocks
338 * to be generated with I/O lines tri-stated after the address has been
339 * transmitted. The purpose is allow SPI flash time to move get data ready
340 * and enable its output line(s). The MCHP XEC SPI driver can do this by
341 * specifying a struct spi_buf with buf pointer set to NULL and length set
342 * to the number of bytes which will generate the required number of clocks.
343 * For full-duplex one byte is 8 clocks, dual one byte is 4 clocks, and for
344 * quad one byte is 2 clocks.
345 */
ZTEST_USER(spi,test_spi_single_read)346 ZTEST_USER(spi, test_spi_single_read)
347 {
348 struct spi_buf spi_bufs[3] = { 0 };
349 int ret = 0;
350 uint16_t spi_opcode = 0;
351 uint8_t cnt = 0;
352
353 clear_buffers();
354
355 /* bits[7:0] = opcode,
356 * bits[15:8] = number of SPI clocks with I/O lines tri-stated after
357 * address transmit before data read phase.
358 */
359 spi_opcode = SPI_FAST_READ_DATA;
360
361 /* read data using spi single mode */
362 /* set the spi operation code and address */
363 safbuf[0] = spi_opcode & 0xFFU;
364 spi_flash_address_format(&safbuf[1], 4U, SPI_TEST_ADDRESS, 3U);
365
366 spi_bufs[cnt].buf = &safbuf;
367 spi_bufs[cnt].len = 4U;
368
369 /* set the dummy clocks */
370 if (spi_opcode & 0xFF00U) {
371 cnt++;
372 spi_bufs[cnt].buf = NULL;
373 spi_bufs[cnt].len = spi_clocks_to_bytes(((spi_opcode >> 8) & 0xffU), 1u);
374 }
375
376 cnt++;
377 spi_bufs[cnt].buf = &safbuf2;
378 spi_bufs[cnt].len = BUF_SIZE;
379 cnt++; /* total number of buffers */
380
381 const struct spi_buf_set txset = {
382 .buffers = &spi_bufs[0],
383 .count = cnt,
384 };
385
386 const struct spi_buf_set rxset = {
387 .buffers = &spi_bufs[0],
388 .count = cnt,
389 };
390
391 ret = spi_transceive(spi_dev, &spi_cfg_single, &txset, &rxset);
392 zassert_true(ret == 0, "Send fast read data spi_transceive failure: error %d", ret);
393
394 /* check read buffer data whether correct */
395 zassert_true(memcmp(buffer_tx, safbuf2, BUF_SIZE) == 0,
396 "Buffer read data is different to write data");
397 }
398
spi_dual_init(void)399 static void spi_dual_init(void)
400 {
401 zassert_true(device_is_ready(spi_dev), "SPI controller device is not ready");
402 }
403
404 /**
405 * @brief Read data from flash using spi dual mode
406 * @details
407 * - read data using spi dual mode
408 * - check read buffer data whether correct
409 */
ZTEST_USER(spi,test_spi_dual_read)410 ZTEST_USER(spi, test_spi_dual_read)
411 {
412 struct spi_buf spi_bufs[3] = { 0 };
413 int ret = 0;
414 uint16_t spi_opcode = 0;
415 uint8_t cnt = 0;
416
417 clear_buffers();
418
419 spi_dual_init();
420
421 spi_opcode = SPI_DUAL_FAST_READ_DATA;
422
423 /* read data using spi dual mode */
424 /* set the spi operation code and address */
425 safbuf[0] = spi_opcode & 0xFFU;
426 spi_flash_address_format(&safbuf[1], 4U, SPI_TEST_ADDRESS, 3U);
427
428 spi_bufs[cnt].buf = &safbuf;
429 spi_bufs[cnt].len = 4U;
430
431 /* set the dummy clocks */
432 if (spi_opcode & 0xFF00U) {
433 cnt++;
434 spi_bufs[cnt].buf = NULL;
435 spi_bufs[cnt].len = spi_clocks_to_bytes(((spi_opcode >> 8) & 0xffU), 1u);
436 }
437
438 cnt++;
439 spi_bufs[cnt].buf = &safbuf2;
440 spi_bufs[cnt].len = BUF_SIZE;
441
442 const struct spi_buf_set txset = {
443 .buffers = &spi_bufs[0],
444 .count = cnt,
445 };
446
447 const struct spi_buf_set rxset = {
448 .buffers = &spi_bufs[cnt],
449 .count = 1U,
450 };
451
452 /* send opcode, address, and tri-state clocks using single mode */
453 ret = spi_transceive(spi_dev, &spi_cfg_single_hold_cs, &txset, NULL);
454 zassert_true(ret == 0, "Send fast read data spi_transceive failure: error %d", ret);
455
456 /* get read data using dual mode */
457 ret = spi_transceive(spi_dev, &spi_cfg_dual, NULL, &rxset);
458 zassert_true(ret == 0, "Receive fast read data spi_transceive failure: error %d", ret);
459
460 /* check read buffer data whether correct */
461 zassert_true(memcmp(buffer_tx, safbuf2, BUF_SIZE) == 0,
462 "Buffer read data is different to write data");
463
464 /* release spi device */
465 ret = spi_release(spi_dev, &spi_cfg_single);
466 zassert_true(ret == 0, "Spi release failure: error %d", ret);
467 }
468
469 /**
470 * @brief Write data into flash using spi quad mode
471 * @details
472 * - check and make sure spi quad mode is enabled
473 * - write data using spi quad mode
474 */
test_spi_quad_write(void)475 static void test_spi_quad_write(void)
476 {
477 struct spi_buf spi_bufs[2] = { 0 };
478 int ret = 0;
479 uint8_t spi_status = 0;
480 uint8_t spi_status2 = 0;
481
482 clear_buffers();
483
484 /* read register2 to judge whether quad mode is enabled */
485 ret = spi_flash_read_status(spi_dev, SPI_READ_STATUS2, &spi_status2);
486 zassert_true(ret == 0, "SPI read flash STATUS2 failure: error %d", ret);
487
488 /* set register2 QE=1 to enable quad mode. We write the volatile STATUS2 register
489 * not the normal STATUS2 which retains the value across a power cycle.
490 */
491 if ((spi_status2 & SPI_STATUS2_QE) == 0U) {
492 ret = spi_flash_tx_one_byte_cmd(spi_dev, SPI_WRITE_ENABLE_VS);
493 zassert_true(ret == 0, "Send write enable volatile spi_transceive failure: "
494 "error %d", ret);
495
496 spi_status2 |= SPI_STATUS2_QE;
497 ret = spi_flash_write_status(spi_dev, SPI_WRITE_STATUS2, spi_status2);
498 zassert_true(ret == 0, "Write spi status2 QE=1 spi_transceive failure: "
499 "error %d", ret);
500
501 /* read register2 to confirm quad mode is enabled */
502 spi_status2 = 0u;
503 ret = spi_flash_read_status(spi_dev, SPI_READ_STATUS2, &spi_status2);
504 zassert_true(ret == 0, "Read register2 status spi_transceive failure: "
505 "error %d", ret);
506
507 zassert_true((spi_status2 & SPI_STATUS2_QE) == SPI_STATUS2_QE,
508 "Enable QSPI mode failure");
509 }
510
511 /* write enable */
512 ret = spi_flash_tx_one_byte_cmd(spi_dev, SPI_WRITE_ENABLE);
513 zassert_true(ret == 0, "Send write enable spi_transceive failure: error %d", ret);
514
515 /* write data using spi quad mode */
516 /* send quad write opcode and address using single mode */
517 safbuf[0] = SPI_QUAD_WRITE_DATA;
518 spi_flash_address_format(&safbuf[1], 4U, SPI_TEST_ADDRESS_2, 3U);
519
520 spi_bufs[0].buf = &safbuf;
521 spi_bufs[0].len = 4;
522
523 const struct spi_buf_set txset = {
524 .buffers = &spi_bufs[0],
525 .count = 1U,
526 };
527
528 ret = spi_transceive(spi_dev, &spi_cfg_single_hold_cs, &txset, NULL);
529 zassert_true(ret == 0, "Send quad write data spi_transceive failure: error %d", ret);
530
531 /* send data using quad mode */
532 memcpy(&safbuf[0], buffer_tx_2, BUF_SIZE_2);
533
534 spi_bufs[0].buf = &safbuf;
535 spi_bufs[0].len = BUF_SIZE_2;
536
537 ret = spi_transceive(spi_dev, &spi_cfg_quad, &txset, NULL);
538 zassert_true(ret == 0, "Send quad write data spi_transceive failure: error %d", ret);
539
540 /* call SPI release API to clear SPI CS Hold On lock */
541 ret = spi_release(spi_dev, &spi_cfg_single);
542 zassert_true(ret == 0, "Spi release failure: error %d", ret);
543
544 /* poll busy bit in flash status1 register */
545 spi_status = SPI_STATUS1_BUSY;
546 while (spi_status & SPI_STATUS1_BUSY) {
547 ret = spi_flash_read_status(spi_dev, SPI_READ_STATUS1, &spi_status);
548 zassert_true(ret == 0, "Read flash STATUS1 register error %d", ret);
549 }
550 }
551
552 /**
553 * @brief Read data from flash using spi quad mode
554 * @details
555 * - read data using spi quad mode
556 * - check read buffer data whether correct
557 */
ZTEST_USER(spi_quad,test_spi_quad_read)558 ZTEST_USER(spi_quad, test_spi_quad_read)
559 {
560 struct spi_buf spi_bufs[3] = {0};
561 int ret = 0;
562 uint16_t spi_opcode = 0;
563 uint8_t cnt = 0;
564
565 clear_buffers();
566
567 spi_opcode = SPI_QUAD_FAST_READ_DATA;
568
569 /* read data using spi quad mode
570 * Transmit opcode, address, and tri-state clocks using full-duplex mode
571 * with driver Hold CS ON flag.
572 * Next, read data using dual configuration.
573 * Call driver release API to release lock set by Hold CS ON flag.
574 */
575
576 /* set the spi operation code and address */
577 safbuf[0] = spi_opcode & 0xFFU;
578 spi_flash_address_format(&safbuf[1], 4U, SPI_TEST_ADDRESS_2, 3U);
579
580 spi_bufs[cnt].buf = &safbuf;
581 spi_bufs[cnt].len = 4U;
582
583 /* set the dummy clocks */
584 if (spi_opcode & 0xFF00U) {
585 cnt++;
586 spi_bufs[cnt].buf = NULL;
587 spi_bufs[cnt].len = spi_clocks_to_bytes(((spi_opcode >> 8) & 0xffU), 1u);
588 }
589
590 cnt++;
591 spi_bufs[cnt].buf = &safbuf2;
592 spi_bufs[cnt].len = BUF_SIZE_2;
593
594 const struct spi_buf_set txset = {
595 .buffers = &spi_bufs[0],
596 .count = cnt,
597 };
598
599 const struct spi_buf_set rxset = {
600 .buffers = &spi_bufs[cnt],
601 .count = 1U,
602 };
603
604 /* send opcode and address using single mode with Hold CS ON flag */
605 ret = spi_transceive(spi_dev, &spi_cfg_single_hold_cs, &txset, NULL);
606 zassert_true(ret == 0, "Send fast read data spi_transceive failure: error %d", ret);
607
608 /* read data using quad mode */
609 ret = spi_transceive(spi_dev, &spi_cfg_quad, NULL, &rxset);
610 zassert_true(ret == 0, "Receive fast read data spi_transceive failure: error %d", ret);
611
612 /* release spi device */
613 ret = spi_release(spi_dev, &spi_cfg_single);
614 zassert_true(ret == 0, "Spi release failure: error %d", ret);
615
616 /* check read buffer data whether correct */
617 zassert_true(memcmp(buffer_tx_2, safbuf2, BUF_SIZE_2) == 0,
618 "Buffer read data is different to write data");
619 }
620
spi_setup(void)621 void *spi_setup(void)
622 {
623 spi_single_init();
624
625 return NULL;
626 }
627
spi_single_setup(void)628 void *spi_single_setup(void)
629 {
630 spi_single_init();
631
632 /* The writing test goes
633 * first berfore testing
634 * the reading.
635 */
636 test_spi_single_write();
637
638 return NULL;
639 }
640
spi_quad_setup(void)641 void *spi_quad_setup(void)
642 {
643 spi_dual_init();
644
645 /* The writing test goes
646 * first berfore testing
647 * the reading.
648 */
649 test_spi_quad_write();
650
651 return NULL;
652 }
653
654 /* Test assumes flash test regions is in erased state */
655 ZTEST_SUITE(spi, NULL, spi_single_setup, NULL, NULL, NULL);
656 ZTEST_SUITE(spi_quad, NULL, spi_quad_setup, NULL, NULL, NULL);
657 ZTEST_SUITE(spi_sector_erase, NULL, spi_setup, NULL, NULL, NULL);
658
