1/*
2 * Copyright 2024-2025 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/clock/scg_k4.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14
15/ {
16	aliases {
17		watchdog0 = &wdog0;
18	};
19
20	chosen {
21		zephyr,bt-hci = &hci;
22		zephyr,ieee802154 = &ieee802154;
23		zephyr,entropy = &trng;
24		zephyr,nbu = &nbu;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu0: cpu@0 {
32			compatible = "arm,cortex-m33f";
33			reg = <0>;
34			#address-cells = <1>;
35			#size-cells = <1>;
36
37			mpu: mpu@e000ed90 {
38				compatible = "arm,armv8m-mpu";
39				reg = <0xe000ed90 0x40>;
40			};
41		};
42	};
43
44	soc {
45		fmu: memory-controller@50020000 {
46			#address-cells = <1>;
47			#size-cells = <1>;
48			compatible = "nxp,msf1";
49			reg = <0x50020000 0x30>;
50			interrupts = <27 0>;
51			status = "disabled";
52
53			flash: flash@0 {
54				compatible = "soc-nv-flash";
55				write-block-size = <16>;
56				erase-block-size = <8192>;
57			};
58		};
59
60		ctcm: sram@14000000 {
61			#address-cells = <1>;
62			#size-cells = <1>;
63
64			ctcm0: code_memory@0 {
65				compatible = "mmio-sram";
66			};
67		};
68
69		stcm: sram@30000000 {
70			#address-cells = <1>;
71			#size-cells = <1>;
72
73			stcm0: system_memory@0 {
74				compatible = "mmio-sram";
75			};
76		};
77
78		peripheral: peripheral@50000000 {
79			ranges = <0x0 0x50000000 0x10000000>;
80			#address-cells = <1>;
81			#size-cells = <1>;
82
83			pbridge2: pbridge2@0 {
84				ranges = <>;
85				#address-cells = <1>;
86				#size-cells = <1>;
87			};
88
89			fast_peripheral0: fast_peripherals0@8000000 {
90				#address-cells = <1>;
91				#size-cells = <1>;
92				ranges = <0x0 0x8000000 0x40000>;
93			};
94
95			fast_peripheral1: fast_peripherals1@8800000 {
96				#address-cells = <1>;
97				#size-cells = <1>;
98				ranges = <0x0 0x8800000 0x20a000>;
99			};
100		};
101	};
102
103	pinctrl: pinctrl {
104		compatible = "nxp,port-pinctrl";
105	};
106};
107
108&nvic {
109	arm,num-irq-priority-bits = <3>;
110};
111
112&pbridge2 {
113	#address-cells = <1>;
114	#size-cells = <1>;
115
116	scg: clock-controller@1e000 {
117		compatible = "nxp,scg-k4";
118		reg = <0x1e000 0x404>;
119		#clock-cells = <2>;
120	};
121
122	porta: pinctrl@42000 {
123		compatible = "nxp,port-pinmux";
124		clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
125	};
126
127	portb: pinctrl@43000 {
128		compatible = "nxp,port-pinmux";
129		clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
130	};
131
132	portc: pinctrl@44000 {
133		compatible = "nxp,port-pinmux";
134		clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
135	};
136
137	portd: pinctrl@45000 {
138		compatible = "nxp,port-pinmux";
139		clocks = <&scg SCG_K4_SLOW_CLK 0>;
140	};
141
142	lpuart0: serial@38000 {
143		compatible = "nxp,lpuart";
144		reg = <0x38000 0x34>;
145		interrupts = <44 0>;
146		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
147		status = "disabled";
148	};
149
150	lpuart1: serial@39000 {
151		compatible = "nxp,lpuart";
152		reg = <0x39000 0x34>;
153		interrupts = <45 0>;
154		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
155		status = "disabled";
156	};
157
158	lpi2c0: i2c@33000 {
159		compatible = "nxp,lpi2c";
160		reg = <0x33000 0x17c>;
161		clock-frequency = <I2C_BITRATE_STANDARD>;
162		#address-cells = <1>;
163		#size-cells = <0>;
164		interrupts = <39 0>;
165		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
166		status = "disabled";
167	};
168
169	lpi2c1: i2c@34000 {
170		compatible = "nxp,lpi2c";
171		reg = <0x34000 0x17c>;
172		clock-frequency = <I2C_BITRATE_STANDARD>;
173		#address-cells = <1>;
174		#size-cells = <0>;
175		interrupts = <40 0>;
176		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
177		status = "disabled";
178	};
179
180	lpspi0: spi@36000 {
181		compatible = "nxp,lpspi";
182		reg = <0x36000 0x800>;
183		interrupts = <42 0>;
184		clocks = <&scg SCG_K4_FIRC_CLK 0xd8>;
185		tx-fifo-size = <8>;
186		rx-fifo-size = <8>;
187		#address-cells = <1>;
188		#size-cells = <0>;
189		status = "disabled";
190	};
191
192	lpspi1: spi@37000 {
193		compatible = "nxp,lpspi";
194		reg = <0x37000 0x800>;
195		interrupts = <43 0>;
196		clocks = <&scg SCG_K4_FIRC_CLK 0xdc>;
197		tx-fifo-size = <8>;
198		rx-fifo-size = <8>;
199		#address-cells = <1>;
200		#size-cells = <0>;
201		status = "disabled";
202	};
203
204	gpiod: gpio@46000{
205		compatible = "nxp,kinetis-gpio";
206		reg = <0x46000 0x128>;
207		interrupts = <65 0>, <66 0>;
208		gpio-controller;
209		#gpio-cells = <2>;
210		nxp,kinetis-port = <&portd>;
211		status = "disabled";
212	};
213
214	vbat: vbat@2b000 {
215		reg = <0x2b000 0x33c>;
216		interrupts = <74 0>;
217	};
218
219	tpm0: pwm@31000 {
220		compatible = "nxp,kinetis-tpm";
221		reg = <0x31000 0x88>;
222		interrupts = <37 0>;
223		clocks = <&scg SCG_K4_FIRC_CLK 0xc4>;
224		prescaler = <16>;
225		status = "disabled";
226		#pwm-cells = <3>;
227	};
228
229	tpm1: pwm@32000 {
230		compatible = "nxp,kinetis-tpm";
231		reg = <0x32000 0x88>;
232		interrupts = <38 0>;
233		clocks = <&scg SCG_K4_FIRC_CLK 0xc8>;
234		prescaler = <16>;
235		status = "disabled";
236		#pwm-cells = <3>;
237	};
238
239	wdog0: watchdog@1a000 {
240		compatible = "nxp,wdog32";
241		reg = <0x1a000 10>;
242		interrupts = <23 0>;
243		clocks = <&scg SCG_K4_SYSOSC_CLK 0x68>;
244		clk-source = <1>;
245		clk-divider = <256>;
246		status = "okay";
247	};
248
249	wdog1: watchdog@1b000 {
250		compatible = "nxp,wdog32";
251		reg = <0x1b000 10>;
252		interrupts = <24 0>;
253		clocks = <&scg SCG_K4_SYSOSC_CLK 0x6c>;
254		clk-source = <1>;
255		clk-divider = <256>;
256		status = "disabled";
257	};
258
259	lptmr0: timer@2d000 {
260		compatible = "nxp,lptmr";
261		reg = <0x2d000 0x10>;
262		interrupts = <34 0>;
263		clock-frequency = <32000>;
264		clk-source = <2>;
265		prescaler = <1>;
266		resolution = <32>;
267		status = "disabled";
268	};
269
270	lptmr1: timer@2e000 {
271		compatible = "nxp,lptmr";
272		reg = <0x2e000 0x10>;
273		interrupts = <35 0>;
274		clock-frequency = <32000>;
275		clk-source = <2>;
276		prescaler = <1>;
277		resolution = <32>;
278		status = "disabled";
279	};
280
281	nbu: nbu {
282		compatible = "nxp,nbu";
283		interrupts = <48 2>;
284		interrupt-names = "nbu_rx_int";
285	};
286
287	hci: hci_ble {
288		compatible = "nxp,hci-ble";
289	};
290
291	ieee802154: ieee802154 {
292		compatible = "nxp,mcxw-ieee802154";
293	};
294
295	trng: trng {
296		compatible = "nxp,ele-trng";
297	};
298
299	flexcan0: can@3b000 {
300		compatible = "nxp,flexcan";
301		reg = <0x3b000 0x3080>;
302		interrupts = <47 0>;
303		interrupt-names = "common";
304		clocks = <&scg SCG_K4_FIRC_CLK 0xec>;
305		clk-source = <2>;
306		status = "disabled";
307	};
308
309	adc0: adc@47000 {
310		compatible = "nxp,lpc-lpadc";
311		reg = <0x47000 0x584>;
312		interrupts = <71 0>;
313		clocks = <&scg SCG_K4_FIRC_CLK 0x11c>;
314		voltage-ref= <1>;
315		calibration-average = <128>;
316		/* pwrlvl 0 is slow speed low power, 1 is opposite */
317		power-level = <0>;
318		offset-value-a = <0>;
319		offset-value-b = <0>;
320		#io-channel-cells = <1>;
321		nxp,references = <&vref 1800>;
322		status = "disabled";
323	};
324
325	vref: regulator@4a000 {
326		compatible = "nxp,vref";
327		reg = <0x4a000 0x14>;
328		regulator-name = "mcxw71-vref";
329		#nxp,reference-cells = <1>;
330		nxp,buffer-startup-delay-us = <400>;
331		nxp,bandgap-startup-time-us = <20>;
332		regulator-min-microvolt = <1000000>;
333		regulator-max-microvolt = <2100000>;
334		nxp,current-compensation-en;
335		status = "disabled";
336	};
337
338	rtc: rtc@4002c000 {
339		compatible = "nxp,rtc";
340		status = "disabled";
341		interrupts = <32 0>, <33 0>;
342		interrupt-names = "alarm", "seconds";
343		clock-frequency = <32768>;
344		prescaler = <32768>;
345	};
346};
347
348&fast_peripheral0 {
349	gpioa: gpio@10000{
350		compatible = "nxp,kinetis-gpio";
351		status = "disabled";
352		gpio-controller;
353		#gpio-cells = <2>;
354		nxp,kinetis-port = <&porta>;
355		reg = <0x10000 0x128>;
356		interrupts = <59 0>, <60 0>;
357	};
358
359	gpiob: gpio@20000{
360		compatible = "nxp,kinetis-gpio";
361		status = "disabled";
362		gpio-controller;
363		#gpio-cells = <2>;
364		nxp,kinetis-port = <&portb>;
365		reg = <0x20000 0x128>;
366		interrupts = <61 0>, <62 0>;
367	};
368
369	gpioc: gpio@30000{
370		compatible = "nxp,kinetis-gpio";
371		status = "disabled";
372		gpio-controller;
373		#gpio-cells = <2>;
374		nxp,kinetis-port = <&portc>;
375		reg = <0x30000 0x128>;
376		interrupts = <63 0>, <64 0>;
377	};
378};
379
380&fast_peripheral1 {
381	smu2: smu2@1c0000 {
382		#address-cells = <1>;
383		#size-cells = <1>;
384
385		rpmsgmem: memory@8800 {
386			compatible = "zephyr,memory-region","mmio-sram";
387			reg = <0x8800 DT_SIZE_K(6)>;
388			zephyr,memory-region = "rpmsg_sh_mem";
389			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
390		};
391	};
392};
393