1 /* 2 * Copyright (c) 2020, Seagate Technology LLC 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_ 8 #define ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_ 9 10 #include <zephyr/drivers/pinctrl.h> 11 12 #define PINCTRL_STATE_FAST_PLUS PINCTRL_STATE_PRIV_START 13 14 #define LPC11U6X_I2C_CONTROL_AA (1 << 2) 15 #define LPC11U6X_I2C_CONTROL_SI (1 << 3) 16 #define LPC11U6X_I2C_CONTROL_STOP (1 << 4) 17 #define LPC11U6X_I2C_CONTROL_START (1 << 5) 18 #define LPC11U6X_I2C_CONTROL_I2C_EN (1 << 6) 19 20 /* I2C controller states */ 21 #define LPC11U6X_I2C_MASTER_TX_START 0x08 22 #define LPC11U6X_I2C_MASTER_TX_RESTART 0x10 23 #define LPC11U6X_I2C_MASTER_TX_ADR_ACK 0x18 24 #define LPC11U6X_I2C_MASTER_TX_ADR_NACK 0x20 25 #define LPC11U6X_I2C_MASTER_TX_DAT_ACK 0x28 26 #define LPC11U6X_I2C_MASTER_TX_DAT_NACK 0x30 27 #define LPC11U6X_I2C_MASTER_TX_ARB_LOST 0x38 28 29 #define LPC11U6X_I2C_MASTER_RX_ADR_ACK 0x40 30 #define LPC11U6X_I2C_MASTER_RX_ADR_NACK 0x48 31 #define LPC11U6X_I2C_MASTER_RX_DAT_ACK 0x50 32 #define LPC11U6X_I2C_MASTER_RX_DAT_NACK 0x58 33 34 #define LPC11U6X_I2C_SLAVE_RX_ADR_ACK 0x60 35 #define LPC11U6X_I2C_SLAVE_RX_ARB_LOST_ADR_ACK 0x68 36 #define LPC11U6X_I2C_SLAVE_RX_GC_ACK 0x70 37 #define LPC11U6X_I2C_SLAVE_RX_ARB_LOST_GC_ACK 0x78 38 #define LPC11U6X_I2C_SLAVE_RX_DAT_ACK 0x80 39 #define LPC11U6X_I2C_SLAVE_RX_DAT_NACK 0x88 40 #define LPC11U6X_I2C_SLAVE_RX_GC_DAT_ACK 0x90 41 #define LPC11U6X_I2C_SLAVE_RX_GC_DAT_NACK 0x98 42 #define LPC11U6X_I2C_SLAVE_RX_STOP 0xA0 43 44 #define LPC11U6X_I2C_SLAVE_TX_ADR_ACK 0xA8 45 #define LPC11U6X_I2C_SLAVE_TX_ARB_LOST_ADR_ACK 0xB0 46 #define LPC11U6X_I2C_SLAVE_TX_DAT_ACK 0xB8 47 #define LPC11U6X_I2C_SLAVE_TX_DAT_NACK 0xC0 48 #define LPC11U6X_I2C_SLAVE_TX_LAST_BYTE 0xC8 49 50 /* Transfer Status */ 51 #define LPC11U6X_I2C_STATUS_BUSY 0x01 52 #define LPC11U6X_I2C_STATUS_OK 0x02 53 #define LPC11U6X_I2C_STATUS_FAIL 0x03 54 #define LPC11U6X_I2C_STATUS_INACTIVE 0x04 55 56 struct lpc11u6x_i2c_regs { 57 volatile uint32_t con_set; /* Control set */ 58 volatile const uint32_t stat; /* Status */ 59 volatile uint32_t dat; /* Data */ 60 volatile uint32_t addr0; /* Slave address 0 */ 61 volatile uint32_t sclh; /* SCL Duty Cycle */ 62 volatile uint32_t scll; /* SCL Duty Cycle */ 63 volatile uint32_t con_clr; /* Control clear */ 64 volatile uint32_t mm_ctrl; /* Monitor mode control */ 65 volatile uint32_t addr[3]; /* Slave address {1,2,3} */ 66 volatile const uint32_t data_buffer; /* Data buffer */ 67 volatile uint32_t mask[4]; /* Slave address mask */ 68 }; 69 70 struct lpc11u6x_i2c_config { 71 struct lpc11u6x_i2c_regs *base; 72 const struct device *clock_dev; 73 void (*irq_config_func)(const struct device *dev); 74 uint32_t clkid; 75 const struct pinctrl_dev_config *pincfg; 76 }; 77 78 struct lpc11u6x_i2c_current_transfer { 79 struct i2c_msg *msgs; 80 uint8_t *curr_buf; 81 uint8_t curr_len; 82 uint8_t nr_msgs; 83 uint8_t addr; 84 uint8_t status; 85 }; 86 87 struct lpc11u6x_i2c_data { 88 struct lpc11u6x_i2c_current_transfer transfer; 89 struct i2c_target_config *slave; 90 struct k_sem completion; 91 struct k_mutex mutex; 92 }; 93 94 #endif /* ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_ */ 95
