1 /** Copyright 2021 Espressif Systems (Shanghai) CO LTD 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #pragma once 16 17 #include <stdint.h> 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /** Group: Timing registers */ 23 /** Type of scl_low_period register 24 * Configures the low level width of the SCL 25 * Clock 26 */ 27 typedef union { 28 struct { 29 /** scl_low_period : R/W; bitpos: [8:0]; default: 0; 30 * This register is used to configure for how long SCL remains low in master mode, in 31 * I2C module clock cycles. 32 */ 33 uint32_t scl_low_period:9; 34 uint32_t reserved_9:23; 35 }; 36 uint32_t val; 37 } i2c_scl_low_period_reg_t; 38 39 /** Type of sda_hold register 40 * Configures the hold time after a negative SCL edge. 41 */ 42 typedef union { 43 struct { 44 /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; 45 * This register is used to configure the time to hold the data after the negative 46 * edge of SCL, in I2C module clock cycles. 47 */ 48 uint32_t sda_hold_time:9; 49 uint32_t reserved_9:23; 50 }; 51 uint32_t val; 52 } i2c_sda_hold_reg_t; 53 54 /** Type of sda_sample register 55 * Configures the sample time after a positive SCL edge. 56 */ 57 typedef union { 58 struct { 59 /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; 60 * This register is used to configure for how long SDA is sampled, in I2C module clock 61 * cycles. 62 */ 63 uint32_t sda_sample_time:9; 64 uint32_t reserved_9:23; 65 }; 66 uint32_t val; 67 } i2c_sda_sample_reg_t; 68 69 /** Type of scl_high_period register 70 * Configures the high level width of SCL 71 */ 72 typedef union { 73 struct { 74 /** scl_high_period : R/W; bitpos: [8:0]; default: 0; 75 * This register is used to configure for how long SCL remains high in master mode, in 76 * I2C module clock cycles. 77 */ 78 uint32_t scl_high_period:9; 79 /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; 80 * This register is used to configure for the SCL_FSM's waiting period for SCL high 81 * level in master mode, in I2C module clock cycles. 82 */ 83 uint32_t scl_wait_high_period:7; 84 uint32_t reserved_16:16; 85 }; 86 uint32_t val; 87 } i2c_scl_high_period_reg_t; 88 89 /** Type of scl_start_hold register 90 * Configures the delay between the SDA and SCL negative edge for a start condition 91 */ 92 typedef union { 93 struct { 94 /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; 95 * This register is used to configure the time between the negative edge 96 * of SDA and the negative edge of SCL for a START condition, in I2C module clock 97 * cycles. 98 */ 99 uint32_t scl_start_hold_time:9; 100 uint32_t reserved_9:23; 101 }; 102 uint32_t val; 103 } i2c_scl_start_hold_reg_t; 104 105 /** Type of scl_rstart_setup register 106 * Configures the delay between the positive 107 * edge of SCL and the negative edge of SDA 108 */ 109 typedef union { 110 struct { 111 /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; 112 * This register is used to configure the time between the positive 113 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module 114 * clock cycles. 115 */ 116 uint32_t scl_rstart_setup_time:9; 117 uint32_t reserved_9:23; 118 }; 119 uint32_t val; 120 } i2c_scl_rstart_setup_reg_t; 121 122 /** Type of scl_stop_hold register 123 * Configures the delay after the SCL clock 124 * edge for a stop condition 125 */ 126 typedef union { 127 struct { 128 /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; 129 * This register is used to configure the delay after the STOP condition, 130 * in I2C module clock cycles. 131 */ 132 uint32_t scl_stop_hold_time:9; 133 uint32_t reserved_9:23; 134 }; 135 uint32_t val; 136 } i2c_scl_stop_hold_reg_t; 137 138 /** Type of scl_stop_setup register 139 * Configures the delay between the SDA and 140 * SCL positive edge for a stop condition 141 */ 142 typedef union { 143 struct { 144 /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; 145 * This register is used to configure the time between the positive edge 146 * of SCL and the positive edge of SDA, in I2C module clock cycles. 147 */ 148 uint32_t scl_stop_setup_time:9; 149 uint32_t reserved_9:23; 150 }; 151 uint32_t val; 152 } i2c_scl_stop_setup_reg_t; 153 154 /** Type of scl_st_time_out register 155 * SCL status time out register 156 */ 157 typedef union { 158 struct { 159 /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; 160 * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 161 */ 162 uint32_t scl_st_to_i2c:5; 163 uint32_t reserved_5:27; 164 }; 165 uint32_t val; 166 } i2c_scl_st_time_out_reg_t; 167 168 /** Type of scl_main_st_time_out register 169 * SCL main status time out register 170 */ 171 typedef union { 172 struct { 173 /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; 174 * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more 175 * than 23 176 */ 177 uint32_t scl_main_st_to_i2c:5; 178 uint32_t reserved_5:27; 179 }; 180 uint32_t val; 181 } i2c_scl_main_st_time_out_reg_t; 182 183 184 /** Group: Configuration registers */ 185 /** Type of ctr register 186 * Transmission setting 187 */ 188 typedef union { 189 struct { 190 /** sda_force_out : R/W; bitpos: [0]; default: 1; 191 * 0: direct output; 1: open drain output. 192 */ 193 uint32_t sda_force_out:1; 194 /** scl_force_out : R/W; bitpos: [1]; default: 1; 195 * 0: direct output; 1: open drain output. 196 */ 197 uint32_t scl_force_out:1; 198 /** sample_scl_level : R/W; bitpos: [2]; default: 0; 199 * This register is used to select the sample mode. 200 * 1: sample SDA data on the SCL low level. 201 * 0: sample SDA data on the SCL high level. 202 */ 203 uint32_t sample_scl_level:1; 204 /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; 205 * This register is used to configure the ACK value that need to sent by master when 206 * the rx_fifo_cnt has reached the threshold. 207 */ 208 uint32_t rx_full_ack_level:1; 209 /** ms_mode : R/W; bitpos: [4]; default: 0; 210 * Set this bit to configure the module as an I2C Master. Clear this bit to configure 211 * the 212 * module as an I2C Slave. 213 */ 214 uint32_t ms_mode:1; 215 /** trans_start : WT; bitpos: [5]; default: 0; 216 * Set this bit to start sending the data in txfifo. 217 */ 218 uint32_t trans_start:1; 219 /** tx_lsb_first : R/W; bitpos: [6]; default: 0; 220 * This bit is used to control the sending mode for data needing to be sent. 221 * 1: send data from the least significant bit; 222 * 0: send data from the most significant bit. 223 */ 224 uint32_t tx_lsb_first:1; 225 /** rx_lsb_first : R/W; bitpos: [7]; default: 0; 226 * This bit is used to control the storage mode for received data. 227 * 1: receive data from the least significant bit; 228 * 0: receive data from the most significant bit. 229 */ 230 uint32_t rx_lsb_first:1; 231 /** clk_en : R/W; bitpos: [8]; default: 0; 232 * Reserved 233 */ 234 uint32_t clk_en:1; 235 /** arbitration_en : R/W; bitpos: [9]; default: 1; 236 * This is the enable bit for arbitration_lost. 237 */ 238 uint32_t arbitration_en:1; 239 /** fsm_rst : WT; bitpos: [10]; default: 0; 240 * This register is used to reset the scl FMS. 241 */ 242 uint32_t fsm_rst:1; 243 /** conf_upgate : WT; bitpos: [11]; default: 0; 244 * synchronization bit 245 */ 246 uint32_t conf_upgate:1; 247 /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; 248 * This is the enable bit for slave to send data automatically 249 */ 250 uint32_t slv_tx_auto_start_en:1; 251 /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; 252 * This is the enable bit to check if the r/w bit of 10bit addressing consists with 253 * I2C protocol 254 */ 255 uint32_t addr_10bit_rw_check_en:1; 256 /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; 257 * This is the enable bit to support the 7bit general call function. 258 */ 259 uint32_t addr_broadcasting_en:1; 260 uint32_t reserved_15:17; 261 }; 262 uint32_t val; 263 } i2c_ctr_reg_t; 264 265 /** Type of to register 266 * Setting time out control for receiving data. 267 */ 268 typedef union { 269 struct { 270 /** time_out_value : R/W; bitpos: [4:0]; default: 16; 271 * This register is used to configure the timeout for receiving a data bit in APB 272 * clock cycles. 273 */ 274 uint32_t time_out_value:5; 275 /** time_out_en : R/W; bitpos: [5]; default: 0; 276 * This is the enable bit for time out control. 277 */ 278 uint32_t time_out_en:1; 279 uint32_t reserved_6:26; 280 }; 281 uint32_t val; 282 } i2c_to_reg_t; 283 284 /** Type of slave_addr register 285 * Local slave address setting 286 */ 287 typedef union { 288 struct { 289 /** slave_addr : R/W; bitpos: [14:0]; default: 0; 290 * When configured as an I2C Slave, this field is used to configure the slave address. 291 */ 292 uint32_t slave_addr:15; 293 uint32_t reserved_15:16; 294 /** addr_10bit_en : R/W; bitpos: [31]; default: 0; 295 * This field is used to enable the slave 10-bit addressing mode in master mode. 296 */ 297 uint32_t addr_10bit_en:1; 298 }; 299 uint32_t val; 300 } i2c_slave_addr_reg_t; 301 302 /** Type of fifo_conf register 303 * FIFO configuration register. 304 */ 305 typedef union { 306 struct { 307 /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; 308 * The water mark threshold of rx FIFO in nonfifo access mode. When 309 * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than 310 * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. 311 */ 312 uint32_t rxfifo_wm_thrhd:5; 313 /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; 314 * The water mark threshold of tx FIFO in nonfifo access mode. When 315 * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than 316 * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. 317 */ 318 uint32_t txfifo_wm_thrhd:5; 319 /** nonfifo_en : R/W; bitpos: [10]; default: 0; 320 * Set this bit to enable APB nonfifo access. 321 */ 322 uint32_t nonfifo_en:1; 323 /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; 324 * When this bit is set to 1, the byte received after the I2C address byte represents 325 * the offset address in the I2C Slave RAM. 326 */ 327 uint32_t fifo_addr_cfg_en:1; 328 /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; 329 * Set this bit to reset rx-fifo. 330 */ 331 uint32_t rx_fifo_rst:1; 332 /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; 333 * Set this bit to reset tx-fifo. 334 */ 335 uint32_t tx_fifo_rst:1; 336 /** fifo_prt_en : R/W; bitpos: [14]; default: 1; 337 * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls 338 * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. 339 */ 340 uint32_t fifo_prt_en:1; 341 uint32_t reserved_15:17; 342 }; 343 uint32_t val; 344 } i2c_fifo_conf_reg_t; 345 346 /** Type of filter_cfg register 347 * SCL and SDA filter configuration register 348 */ 349 typedef union { 350 struct { 351 /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; 352 * When a pulse on the SCL input has smaller width than this register value 353 * in I2C module clock cycles, the I2C controller will ignore that pulse. 354 */ 355 uint32_t scl_filter_thres:4; 356 /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; 357 * When a pulse on the SDA input has smaller width than this register value 358 * in I2C module clock cycles, the I2C controller will ignore that pulse. 359 */ 360 uint32_t sda_filter_thres:4; 361 /** scl_filter_en : R/W; bitpos: [8]; default: 1; 362 * This is the filter enable bit for SCL. 363 */ 364 uint32_t scl_filter_en:1; 365 /** sda_filter_en : R/W; bitpos: [9]; default: 1; 366 * This is the filter enable bit for SDA. 367 */ 368 uint32_t sda_filter_en:1; 369 uint32_t reserved_10:22; 370 }; 371 uint32_t val; 372 } i2c_filter_cfg_reg_t; 373 374 /** Type of clk_conf register 375 * I2C CLK configuration register 376 */ 377 typedef union { 378 struct { 379 /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; 380 * the integral part of the fractional divisor for i2c module 381 */ 382 uint32_t sclk_div_num:8; 383 /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; 384 * the numerator of the fractional part of the fractional divisor for i2c module 385 */ 386 uint32_t sclk_div_a:6; 387 /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; 388 * the denominator of the fractional part of the fractional divisor for i2c module 389 */ 390 uint32_t sclk_div_b:6; 391 /** sclk_sel : R/W; bitpos: [20]; default: 0; 392 * The clock selection for i2c module:0-XTAL;1-CLK_8MHz. 393 */ 394 uint32_t sclk_sel:1; 395 /** sclk_active : R/W; bitpos: [21]; default: 1; 396 * The clock switch for i2c module 397 */ 398 uint32_t sclk_active:1; 399 uint32_t reserved_22:10; 400 }; 401 uint32_t val; 402 } i2c_clk_conf_reg_t; 403 404 /** Type of scl_sp_conf register 405 * Power configuration register 406 */ 407 typedef union { 408 struct { 409 /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; 410 * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses 411 * equals to reg_scl_rst_slv_num[4:0]. 412 */ 413 uint32_t scl_rst_slv_en:1; 414 /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; 415 * Configure the pulses of SCL generated in I2C master mode. Valid when 416 * reg_scl_rst_slv_en is 1. 417 */ 418 uint32_t scl_rst_slv_num:5; 419 /** scl_pd_en : R/W; bitpos: [6]; default: 0; 420 * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power 421 * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. 422 */ 423 uint32_t scl_pd_en:1; 424 /** sda_pd_en : R/W; bitpos: [7]; default: 0; 425 * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power 426 * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. 427 */ 428 uint32_t sda_pd_en:1; 429 uint32_t reserved_8:24; 430 }; 431 uint32_t val; 432 } i2c_scl_sp_conf_reg_t; 433 434 /** Type of scl_stretch_conf register 435 * Set SCL stretch of I2C slave 436 */ 437 typedef union { 438 struct { 439 /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; 440 * Configure the period of I2C slave stretching SCL line. 441 */ 442 uint32_t stretch_protect_num:10; 443 /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; 444 * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL 445 * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch 446 * event happens. The stretch cause can be seen in reg_stretch_cause. 447 */ 448 uint32_t slave_scl_stretch_en:1; 449 /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; 450 * Set this bit to clear the I2C slave SCL stretch function. 451 */ 452 uint32_t slave_scl_stretch_clr:1; 453 /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; 454 * The enable bit for slave to control ACK level function. 455 */ 456 uint32_t slave_byte_ack_ctl_en:1; 457 /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; 458 * Set the ACK level when slave controlling ACK level function enables. 459 */ 460 uint32_t slave_byte_ack_lvl:1; 461 uint32_t reserved_14:18; 462 }; 463 uint32_t val; 464 } i2c_scl_stretch_conf_reg_t; 465 466 467 /** Group: Status registers */ 468 /** Type of sr register 469 * Describe I2C work status. 470 */ 471 typedef union { 472 struct { 473 /** resp_rec : RO; bitpos: [0]; default: 0; 474 * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. 475 */ 476 uint32_t resp_rec:1; 477 /** slave_rw : RO; bitpos: [1]; default: 0; 478 * When in slave mode, 1: master reads from slave; 0: master writes to slave. 479 */ 480 uint32_t slave_rw:1; 481 uint32_t reserved_2:1; 482 /** arb_lost : RO; bitpos: [3]; default: 0; 483 * When the I2C controller loses control of SCL line, this register changes to 1. 484 */ 485 uint32_t arb_lost:1; 486 /** bus_busy : RO; bitpos: [4]; default: 0; 487 * 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. 488 */ 489 uint32_t bus_busy:1; 490 /** slave_addressed : RO; bitpos: [5]; default: 0; 491 * When configured as an I2C Slave, and the address sent by the master is 492 * equal to the address of the slave, then this bit will be of high level. 493 */ 494 uint32_t slave_addressed:1; 495 uint32_t reserved_6:2; 496 /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; 497 * This field represents the amount of data needed to be sent. 498 */ 499 uint32_t rxfifo_cnt:6; 500 /** stretch_cause : RO; bitpos: [15:14]; default: 3; 501 * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the 502 * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty 503 * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. 504 */ 505 uint32_t stretch_cause:2; 506 uint32_t reserved_16:2; 507 /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; 508 * This field stores the amount of received data in RAM. 509 */ 510 uint32_t txfifo_cnt:6; 511 /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; 512 * This field indicates the states of the I2C module state machine. 513 * 0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: 514 * Wait ACK 515 */ 516 uint32_t scl_main_state_last:3; 517 uint32_t reserved_27:1; 518 /** scl_state_last : RO; bitpos: [30:28]; default: 0; 519 * This field indicates the states of the state machine used to produce SCL. 520 * 0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop 521 */ 522 uint32_t scl_state_last:3; 523 uint32_t reserved_31:1; 524 }; 525 uint32_t val; 526 } i2c_sr_reg_t; 527 528 /** Type of fifo_st register 529 * FIFO status register. 530 */ 531 typedef union { 532 struct { 533 /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; 534 * This is the offset address of the APB reading from rxfifo 535 */ 536 uint32_t rxfifo_raddr:5; 537 /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; 538 * This is the offset address of i2c module receiving data and writing to rxfifo. 539 */ 540 uint32_t rxfifo_waddr:5; 541 /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; 542 * This is the offset address of i2c module reading from txfifo. 543 */ 544 uint32_t txfifo_raddr:5; 545 /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; 546 * This is the offset address of APB bus writing to txfifo. 547 */ 548 uint32_t txfifo_waddr:5; 549 uint32_t reserved_20:2; 550 /** slave_rw_point : RO; bitpos: [29:22]; default: 0; 551 * The received data in I2C slave mode. 552 */ 553 uint32_t slave_rw_point:8; 554 uint32_t reserved_30:2; 555 }; 556 uint32_t val; 557 } i2c_fifo_st_reg_t; 558 559 /** Type of data register 560 * Rx FIFO read data. 561 */ 562 typedef union { 563 struct { 564 /** fifo_rdata : RO; bitpos: [7:0]; default: 0; 565 * The value of rx FIFO read data. 566 */ 567 uint32_t fifo_rdata:8; 568 uint32_t reserved_8:24; 569 }; 570 uint32_t val; 571 } i2c_data_reg_t; 572 573 574 /** Group: Interrupt registers */ 575 /** Type of int_raw register 576 * Raw interrupt status 577 */ 578 typedef union { 579 struct { 580 /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; 581 * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. 582 */ 583 uint32_t rxfifo_wm_int_raw:1; 584 /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; 585 * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. 586 */ 587 uint32_t txfifo_wm_int_raw:1; 588 /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; 589 * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. 590 */ 591 uint32_t rxfifo_ovf_int_raw:1; 592 /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; 593 * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 594 */ 595 uint32_t end_detect_int_raw:1; 596 /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; 597 * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 598 */ 599 uint32_t byte_trans_done_int_raw:1; 600 /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; 601 * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. 602 */ 603 uint32_t arbitration_lost_int_raw:1; 604 /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; 605 * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. 606 */ 607 uint32_t mst_txfifo_udf_int_raw:1; 608 /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; 609 * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. 610 */ 611 uint32_t trans_complete_int_raw:1; 612 /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; 613 * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. 614 */ 615 uint32_t time_out_int_raw:1; 616 /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; 617 * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. 618 */ 619 uint32_t trans_start_int_raw:1; 620 /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; 621 * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 622 */ 623 uint32_t nack_int_raw:1; 624 /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; 625 * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. 626 */ 627 uint32_t txfifo_ovf_int_raw:1; 628 /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; 629 * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. 630 */ 631 uint32_t rxfifo_udf_int_raw:1; 632 /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; 633 * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. 634 */ 635 uint32_t scl_st_to_int_raw:1; 636 /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; 637 * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 638 */ 639 uint32_t scl_main_st_to_int_raw:1; 640 /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; 641 * The raw interrupt bit for I2C_DET_START_INT interrupt. 642 */ 643 uint32_t det_start_int_raw:1; 644 /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; 645 * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 646 */ 647 uint32_t slave_stretch_int_raw:1; 648 /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; 649 * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. 650 */ 651 uint32_t general_call_int_raw:1; 652 uint32_t reserved_18:14; 653 }; 654 uint32_t val; 655 } i2c_int_raw_reg_t; 656 657 /** Type of int_clr register 658 * Interrupt clear bits 659 */ 660 typedef union { 661 struct { 662 /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; 663 * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. 664 */ 665 uint32_t rxfifo_wm_int_clr:1; 666 /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; 667 * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. 668 */ 669 uint32_t txfifo_wm_int_clr:1; 670 /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; 671 * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. 672 */ 673 uint32_t rxfifo_ovf_int_clr:1; 674 /** end_detect_int_clr : WT; bitpos: [3]; default: 0; 675 * Set this bit to clear the I2C_END_DETECT_INT interrupt. 676 */ 677 uint32_t end_detect_int_clr:1; 678 /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; 679 * Set this bit to clear the I2C_END_DETECT_INT interrupt. 680 */ 681 uint32_t byte_trans_done_int_clr:1; 682 /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; 683 * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. 684 */ 685 uint32_t arbitration_lost_int_clr:1; 686 /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; 687 * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. 688 */ 689 uint32_t mst_txfifo_udf_int_clr:1; 690 /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; 691 * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. 692 */ 693 uint32_t trans_complete_int_clr:1; 694 /** time_out_int_clr : WT; bitpos: [8]; default: 0; 695 * Set this bit to clear the I2C_TIME_OUT_INT interrupt. 696 */ 697 uint32_t time_out_int_clr:1; 698 /** trans_start_int_clr : WT; bitpos: [9]; default: 0; 699 * Set this bit to clear the I2C_TRANS_START_INT interrupt. 700 */ 701 uint32_t trans_start_int_clr:1; 702 /** nack_int_clr : WT; bitpos: [10]; default: 0; 703 * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 704 */ 705 uint32_t nack_int_clr:1; 706 /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; 707 * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. 708 */ 709 uint32_t txfifo_ovf_int_clr:1; 710 /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; 711 * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. 712 */ 713 uint32_t rxfifo_udf_int_clr:1; 714 /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; 715 * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. 716 */ 717 uint32_t scl_st_to_int_clr:1; 718 /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; 719 * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. 720 */ 721 uint32_t scl_main_st_to_int_clr:1; 722 /** det_start_int_clr : WT; bitpos: [15]; default: 0; 723 * Set this bit to clear I2C_DET_START_INT interrupt. 724 */ 725 uint32_t det_start_int_clr:1; 726 /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; 727 * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 728 */ 729 uint32_t slave_stretch_int_clr:1; 730 /** general_call_int_clr : WT; bitpos: [17]; default: 0; 731 * Set this bit for I2C_GENARAL_CALL_INT interrupt. 732 */ 733 uint32_t general_call_int_clr:1; 734 uint32_t reserved_18:14; 735 }; 736 uint32_t val; 737 } i2c_int_clr_reg_t; 738 739 /** Type of int_ena register 740 * Interrupt enable bits 741 */ 742 typedef union { 743 struct { 744 /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; 745 * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. 746 */ 747 uint32_t rxfifo_wm_int_ena:1; 748 /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; 749 * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. 750 */ 751 uint32_t txfifo_wm_int_ena:1; 752 /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; 753 * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. 754 */ 755 uint32_t rxfifo_ovf_int_ena:1; 756 /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; 757 * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 758 */ 759 uint32_t end_detect_int_ena:1; 760 /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; 761 * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 762 */ 763 uint32_t byte_trans_done_int_ena:1; 764 /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; 765 * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. 766 */ 767 uint32_t arbitration_lost_int_ena:1; 768 /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; 769 * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. 770 */ 771 uint32_t mst_txfifo_udf_int_ena:1; 772 /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; 773 * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. 774 */ 775 uint32_t trans_complete_int_ena:1; 776 /** time_out_int_ena : R/W; bitpos: [8]; default: 0; 777 * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. 778 */ 779 uint32_t time_out_int_ena:1; 780 /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; 781 * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. 782 */ 783 uint32_t trans_start_int_ena:1; 784 /** nack_int_ena : R/W; bitpos: [10]; default: 0; 785 * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. 786 */ 787 uint32_t nack_int_ena:1; 788 /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; 789 * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. 790 */ 791 uint32_t txfifo_ovf_int_ena:1; 792 /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; 793 * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. 794 */ 795 uint32_t rxfifo_udf_int_ena:1; 796 /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; 797 * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. 798 */ 799 uint32_t scl_st_to_int_ena:1; 800 /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; 801 * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 802 */ 803 uint32_t scl_main_st_to_int_ena:1; 804 /** det_start_int_ena : R/W; bitpos: [15]; default: 0; 805 * The interrupt enable bit for I2C_DET_START_INT interrupt. 806 */ 807 uint32_t det_start_int_ena:1; 808 /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; 809 * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. 810 */ 811 uint32_t slave_stretch_int_ena:1; 812 /** general_call_int_ena : R/W; bitpos: [17]; default: 0; 813 * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. 814 */ 815 uint32_t general_call_int_ena:1; 816 uint32_t reserved_18:14; 817 }; 818 uint32_t val; 819 } i2c_int_ena_reg_t; 820 821 /** Type of int_status register 822 * Status of captured I2C communication events 823 */ 824 typedef union { 825 struct { 826 /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; 827 * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. 828 */ 829 uint32_t rxfifo_wm_int_st:1; 830 /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; 831 * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. 832 */ 833 uint32_t txfifo_wm_int_st:1; 834 /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; 835 * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. 836 */ 837 uint32_t rxfifo_ovf_int_st:1; 838 /** end_detect_int_st : RO; bitpos: [3]; default: 0; 839 * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 840 */ 841 uint32_t end_detect_int_st:1; 842 /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; 843 * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 844 */ 845 uint32_t byte_trans_done_int_st:1; 846 /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; 847 * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. 848 */ 849 uint32_t arbitration_lost_int_st:1; 850 /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; 851 * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. 852 */ 853 uint32_t mst_txfifo_udf_int_st:1; 854 /** trans_complete_int_st : RO; bitpos: [7]; default: 0; 855 * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. 856 */ 857 uint32_t trans_complete_int_st:1; 858 /** time_out_int_st : RO; bitpos: [8]; default: 0; 859 * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. 860 */ 861 uint32_t time_out_int_st:1; 862 /** trans_start_int_st : RO; bitpos: [9]; default: 0; 863 * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. 864 */ 865 uint32_t trans_start_int_st:1; 866 /** nack_int_st : RO; bitpos: [10]; default: 0; 867 * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 868 */ 869 uint32_t nack_int_st:1; 870 /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; 871 * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. 872 */ 873 uint32_t txfifo_ovf_int_st:1; 874 /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; 875 * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. 876 */ 877 uint32_t rxfifo_udf_int_st:1; 878 /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; 879 * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. 880 */ 881 uint32_t scl_st_to_int_st:1; 882 /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; 883 * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 884 */ 885 uint32_t scl_main_st_to_int_st:1; 886 /** det_start_int_st : RO; bitpos: [15]; default: 0; 887 * The masked interrupt status bit for I2C_DET_START_INT interrupt. 888 */ 889 uint32_t det_start_int_st:1; 890 /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; 891 * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 892 */ 893 uint32_t slave_stretch_int_st:1; 894 /** general_call_int_st : RO; bitpos: [17]; default: 0; 895 * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. 896 */ 897 uint32_t general_call_int_st:1; 898 uint32_t reserved_18:14; 899 }; 900 uint32_t val; 901 } i2c_int_status_reg_t; 902 903 904 /** Group: Command registers */ 905 /** Type of command register 906 * I2C command register 907 */ 908 typedef union { 909 struct { 910 /** command0 : R/W; bitpos: [13:0]; default: 0; 911 * This is the content of command 0. It consists of three parts: 912 * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. 913 * Byte_num represents the number of bytes that need to be sent or received. 914 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 915 * structure for more 916 * Information. 917 */ 918 uint32_t command:14; 919 uint32_t reserved_14:17; 920 /** command0_done : R/W/SS; bitpos: [31]; default: 0; 921 * When command 0 is done in I2C Master mode, this bit changes to high 922 * level. 923 */ 924 uint32_t command_done:1; 925 }; 926 uint32_t val; 927 } i2c_comd_reg_t; 928 929 930 /** Group: Version register */ 931 /** Type of date register 932 * Version register 933 */ 934 typedef union { 935 struct { 936 /** date : R/W; bitpos: [31:0]; default: 537330177; 937 * This is the the version register. 938 */ 939 uint32_t date:32; 940 }; 941 uint32_t val; 942 } i2c_date_reg_t; 943 944 945 /** Group: Address register */ 946 /** Type of txfifo_start_addr register 947 * I2C TXFIFO base address register 948 */ 949 typedef union { 950 struct { 951 /** txfifo_start_addr : RO; bitpos: [31:0]; default: 0; 952 * This is the I2C txfifo first address. 953 */ 954 uint32_t txfifo_start_addr:32; 955 }; 956 uint32_t val; 957 } i2c_txfifo_start_addr_reg_t; 958 959 /** Type of rxfifo_start_addr register 960 * I2C RXFIFO base address register 961 */ 962 typedef union { 963 struct { 964 /** rxfifo_start_addr : RO; bitpos: [31:0]; default: 0; 965 * This is the I2C rxfifo first address. 966 */ 967 uint32_t rxfifo_start_addr:32; 968 }; 969 uint32_t val; 970 } i2c_rxfifo_start_addr_reg_t; 971 972 973 typedef struct { 974 volatile i2c_scl_low_period_reg_t scl_low_period; 975 volatile i2c_ctr_reg_t ctr; 976 volatile i2c_sr_reg_t sr; 977 volatile i2c_to_reg_t to; 978 volatile i2c_slave_addr_reg_t slave_addr; 979 volatile i2c_fifo_st_reg_t fifo_st; 980 volatile i2c_fifo_conf_reg_t fifo_conf; 981 volatile i2c_data_reg_t data; 982 volatile i2c_int_raw_reg_t int_raw; 983 volatile i2c_int_clr_reg_t int_clr; 984 volatile i2c_int_ena_reg_t int_ena; 985 volatile i2c_int_status_reg_t int_status; 986 volatile i2c_sda_hold_reg_t sda_hold; 987 volatile i2c_sda_sample_reg_t sda_sample; 988 volatile i2c_scl_high_period_reg_t scl_high_period; 989 uint32_t reserved_03c; 990 volatile i2c_scl_start_hold_reg_t scl_start_hold; 991 volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; 992 volatile i2c_scl_stop_hold_reg_t scl_stop_hold; 993 volatile i2c_scl_stop_setup_reg_t scl_stop_setup; 994 volatile i2c_filter_cfg_reg_t filter_cfg; 995 volatile i2c_clk_conf_reg_t clk_conf; 996 volatile i2c_comd_reg_t comd[8]; 997 volatile i2c_scl_st_time_out_reg_t scl_st_time_out; 998 volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; 999 volatile i2c_scl_sp_conf_reg_t scl_sp_conf; 1000 volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; 1001 uint32_t reserved_088[28]; 1002 volatile i2c_date_reg_t date; 1003 uint32_t reserved_0fc; 1004 volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; 1005 uint32_t reserved_104[31]; 1006 volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; 1007 } i2c_dev_t; 1008 1009 extern i2c_dev_t I2C0; 1010 extern i2c_dev_t I2C1; 1011 1012 #ifndef __cplusplus 1013 _Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); 1014 #endif 1015 1016 #ifdef __cplusplus 1017 } 1018 #endif 1019
