1/* 2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/clock/kinetis_pcc.h> 10#include <zephyr/dt-bindings/clock/kinetis_scg.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13 14/ { 15 aliases { 16 watchdog0 = &wdog; 17 }; 18 19 chosen { 20 zephyr,flash-controller = &ftfe; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-m4f"; 30 reg = <0>; 31 cpu-power-states = <&idle &stop &pstop1 &pstop2>; 32 }; 33 34 power-states { 35 idle: idle { 36 compatible = "zephyr,power-state"; 37 power-state-name = "runtime-idle"; 38 }; 39 40 stop: stop { 41 compatible = "zephyr,power-state"; 42 power-state-name = "suspend-to-idle"; 43 substate-id = <0>; 44 }; 45 46 pstop1: pstop1 { 47 compatible = "zephyr,power-state"; 48 power-state-name = "suspend-to-idle"; 49 substate-id = <1>; 50 }; 51 52 pstop2: pstop2 { 53 compatible = "zephyr,power-state"; 54 power-state-name = "suspend-to-idle"; 55 substate-id = <2>; 56 }; 57 }; 58 }; 59 60 temp0: temp0 { 61 compatible = "nxp,kinetis-temperature"; 62 io-channels = <&adc0 26>, <&adc0 27>; 63 io-channel-names = "SENSOR", "BANDGAP"; 64 bandgap-voltage = <1000000>; 65 vtemp25 = <740500>; 66 sensor-slope-cold = <1564>; 67 sensor-slope-hot = <1564>; 68 status = "disabled"; 69 }; 70 71 temp1: temp1 { 72 compatible = "nxp,kinetis-temperature"; 73 io-channels = <&adc1 26>, <&adc1 27>; 74 io-channel-names = "SENSOR", "BANDGAP"; 75 bandgap-voltage = <1000000>; 76 vtemp25 = <740500>; 77 sensor-slope-cold = <1564>; 78 sensor-slope-hot = <1564>; 79 status = "disabled"; 80 }; 81 82 temp2: temp2 { 83 compatible = "nxp,kinetis-temperature"; 84 io-channels = <&adc2 26>, <&adc2 27>; 85 io-channel-names = "SENSOR", "BANDGAP"; 86 bandgap-voltage = <1000000>; 87 vtemp25 = <740500>; 88 sensor-slope-cold = <1564>; 89 sensor-slope-hot = <1564>; 90 status = "disabled"; 91 }; 92 93 /* Dummy pinctrl node, filled with pin mux options at board level */ 94 pinctrl: pinctrl { 95 compatible = "nxp,kinetis-pinctrl"; 96 status = "okay"; 97 }; 98 99 soc { 100 edma: dma-controller@40008000 { 101 compatible = "nxp,mcux-edma"; 102 dma-channels = <16>; 103 dma-requests = <64>; 104 nxp,mem2mem; 105 reg = <0x40008000 0x1000>, <0x40021000 0x1000>; 106 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 107 <4 0>, <5 0>, <6 0>, <7 0>, 108 <8 0>, <9 0>, <10 0>, <11 0>, 109 <12 0>, <13 0>, <14 0>, <15 0>, 110 <16 0>; 111 status = "disabled"; 112 #dma-cells = <2>; 113 }; 114 115 mpu: mpu@4000d000 { 116 compatible = "nxp,kinetis-mpu"; 117 reg = <0x4000d000 0x1000>; 118 status = "disabled"; 119 }; 120 121 sim: sim@40048000 { 122 compatible = "nxp,kinetis-ke1xf-sim"; 123 reg = <0x40048000 0x1000>; 124 }; 125 126 scg: scg@40064000 { 127 compatible = "nxp,kinetis-scg"; 128 reg = <0x40064000 0x1000>; 129 #clock-cells = <1>; 130 131 sosc_clk: sosc_clk { 132 compatible = "fixed-clock"; 133 status = "disabled"; 134 #clock-cells = <0>; 135 }; 136 137 sirc_clk: sirc_clk { 138 compatible = "fixed-clock"; 139 clock-frequency = <8000000>; 140 #clock-cells = <0>; 141 }; 142 143 firc_clk: firc_clk { 144 compatible = "fixed-clock"; 145 clock-frequency = <48000000>; 146 #clock-cells = <0>; 147 }; 148 149 pll: pll { 150 compatible = "fixed-factor-clock"; 151 clocks = <&sosc_clk>; 152 clock-div = <1>; 153 clock-mult = <16>; 154 #clock-cells = <0>; 155 }; 156 157 spll_clk: spll_clk { 158 compatible = "fixed-factor-clock"; 159 clocks = <&pll>; 160 clock-div = <2>; 161 #clock-cells = <0>; 162 }; 163 164 core_clk: core_clk { 165 compatible = "fixed-factor-clock"; 166 clocks = <&firc_clk>; 167 clock-div = <1>; 168 #clock-cells = <0>; 169 }; 170 171 bus_clk: bus_clk { 172 compatible = "fixed-factor-clock"; 173 clocks = <&core_clk>; 174 clock-div = <1>; 175 #clock-cells = <0>; 176 }; 177 178 slow_clk: slow_clk { 179 compatible = "fixed-factor-clock"; 180 clocks = <&core_clk>; 181 clock-div = <2>; 182 #clock-cells = <0>; 183 }; 184 185 clkout_clk: clkout_clk { 186 compatible = "fixed-factor-clock"; 187 status = "disabled"; 188 clocks = <&firc_clk>; 189 #clock-cells = <0>; 190 }; 191 192 splldiv1_clk: splldiv1_clk { 193 compatible = "fixed-factor-clock"; 194 clocks = <&spll_clk>; 195 clock-div = <0>; 196 #clock-cells = <0>; 197 }; 198 199 splldiv2_clk: splldiv2_clk { 200 compatible = "fixed-factor-clock"; 201 clocks = <&spll_clk>; 202 clock-div = <0>; 203 #clock-cells = <0>; 204 }; 205 206 sircdiv1_clk: sircdiv1_clk { 207 compatible = "fixed-factor-clock"; 208 clocks = <&sirc_clk>; 209 clock-div = <0>; 210 #clock-cells = <0>; 211 }; 212 213 sircdiv2_clk: sircdiv2_clk { 214 compatible = "fixed-factor-clock"; 215 clocks = <&sirc_clk>; 216 clock-div = <0>; 217 #clock-cells = <0>; 218 }; 219 220 fircdiv1_clk: fircdiv1_clk { 221 compatible = "fixed-factor-clock"; 222 clocks = <&firc_clk>; 223 clock-div = <0>; 224 #clock-cells = <0>; 225 }; 226 227 fircdiv2_clk: fircdiv2_clk { 228 compatible = "fixed-factor-clock"; 229 clocks = <&firc_clk>; 230 clock-div = <0>; 231 #clock-cells = <0>; 232 }; 233 234 soscdiv1_clk: soscdiv1_clk { 235 compatible = "fixed-factor-clock"; 236 clocks = <&sosc_clk>; 237 clock-div = <0>; 238 #clock-cells = <0>; 239 }; 240 241 soscdiv2_clk: soscdiv2_clk { 242 compatible = "fixed-factor-clock"; 243 clocks = <&sosc_clk>; 244 clock-div = <0>; 245 #clock-cells = <0>; 246 }; 247 }; 248 249 pmc: pmc@4007d000 { 250 reg = <0x4007d000 0x1000>; 251 252 lpo: lpo128k { 253 /* LPO clock */ 254 compatible = "fixed-clock"; 255 clock-frequency = <128000>; 256 #clock-cells = <0>; 257 }; 258 }; 259 260 pcc: pcc@40065000 { 261 compatible = "nxp,kinetis-pcc"; 262 reg = <0x40065000 0x1000>; 263 #clock-cells = <2>; 264 }; 265 266 rtc: rtc@4003d000 { 267 compatible = "nxp,kinetis-rtc"; 268 reg = <0x4003d000 0x1000>; 269 interrupts = <46 0>, <47 0>; 270 interrupt-names = "alarm", "seconds"; 271 clock-frequency = <32768>; 272 prescaler = <32768>; 273 }; 274 275 dac0: dac@4003f000 { 276 compatible = "nxp,kinetis-dac32"; 277 reg = <0x4003f000 0x1000>; 278 interrupts = <56 0>; 279 clocks = <&scg KINETIS_SCG_BUS_CLK>; 280 voltage-reference = <1>; 281 buffered; 282 status = "disabled"; 283 #io-channel-cells = <1>; 284 }; 285 286 lptmr0: lptmr@40040000 { 287 compatible = "nxp,lptmr"; 288 reg = <0x40040000 0x1000>; 289 interrupts = <58 0>; 290 clock-frequency = <128000>; 291 prescaler = <1>; 292 clk-source = <1>; 293 resolution = <16>; 294 }; 295 296 wdog: watchdog@40052000 { 297 compatible = "nxp,kinetis-wdog32"; 298 reg = <0x40052000 0x1000>; 299 interrupts = <22 0>; 300 clocks = <&lpo>; 301 clk-source = <1>; 302 clk-divider = <256>; 303 }; 304 305 pwt: pwt@40056000 { 306 compatible = "nxp,kinetis-pwt"; 307 reg = <0x40056000 0x1000>; 308 interrupts = <29 0>; 309 clocks = <&scg KINETIS_SCG_BUS_CLK>; 310 prescaler = <1>; 311 status = "disabled"; 312 313 #pwm-cells = <3>; 314 }; 315 316 ftfe: flash-controller@40020000 { 317 compatible = "nxp,kinetis-ftfe"; 318 reg = <0x40020000 0x1000>; 319 interrupts = <18 0>, <19 0>; 320 interrupt-names = "command-complete", "read-collision"; 321 322 #address-cells = <1>; 323 #size-cells = <1>; 324 }; 325 326 lpuart0: uart@4006a000 { 327 compatible = "nxp,kinetis-lpuart"; 328 reg = <0x4006a000 0x1000>; 329 interrupts = <31 0>, <32 0>; 330 interrupt-names = "transmit", "receive"; 331 clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>; 332 dmas = <&edma 1 2>, <&edma 2 3>; 333 dma-names = "rx", "tx"; 334 status = "disabled"; 335 }; 336 337 lpuart1: uart@4006b000 { 338 compatible = "nxp,kinetis-lpuart"; 339 reg = <0x4006b000 0x1000>; 340 interrupts = <33 0>, <34 0>; 341 interrupt-names = "transmit", "receive"; 342 clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>; 343 dmas = <&edma 3 4>, <&edma 4 5>; 344 dma-names = "rx", "tx"; 345 status = "disabled"; 346 }; 347 348 lpuart2: uart@4006c000 { 349 compatible = "nxp,kinetis-lpuart"; 350 reg = <0x4006c000 0x1000>; 351 interrupts = <35 0>, <36 0>; 352 interrupt-names = "transmit", "receive"; 353 clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>; 354 dmas = <&edma 5 6>, <&edma 5 7>; 355 dma-names = "rx", "tx"; 356 status = "disabled"; 357 }; 358 359 lpi2c0: i2c@40066000 { 360 compatible = "nxp,imx-lpi2c"; 361 clock-frequency = <I2C_BITRATE_STANDARD>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 reg = <0x40066000 0x1000>; 365 interrupts = <24 0>; 366 clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>; 367 status = "disabled"; 368 }; 369 370 lpi2c1: i2c@40067000 { 371 compatible = "nxp,imx-lpi2c"; 372 clock-frequency = <I2C_BITRATE_STANDARD>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 reg = <0x40067000 0x1000>; 376 interrupts = <25 0>; 377 clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>; 378 status = "disabled"; 379 }; 380 381 lpspi0: spi@4002c000 { 382 compatible = "nxp,imx-lpspi"; 383 reg = <0x4002c000 0x1000>; 384 interrupts = <26 0>; 385 clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>; 386 status = "disabled"; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 }; 390 391 lpspi1: spi@4002d000 { 392 compatible = "nxp,imx-lpspi"; 393 reg = <0x4002d000 0x1000>; 394 interrupts = <27 0>; 395 clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>; 396 status = "disabled"; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 }; 400 401 flexcan0: can@40024000 { 402 compatible = "nxp,flexcan"; 403 reg = <0x40024000 0x1000>; 404 interrupts = <78 0>, <79 0>, <80 0>, <81 0>; 405 interrupt-names = "warning", "error", "wake-up", 406 "mb-0-15"; 407 clocks = <&scg KINETIS_SCG_BUS_CLK>; 408 clk-source = <1>; 409 status = "disabled"; 410 }; 411 412 flexcan1: can@40025000 { 413 compatible = "nxp,flexcan"; 414 reg = <0x40025000 0x1000>; 415 interrupts = <85 0>, <86 0>, <87 0>, <88 0>; 416 interrupt-names = "warning", "error", "wake-up", 417 "mb-0-15"; 418 clocks = <&scg KINETIS_SCG_BUS_CLK>; 419 clk-source = <1>; 420 status = "disabled"; 421 }; 422 423 porta: pinmux@40049000 { 424 compatible = "nxp,kinetis-pinmux"; 425 reg = <0x40049000 0x1000>; 426 clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>; 427 }; 428 429 portb: pinmux@4004a000 { 430 compatible = "nxp,kinetis-pinmux"; 431 reg = <0x4004a000 0x1000>; 432 clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>; 433 }; 434 435 portc: pinmux@4004b000 { 436 compatible = "nxp,kinetis-pinmux"; 437 reg = <0x4004b000 0x1000>; 438 clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>; 439 }; 440 441 portd: pinmux@4004c000 { 442 compatible = "nxp,kinetis-pinmux"; 443 reg = <0x4004c000 0x1000>; 444 clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>; 445 }; 446 447 porte: pinmux@4004d000 { 448 compatible = "nxp,kinetis-pinmux"; 449 reg = <0x4004d000 0x1000>; 450 clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>; 451 }; 452 453 gpioa: gpio@400ff000 { 454 compatible = "nxp,kinetis-gpio"; 455 status = "disabled"; 456 reg = <0x400ff000 0x40>; 457 interrupts = <59 2>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 nxp,kinetis-port = <&porta>; 461 }; 462 463 gpiob: gpio@400ff040 { 464 compatible = "nxp,kinetis-gpio"; 465 status = "disabled"; 466 reg = <0x400ff040 0x40>; 467 interrupts = <60 2>; 468 gpio-controller; 469 #gpio-cells = <2>; 470 nxp,kinetis-port = <&portb>; 471 }; 472 473 gpioc: gpio@400ff080 { 474 compatible = "nxp,kinetis-gpio"; 475 status = "disabled"; 476 reg = <0x400ff080 0x40>; 477 interrupts = <61 2>; 478 gpio-controller; 479 #gpio-cells = <2>; 480 nxp,kinetis-port = <&portc>; 481 }; 482 483 gpiod: gpio@400ff0c0 { 484 compatible = "nxp,kinetis-gpio"; 485 status = "disabled"; 486 reg = <0x400ff0c0 0x40>; 487 interrupts = <62 2>; 488 gpio-controller; 489 #gpio-cells = <2>; 490 nxp,kinetis-port = <&portd>; 491 }; 492 493 gpioe: gpio@400ff100 { 494 compatible = "nxp,kinetis-gpio"; 495 status = "disabled"; 496 reg = <0x400ff100 0x40>; 497 interrupts = <63 2>; 498 gpio-controller; 499 #gpio-cells = <2>; 500 nxp,kinetis-port = <&porte>; 501 }; 502 503 adc0: adc@4003b000 { 504 compatible = "nxp,kinetis-adc12"; 505 reg = <0x4003b000 0x1000>; 506 interrupts = <39 0>; 507 clocks = <&pcc 0xec KINETIS_PCC_SRC_FIRC_ASYNC>; 508 clk-source = <0>; 509 clk-divider = <1>; 510 status = "disabled"; 511 #io-channel-cells = <1>; 512 }; 513 514 adc1: adc@40027000 { 515 compatible = "nxp,kinetis-adc12"; 516 reg = <0x40027000 0x1000>; 517 interrupts = <73 0>; 518 clocks = <&pcc 0x9c KINETIS_PCC_SRC_FIRC_ASYNC>; 519 clk-source = <0>; 520 clk-divider = <1>; 521 status = "disabled"; 522 #io-channel-cells = <1>; 523 }; 524 525 adc2: adc@4003c000 { 526 compatible = "nxp,kinetis-adc12"; 527 reg = <0x4003c000 0x1000>; 528 interrupts = <74 0>; 529 clocks = <&pcc 0xf0 KINETIS_PCC_SRC_FIRC_ASYNC>; 530 clk-source = <0>; 531 clk-divider = <1>; 532 status = "disabled"; 533 #io-channel-cells = <1>; 534 }; 535 536 ftm0: ftm@40038000 { 537 compatible = "nxp,kinetis-ftm"; 538 reg = <0x40038000 0x1000>; 539 interrupts = <42 0>; 540 clocks = <&pcc 0xe0 KINETIS_PCC_SRC_FIRC_ASYNC>; 541 prescaler = <16>; 542 status = "disabled"; 543 }; 544 545 ftm1: ftm@40039000 { 546 compatible = "nxp,kinetis-ftm"; 547 reg = <0x40039000 0x1000>; 548 interrupts = <43 0>; 549 clocks = <&pcc 0xe4 KINETIS_PCC_SRC_FIRC_ASYNC>; 550 prescaler = <16>; 551 status = "disabled"; 552 }; 553 554 ftm2: ftm@4003a000 { 555 compatible = "nxp,kinetis-ftm"; 556 reg = <0x4003a000 0x1000>; 557 interrupts = <44 0>; 558 clocks = <&pcc 0xe8 KINETIS_PCC_SRC_FIRC_ASYNC>; 559 prescaler = <16>; 560 status = "disabled"; 561 }; 562 563 ftm3: ftm@40026000 { 564 compatible = "nxp,kinetis-ftm"; 565 reg = <0x40026000 0x1000>; 566 interrupts = <71 0>; 567 clocks = <&pcc 0x98 KINETIS_PCC_SRC_FIRC_ASYNC>; 568 prescaler = <16>; 569 status = "disabled"; 570 }; 571 572 cmp0: cmp@40073000 { 573 compatible = "nxp,kinetis-acmp"; 574 reg = <0x40073000 0x1000>; 575 interrupts = <40 0>; 576 clocks = <&scg KINETIS_SCG_BUS_CLK>; 577 status = "disabled"; 578 #io-channel-cells = <2>; 579 }; 580 581 cmp1: cmp@40074000 { 582 compatible = "nxp,kinetis-acmp"; 583 reg = <0x40074000 0x1000>; 584 interrupts = <41 0>; 585 clocks = <&scg KINETIS_SCG_BUS_CLK>; 586 status = "disabled"; 587 #io-channel-cells = <2>; 588 }; 589 590 cmp2: cmp@40075000 { 591 compatible = "nxp,kinetis-acmp"; 592 reg = <0x40075000 0x1000>; 593 interrupts = <70 0>; 594 clocks = <&scg KINETIS_SCG_BUS_CLK>; 595 status = "disabled"; 596 #io-channel-cells = <2>; 597 }; 598 599 flexio1: flexio@4005a000 { 600 compatible = "nxp,flexio"; 601 reg = <0x4005a000 0x1000>; 602 status = "disabled"; 603 interrupts = <69 0>; 604 clocks = <&pcc 0x168 KINETIS_PCC_SRC_FIRC_ASYNC>; 605 }; 606 }; 607}; 608 609&nvic { 610 arm,num-irq-priority-bits = <4>; 611}; 612
