1 /*
2 * Copyright (c) 2022 Google LLC
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_shi
8
9 #include "ec_host_cmd_backend_shi.h"
10
11 #include <chip_chipregs.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
15 #include <zephyr/logging/log.h>
16 #include <zephyr/mgmt/ec_host_cmd/backend.h>
17 #include <zephyr/mgmt/ec_host_cmd/ec_host_cmd.h>
18 #include <zephyr/pm/device.h>
19 #include <zephyr/pm/device_runtime.h>
20 #include <zephyr/pm/policy.h>
21
22 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "Invalid number of ITE SHI peripherals");
23
24 LOG_MODULE_REGISTER(host_cmd_shi_ite, CONFIG_EC_HC_LOG_LEVEL);
25
26 #define EC_SHI_PREAMBLE_LENGTH 4
27 #define EC_SHI_PAST_END_LENGTH 4
28 #define SPI_RX_MAX_FIFO_SIZE DT_INST_PROP(0, buffer_rx_size)
29 #define SPI_TX_MAX_FIFO_SIZE DT_INST_PROP(0, buffer_tx_size)
30
31 #define SHI_MAX_RESPONSE_SIZE \
32 (SPI_TX_MAX_FIFO_SIZE - EC_SHI_PREAMBLE_LENGTH - EC_SHI_PAST_END_LENGTH)
33
34 BUILD_ASSERT(CONFIG_EC_HOST_CMD_BACKEND_SHI_MAX_REQUEST <= SPI_RX_MAX_FIFO_SIZE,
35 "SHI max request size is too big");
36 BUILD_ASSERT(CONFIG_EC_HOST_CMD_BACKEND_SHI_MAX_RESPONSE <= SHI_MAX_RESPONSE_SIZE,
37 "SHI max response size is too big");
38
39 /* Parameters used by host protocols */
40 enum shi_state_machine {
41 /* Interface is disabled */
42 SHI_STATE_DISABLED,
43 /* Ready to receive next request */
44 SHI_STATE_READY_TO_RECV,
45 /* Receiving request */
46 SHI_STATE_RECEIVING,
47 /* Processing request */
48 SHI_STATE_PROCESSING,
49 /* Received bad data */
50 SHI_STATE_RX_BAD,
51
52 SHI_STATE_COUNT,
53 };
54
55 /*
56 * Structure shi_it8xxx2_cfg is about the setting of SHI,
57 * this config will be used at initial time
58 */
59 struct shi_it8xxx2_cfg {
60 /* SHI alternate configuration */
61 const struct pinctrl_dev_config *pcfg;
62 /* Chip select pin */
63 const struct gpio_dt_spec cs;
64 };
65
66 enum shi_ite_pm_policy_state_flag {
67 SHI_ITE_PM_POLICY_FLAG,
68 SHI_ITE_PM_POLICY_FLAG_COUNT,
69 };
70
71 struct shi_it8xxx2_data {
72 /* Peripheral data */
73 struct ec_host_cmd_rx_ctx *rx_ctx;
74 struct ec_host_cmd_tx_buf *tx;
75 struct gpio_callback cs_cb;
76 struct k_work_delayable cs_off_put;
77 /* Current state */
78 enum shi_state_machine shi_state;
79 /* Buffers */
80 uint8_t in_msg[SPI_RX_MAX_FIFO_SIZE] __aligned(4);
81 uint8_t out_msg[SPI_TX_MAX_FIFO_SIZE] __aligned(4);
82 ATOMIC_DEFINE(pm_policy_state_flag, SHI_ITE_PM_POLICY_FLAG_COUNT);
83 };
84
85 struct ec_host_cmd_shi_ite_ctx {
86 /* SHI device instance */
87 const struct device *dev;
88 };
89
shi_ite_pm_policy_state_lock_get(struct shi_it8xxx2_data * data,enum shi_ite_pm_policy_state_flag flag)90 static void shi_ite_pm_policy_state_lock_get(struct shi_it8xxx2_data *data,
91 enum shi_ite_pm_policy_state_flag flag)
92 {
93 if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) {
94 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
95 k_work_reschedule(&data->cs_off_put, K_SECONDS(3));
96 }
97 }
98
shi_ite_pm_policy_state_lock_put(struct shi_it8xxx2_data * data,enum shi_ite_pm_policy_state_flag flag)99 static void shi_ite_pm_policy_state_lock_put(struct shi_it8xxx2_data *data,
100 enum shi_ite_pm_policy_state_flag flag)
101 {
102 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) {
103 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
104 k_work_cancel_delayable(&data->cs_off_put);
105 }
106 }
107
108 /*
109 * When AP is In S0 state, AP assert CS of SPI for a new command transaction.
110 * Under the condition, SoC will not enter deep sleep until AP de-assert the CS.
111 * But If AP is powered off (G3 state) CS will go low (assert CS).
112 * This assertion will prevent SoC from entering deep sleep but the assertion
113 * is not for starting a new command transaction.
114 * This handler is used to resolve the situation.
115 */
cs_off_put_handler(struct k_work * item)116 static void cs_off_put_handler(struct k_work *item)
117 {
118 struct k_work_delayable *dwork = k_work_delayable_from_work(item);
119 struct shi_it8xxx2_data *data = CONTAINER_OF(dwork, struct shi_it8xxx2_data, cs_off_put);
120
121 shi_ite_pm_policy_state_lock_put(data, SHI_ITE_PM_POLICY_FLAG);
122 }
123
124 static const uint8_t out_preamble[EC_SHI_PREAMBLE_LENGTH] = {
125 EC_SHI_PROCESSING,
126 EC_SHI_PROCESSING,
127 EC_SHI_PROCESSING,
128 /* This is the byte which matters */
129 EC_SHI_FRAME_START,
130 };
131
132 static const int shi_ite_response_state[] = {
133 [SHI_STATE_DISABLED] = EC_SHI_NOT_READY, [SHI_STATE_READY_TO_RECV] = EC_SHI_RX_READY,
134 [SHI_STATE_RECEIVING] = EC_SHI_RECEIVING, [SHI_STATE_PROCESSING] = EC_SHI_PROCESSING,
135 [SHI_STATE_RX_BAD] = EC_SHI_RX_BAD_DATA,
136 };
137 BUILD_ASSERT(ARRAY_SIZE(shi_ite_response_state) == SHI_STATE_COUNT);
138
139 #define EC_HOST_CMD_SHI_ITE_DEFINE(_name) \
140 static struct ec_host_cmd_shi_ite_ctx _name##_hc_shi_ite; \
141 struct ec_host_cmd_backend _name = { \
142 .api = &ec_host_cmd_api, \
143 .ctx = (struct ec_host_cmd_shi_ite_ctx *)&_name##_hc_shi_ite, \
144 }
145
shi_ite_set_state(struct shi_it8xxx2_data * data,int state)146 static void shi_ite_set_state(struct shi_it8xxx2_data *data, int state)
147 {
148 /* SPI peripheral state machine */
149 data->shi_state = state;
150
151 /* Response spi peripheral state */
152 IT83XX_SPI_SPISRDR = shi_ite_response_state[state];
153 }
154
shi_ite_reset_rx_fifo(void)155 static void shi_ite_reset_rx_fifo(void)
156 {
157 /* End Rx FIFO access */
158 IT83XX_SPI_TXRXFAR = 0x00;
159
160 /* Rx FIFO reset and count monitor reset */
161 IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
162 }
163
164 /* This routine handles spi received unexcepted data */
shi_ite_bad_received_data(const struct device * dev,int count)165 static void shi_ite_bad_received_data(const struct device *dev, int count)
166 {
167 struct shi_it8xxx2_data *data = dev->data;
168
169 /* State machine mismatch, timeout, or protocol we can't handle. */
170 shi_ite_set_state(data, SHI_STATE_RX_BAD);
171
172 /* End CPU access Rx FIFO, so it can clock in bytes from AP again. */
173 IT83XX_SPI_TXRXFAR = 0;
174
175 LOG_ERR("SPI rx bad data");
176 LOG_HEXDUMP_DBG(data->in_msg, count, "in_msg=");
177 }
178
shi_ite_response_host_data(const struct device * dev,uint8_t * out_msg_addr,int tx_size)179 static void shi_ite_response_host_data(const struct device *dev, uint8_t *out_msg_addr, int tx_size)
180 {
181 struct shi_it8xxx2_data *data = dev->data;
182
183 /*
184 * Protect sequence of filling response packet for host.
185 * This will ensure CPU access FIFO is disabled at SPI end interrupt no
186 * matter the interrupt is triggered before or after the sequence.
187 */
188 unsigned int key = irq_lock();
189
190 if (data->shi_state == SHI_STATE_PROCESSING) {
191 /* Tx FIFO reset and count monitor reset */
192 IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
193
194 /* CPU Tx FIFO1 and FIFO2 access */
195 IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
196
197 for (int i = 0; i < tx_size; i += 4) {
198 /* Write response data from out_msg buffer to Tx FIFO */
199 IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(out_msg_addr + i);
200 }
201
202 /*
203 * After writing data to Tx FIFO is finished, this bit will
204 * be to indicate the SPI peripheral controller.
205 */
206 IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
207
208 /* End Tx FIFO access */
209 IT83XX_SPI_TXRXFAR = 0;
210
211 /* SPI peripheral read Tx FIFO */
212 IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
213 }
214
215 irq_unlock(key);
216 }
217
218 /*
219 * Called to send a response back to the host.
220 *
221 * Some commands can continue for a while. This function is called by
222 * host_command when it completes.
223 */
shi_ite_backend_send(const struct ec_host_cmd_backend * backend)224 static int shi_ite_backend_send(const struct ec_host_cmd_backend *backend)
225 {
226 struct ec_host_cmd_shi_ite_ctx *hc_shi = (struct ec_host_cmd_shi_ite_ctx *)backend->ctx;
227 struct shi_it8xxx2_data *data = hc_shi->dev->data;
228 int tx_size;
229
230 if (data->shi_state != SHI_STATE_PROCESSING) {
231 LOG_ERR("The request data is not processing (state=%d)", data->shi_state);
232 return -EBUSY;
233 }
234
235 /* Copy preamble */
236 memcpy(data->out_msg, out_preamble, sizeof(out_preamble));
237
238 /* Data to sent are already at "out_msg + sizeof(out_preamble)" memory address(tx buf
239 * assigned in the init function), prepared by the handler.
240 * Append our past-end byte, which we reserved space for.
241 */
242 memset(&data->out_msg[sizeof(out_preamble) + data->tx->len], EC_SHI_PAST_END,
243 EC_SHI_PAST_END_LENGTH);
244
245 tx_size = data->tx->len + EC_SHI_PREAMBLE_LENGTH + EC_SHI_PAST_END_LENGTH;
246
247 /* Transmit the reply */
248 shi_ite_response_host_data(hc_shi->dev, data->out_msg, tx_size);
249
250 return 0;
251 }
252
253 /* Store request data from Rx FIFO to in_msg buffer */
shi_ite_host_request_data(uint8_t * in_msg_addr,int count)254 static void shi_ite_host_request_data(uint8_t *in_msg_addr, int count)
255 {
256 /* CPU Rx FIFO1 access */
257 IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPURXF1A;
258
259 /*
260 * In shi_ite_parse_header, the request data will separate to write in_msg buffer so we
261 * cannot set CPU to end accessing Rx FIFO in this function. We will set
262 * IT83XX_SPI_TXRXFAR = 0 in shi_ite_reset_rx_fifo.
263 */
264 for (int i = 0; i < count; i += 4) {
265 /* Get data from master to buffer */
266 *(uint32_t *)(in_msg_addr + i) = IT83XX_SPI_RXFRDRB0;
267 }
268 }
269
shi_ite_host_request_expected_size(const struct ec_host_cmd_request_header * r)270 static int shi_ite_host_request_expected_size(const struct ec_host_cmd_request_header *r)
271 {
272 /* Check host request version */
273 if (r->prtcl_ver != EC_HOST_REQUEST_VERSION) {
274 return 0;
275 }
276
277 /* Reserved byte should be 0 */
278 if (r->reserved) {
279 return 0;
280 }
281
282 return sizeof(*r) + r->data_len;
283 }
284
285 /* Parse header for version of spi-protocol */
shi_ite_parse_header(const struct device * dev)286 static void shi_ite_parse_header(const struct device *dev)
287 {
288 struct shi_it8xxx2_data *data = dev->data;
289 struct ec_host_cmd_request_header *r = (struct ec_host_cmd_request_header *)data->in_msg;
290
291 /* Store request data from Rx FIFO to in_msg buffer (rx_ctx->buf) */
292 shi_ite_host_request_data(data->in_msg, sizeof(*r));
293
294 /* Protocol version 3 */
295 if (r->prtcl_ver == EC_HOST_REQUEST_VERSION) {
296 /* Check how big the packet should be */
297 data->rx_ctx->len = shi_ite_host_request_expected_size(r);
298
299 if (data->rx_ctx->len == 0 || data->rx_ctx->len > sizeof(data->in_msg)) {
300 shi_ite_bad_received_data(dev, data->rx_ctx->len);
301 return;
302 }
303
304 /* Store request data from Rx FIFO to in_msg buffer */
305 shi_ite_host_request_data(data->rx_ctx->buf + sizeof(*r),
306 data->rx_ctx->len - sizeof(*r));
307
308 ec_host_cmd_rx_notify();
309 } else {
310 /* Invalid version number */
311 LOG_ERR("Invalid version number");
312 shi_ite_bad_received_data(dev, 1);
313 }
314 }
315
shi_ite_int_handler(const struct device * dev)316 static void shi_ite_int_handler(const struct device *dev)
317 {
318 struct shi_it8xxx2_data *data = dev->data;
319
320 if (data->shi_state == SHI_STATE_DISABLED) {
321 return;
322 }
323
324 /*
325 * The status of SPI end detection interrupt bit is set, it means that host command parse
326 * has been completed and AP has received the last byte which is EC_SHI_PAST_END from
327 * EC responded data, then AP ended the transaction.
328 */
329 if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) {
330 /* Disable CPU access Rx FIFO to clock in data from AP again */
331 IT83XX_SPI_TXRXFAR = 0;
332 /* Ready to receive */
333 shi_ite_set_state(data, SHI_STATE_READY_TO_RECV);
334 /* CS# is deasserted, so write clear all slave status */
335 IT83XX_SPI_ISR = 0xff;
336 /* Allow the MCU to go into lower power mode */
337 shi_ite_pm_policy_state_lock_put(data, SHI_ITE_PM_POLICY_FLAG);
338 }
339
340 /*
341 * The status of Rx valid length interrupt bit is set that indicates reached target count
342 * (IT83XX_SPI_FTCB1R, IT83XX_SPI_FTCB0R) and the length field of the host requested data.
343 */
344 if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
345 /* write clear slave status */
346 IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
347 /* Move to processing state */
348 shi_ite_set_state(data, SHI_STATE_PROCESSING);
349 /* Parse header for version of spi-protocol */
350 shi_ite_parse_header(dev);
351 }
352 }
353
shi_ite_cs_callback(const struct device * port,struct gpio_callback * cb,gpio_port_pins_t pins)354 void shi_ite_cs_callback(const struct device *port, struct gpio_callback *cb, gpio_port_pins_t pins)
355 {
356 struct shi_it8xxx2_data *data = CONTAINER_OF(cb, struct shi_it8xxx2_data, cs_cb);
357
358 if (data->shi_state == SHI_STATE_DISABLED) {
359 return;
360 }
361
362 /* Prevent the MCU from sleeping during the transmission */
363 shi_ite_pm_policy_state_lock_get(data, SHI_ITE_PM_POLICY_FLAG);
364
365 /* Move to processing state */
366 shi_ite_set_state(data, SHI_STATE_PROCESSING);
367 }
368
shi_ite_init_registers(const struct device * dev)369 static int shi_ite_init_registers(const struct device *dev)
370 {
371 const struct shi_it8xxx2_cfg *const cfg = dev->config;
372 /* Set FIFO data target count */
373 struct ec_host_cmd_request_header cmd_head;
374 int status;
375
376 /*
377 * Target count means the size of host request.
378 * And plus extra 4 bytes because the CPU accesses FIFO base on word. If host requested
379 * data length is one byte, we need to align the data length to 4 bytes.
380 */
381 int target_count = sizeof(cmd_head) + 4;
382 /* Offset of data_len member of host request. */
383 int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
384
385 IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
386 IT83XX_SPI_FTCB0R = target_count & 0xff;
387
388 /*
389 * The register setting can capture the length field of host
390 * request.
391 */
392 IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
393 IT83XX_SPI_TCCB0 = offset & 0xff;
394
395 /*
396 * Memory controller configuration register 3.
397 * bit6 : SPI pin function select (0b:Enable, 1b:Mask)
398 */
399 IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE;
400
401 /* Set unused blocked byte */
402 IT83XX_SPI_HPR2 = 0x00;
403
404 /* Rx valid length interrupt enabled */
405 IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
406
407 /*
408 * General control register2
409 * bit4 : Rx FIFO2 will not be overwrited once it's full.
410 * bit3 : Rx FIFO1 will not be overwrited once it's full.
411 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
412 */
413 IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC | IT83XX_SPI_RXFAR;
414
415 /*
416 * Interrupt mask register (0b:Enable, 1b:Mask)
417 * bit5 : Rx byte reach interrupt mask
418 * bit2 : SPI end detection interrupt mask
419 */
420 IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM;
421
422 /* Reset fifo and prepare to for next transaction */
423 shi_ite_reset_rx_fifo();
424
425 /* Ready to receive */
426 shi_ite_set_state(dev->data, SHI_STATE_READY_TO_RECV);
427
428 /* Interrupt status register(write one to clear) */
429 IT83XX_SPI_ISR = 0xff;
430
431 /* SPI peripheral controller enable (after settings are ready) */
432 IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN;
433
434 /* Set the pin to SHI alternate function. */
435 status = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
436 if (status < 0) {
437 LOG_ERR("Failed to configure SHI pins");
438 return status;
439 }
440
441 /* Enable SPI peripheral interrupt */
442 IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), shi_ite_int_handler,
443 DEVICE_DT_INST_GET(0), 0);
444 irq_enable(DT_INST_IRQN(0));
445
446 return 0;
447 }
448
shi_ite_init(const struct device * dev)449 static int shi_ite_init(const struct device *dev)
450 {
451 const struct shi_it8xxx2_cfg *cfg = dev->config;
452 struct shi_it8xxx2_data *data = dev->data;
453 int ret;
454
455 ret = shi_ite_init_registers(dev);
456 if (ret) {
457 return ret;
458 }
459
460 /* Configure the SPI chip select */
461 ret = gpio_pin_configure(cfg->cs.port, cfg->cs.pin, GPIO_INPUT | cfg->cs.dt_flags);
462 if (ret < 0) {
463 LOG_ERR("Failed to configure SHI CS pin");
464 return ret;
465 }
466
467 /* Enable SPI chip select pin interrupt */
468 gpio_init_callback(&data->cs_cb, shi_ite_cs_callback, BIT(cfg->cs.pin));
469 ret = gpio_add_callback(cfg->cs.port, &data->cs_cb);
470 if (ret < 0) {
471 return -EINVAL;
472 }
473
474 ret = gpio_pin_interrupt_configure(cfg->cs.port, cfg->cs.pin, GPIO_INT_EDGE_FALLING);
475 if (ret < 0) {
476 LOG_ERR("Failed to configure SHI CS interrupt");
477 return -EINVAL;
478 }
479
480 k_work_init_delayable(&data->cs_off_put, cs_off_put_handler);
481
482 pm_device_init_suspended(dev);
483 return pm_device_runtime_enable(dev);
484 }
485
shi_ite_backend_init(const struct ec_host_cmd_backend * backend,struct ec_host_cmd_rx_ctx * rx_ctx,struct ec_host_cmd_tx_buf * tx)486 static int shi_ite_backend_init(const struct ec_host_cmd_backend *backend,
487 struct ec_host_cmd_rx_ctx *rx_ctx, struct ec_host_cmd_tx_buf *tx)
488 {
489 struct ec_host_cmd_shi_ite_ctx *hc_shi = (struct ec_host_cmd_shi_ite_ctx *)backend->ctx;
490 struct shi_it8xxx2_data *data;
491
492 hc_shi->dev = DEVICE_DT_INST_GET(0);
493 if (!device_is_ready(hc_shi->dev)) {
494 return -ENODEV;
495 }
496
497 data = hc_shi->dev->data;
498 data->rx_ctx = rx_ctx;
499 data->tx = tx;
500
501 rx_ctx->buf = data->in_msg;
502 rx_ctx->len_max = CONFIG_EC_HOST_CMD_BACKEND_SHI_MAX_REQUEST;
503 tx->buf = data->out_msg + sizeof(out_preamble);
504 data->tx->len_max = CONFIG_EC_HOST_CMD_BACKEND_SHI_MAX_RESPONSE;
505
506 return 0;
507 }
508
509 PINCTRL_DT_INST_DEFINE(0);
510
511 #ifdef CONFIG_PM_DEVICE
shi_ite_pm_cb(const struct device * dev,enum pm_device_action action)512 static int shi_ite_pm_cb(const struct device *dev, enum pm_device_action action)
513 {
514 struct shi_it8xxx2_data *data = dev->data;
515 int ret = 0;
516
517 switch (action) {
518 case PM_DEVICE_ACTION_SUSPEND:
519 shi_ite_set_state(data, SHI_STATE_DISABLED);
520 break;
521 case PM_DEVICE_ACTION_RESUME:
522 shi_ite_set_state(data, SHI_STATE_READY_TO_RECV);
523 break;
524 default:
525 ret = -ENOTSUP;
526 break;
527 }
528
529 return ret;
530 }
531 #endif
532
533 /* Assume only one peripheral */
534 PM_DEVICE_DT_INST_DEFINE(0, shi_ite_pm_cb);
535
536 static const struct ec_host_cmd_backend_api ec_host_cmd_api = {
537 .init = shi_ite_backend_init,
538 .send = shi_ite_backend_send,
539 };
540
541 static const struct shi_it8xxx2_cfg shi_cfg = {
542 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
543 .cs = GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(0), cs_gpios, 0),
544 };
545
546 static struct shi_it8xxx2_data shi_data = {
547 .shi_state = SHI_STATE_DISABLED,
548 };
549
550 DEVICE_DT_INST_DEFINE(0, shi_ite_init, PM_DEVICE_DT_INST_GET(0), &shi_data, &shi_cfg, POST_KERNEL,
551 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &ec_host_cmd_api);
552
553 EC_HOST_CMD_SHI_ITE_DEFINE(ec_host_cmd_shi_ite);
554
ec_host_cmd_backend_get_shi_ite(void)555 struct ec_host_cmd_backend *ec_host_cmd_backend_get_shi_ite(void)
556 {
557 return &ec_host_cmd_shi_ite;
558 }
559
560 #if DT_NODE_EXISTS(DT_CHOSEN(zephyr_host_cmd_shi_backend)) && \
561 defined(CONFIG_EC_HOST_CMD_INITIALIZE_AT_BOOT)
host_cmd_init(void)562 static int host_cmd_init(void)
563 {
564 ec_host_cmd_init(ec_host_cmd_backend_get_shi_ite());
565 return 0;
566 }
567 SYS_INIT(host_cmd_init, POST_KERNEL, CONFIG_EC_HOST_CMD_INIT_PRIORITY);
568 #endif
569
