1 /*
2 * Copyright (C) 2023 BeagleBoard.org Foundation
3 * Copyright (C) 2023 S Prashanth
4 * Copyright (C) 2025 Siemens Mobility GmbH
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define DT_DRV_COMPAT ti_davinci_gpio
10
11 #include <errno.h>
12
13 #include <zephyr/arch/common/sys_bitops.h>
14 #include <zephyr/device.h>
15 #include <zephyr/devicetree.h>
16 #include <zephyr/drivers/gpio.h>
17 #include <zephyr/drivers/gpio/gpio_utils.h>
18 #include <zephyr/init.h>
19 #include <zephyr/kernel.h>
20 #include <zephyr/sys/sys_io.h>
21 #include <zephyr/logging/log.h>
22 #include <zephyr/drivers/pinctrl.h>
23
24 LOG_MODULE_REGISTER(gpio_davinci, CONFIG_GPIO_LOG_LEVEL);
25
26 /* Helper Macros for GPIO */
27 #define DEV_CFG(dev) \
28 ((const struct gpio_davinci_config *)((dev)->config))
29 #define DEV_DATA(dev) ((struct gpio_davinci_data *)(dev)->data)
30 #define DEV_GPIO_CFG_BASE(dev) \
31 ((struct gpio_davinci_regs *)DEVICE_MMIO_NAMED_GET(dev, port_base))
32
33 #define GPIO_DAVINCI_DIR_RESET_VAL (0xFFFFFFFF)
34
35 struct gpio_davinci_regs {
36 uint32_t dir;
37 uint32_t out_data;
38 uint32_t set_data;
39 uint32_t clr_data;
40 uint32_t in_data;
41 uint32_t set_ris_trig;
42 uint32_t clr_ris_trig;
43 uint32_t set_fal_trig;
44 uint32_t clr_fal_trig;
45 uint32_t intstat;
46 };
47
48 struct gpio_davinci_data {
49 struct gpio_driver_data common;
50
51 DEVICE_MMIO_NAMED_RAM(port_base);
52
53 sys_slist_t cb;
54 };
55
56 struct gpio_davinci_config {
57 struct gpio_driver_config common;
58 void (*bank_config)(const struct device *dev);
59
60 DEVICE_MMIO_NAMED_ROM(port_base);
61
62 uint32_t port_num;
63 const struct pinctrl_dev_config *pcfg;
64 };
65
gpio_davinci_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)66 static int gpio_davinci_configure(const struct device *dev, gpio_pin_t pin,
67 gpio_flags_t flags)
68 {
69 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
70
71 if ((flags & GPIO_SINGLE_ENDED) != 0) {
72 return -ENOTSUP;
73 }
74
75 if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
76 return -ENOTSUP;
77 }
78
79 if ((flags & GPIO_OUTPUT) != 0) {
80 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
81 regs->set_data = BIT(pin);
82 } else {
83 regs->clr_data = BIT(pin);
84 }
85 regs->dir &= ~(BIT(pin));
86 } else {
87 regs->dir |= BIT(pin);
88 }
89
90 return 0;
91 }
92
gpio_davinci_port_get_raw(const struct device * dev,gpio_port_value_t * value)93 static int gpio_davinci_port_get_raw(const struct device *dev,
94 gpio_port_value_t *value)
95 {
96 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
97
98 *value = regs->in_data;
99
100 return 0;
101 }
102
gpio_davinci_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)103 static int gpio_davinci_port_set_masked_raw(const struct device *dev,
104 gpio_port_pins_t mask, gpio_port_value_t value)
105 {
106 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
107
108 regs->out_data = (regs->out_data & (~mask)) | (mask & value);
109
110 return 0;
111 }
112
gpio_davinci_port_set_bits_raw(const struct device * dev,gpio_port_pins_t mask)113 static int gpio_davinci_port_set_bits_raw(const struct device *dev,
114 gpio_port_pins_t mask)
115 {
116 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
117
118 regs->set_data |= mask;
119
120 return 0;
121 }
122
gpio_davinci_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t mask)123 static int gpio_davinci_port_clear_bits_raw(const struct device *dev,
124 gpio_port_pins_t mask)
125 {
126 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
127
128 regs->clr_data |= mask;
129
130 return 0;
131 }
132
gpio_davinci_port_toggle_bits(const struct device * dev,gpio_port_pins_t mask)133 static int gpio_davinci_port_toggle_bits(const struct device *dev,
134 gpio_port_pins_t mask)
135 {
136 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
137
138 regs->out_data ^= mask;
139
140 return 0;
141 }
142
143 static DEVICE_API(gpio, gpio_davinci_driver_api) = {
144 .pin_configure = gpio_davinci_configure,
145 .port_get_raw = gpio_davinci_port_get_raw,
146 .port_set_masked_raw = gpio_davinci_port_set_masked_raw,
147 .port_set_bits_raw = gpio_davinci_port_set_bits_raw,
148 .port_clear_bits_raw = gpio_davinci_port_clear_bits_raw,
149 .port_toggle_bits = gpio_davinci_port_toggle_bits
150 };
151
gpio_davinci_init(const struct device * dev)152 static int gpio_davinci_init(const struct device *dev)
153 {
154 const struct gpio_davinci_config *config = DEV_CFG(dev);
155 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
156 int ret;
157
158 DEVICE_MMIO_NAMED_MAP(dev, port_base, K_MEM_CACHE_NONE);
159
160 regs->dir = GPIO_DAVINCI_DIR_RESET_VAL;
161
162 config->bank_config(dev);
163
164 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
165 if (ret < 0) {
166 LOG_ERR("failed to apply pinctrl");
167 return ret;
168 }
169 return 0;
170 }
171
172 #define GPIO_DAVINCI_INIT_FUNC(n) \
173 static void gpio_davinci_bank_##n##_config(const struct device *dev) \
174 { \
175 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); \
176 ARG_UNUSED(regs); \
177 }
178
179 #define GPIO_DAVINCI_INIT(n) \
180 PINCTRL_DT_INST_DEFINE(n); \
181 GPIO_DAVINCI_INIT_FUNC(n); \
182 static const struct gpio_davinci_config gpio_davinci_##n##_config = { \
183 .bank_config = gpio_davinci_bank_##n##_config, \
184 .common = { \
185 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
186 }, \
187 DEVICE_MMIO_NAMED_ROM_INIT(port_base, DT_DRV_INST(n)), \
188 .port_num = n, \
189 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
190 }; \
191 \
192 static struct gpio_davinci_data gpio_davinci_##n##_data; \
193 \
194 DEVICE_DT_INST_DEFINE(n, \
195 gpio_davinci_init, \
196 NULL, \
197 &gpio_davinci_##n##_data, \
198 &gpio_davinci_##n##_config, \
199 PRE_KERNEL_2, \
200 CONFIG_GPIO_INIT_PRIORITY, \
201 &gpio_davinci_driver_api);
202
203 DT_INST_FOREACH_STATUS_OKAY(GPIO_DAVINCI_INIT)
204
