1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_espi
8
9 #include <assert.h>
10 #include <stdlib.h>
11 #include <zephyr/drivers/espi.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/pinctrl.h>
15 #include <zephyr/dt-bindings/espi/npcx_espi.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/sys/byteorder.h>
18 #include <zephyr/sys/util.h>
19 #include <soc.h>
20 #include "espi_utils.h"
21 #include "soc_host.h"
22 #include "soc_miwu.h"
23
24 #include <zephyr/logging/log.h>
25 #include <zephyr/irq.h>
26 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
27
28 struct espi_npcx_config {
29 uintptr_t base;
30 /* clock configuration */
31 struct npcx_clk_cfg clk_cfg;
32 /* mapping table between eSPI reset signal and wake-up input */
33 struct npcx_wui espi_rst_wui;
34 /* pinmux configuration */
35 const struct pinctrl_dev_config *pcfg;
36 };
37
38 struct espi_npcx_data {
39 sys_slist_t callbacks;
40 uint8_t plt_rst_asserted;
41 uint8_t espi_rst_level;
42 uint8_t sx_state;
43 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
44 struct k_sem oob_rx_lock;
45 #endif
46 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
47 struct k_sem flash_rx_lock;
48 #endif
49 #ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
50 /* tell the interrupt handler that it is a fake request */
51 bool fake_req_flag;
52 #endif
53 };
54
55 #if DT_NODE_HAS_PROP(DT_DRV_INST(0), vw_index_extend_set)
56 struct espi_npcx_vw_ex {
57 uint8_t direction;
58 uint8_t group_num;
59 uint8_t index;
60 };
61
62 /* n = node, p = property, i = index */
63 #define ESPI_NPCX_VW_EX_INFO(n, p, i) \
64 { \
65 .index = ESPI_NPCX_VW_EX_INDEX(DT_PROP_BY_IDX(n, p, i)), \
66 .group_num = ESPI_NPCX_VW_EX_GROUP_NUM(DT_PROP_BY_IDX(n, p, i)), \
67 .direction = ESPI_NPCX_VW_EX_DIR(DT_PROP_BY_IDX(n, p, i)), \
68 },
69
70 static const struct espi_npcx_vw_ex espi_npcx_vw_ex_0[] = {
71 DT_FOREACH_PROP_ELEM(DT_DRV_INST(0), vw_index_extend_set, ESPI_NPCX_VW_EX_INFO)
72 };
73 #endif
74
75 /* Driver convenience defines */
76 #define HAL_INSTANCE(dev) \
77 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
78
79 /* eSPI channels */
80 #define NPCX_ESPI_CH_PC 0
81 #define NPCX_ESPI_CH_VW 1
82 #define NPCX_ESPI_CH_OOB 2
83 #define NPCX_ESPI_CH_FLASH 3
84 #define NPCX_ESPI_CH_COUNT 4
85 #define NPCX_ESPI_HOST_CH_EN(ch) (ch + 4)
86
87 /* eSPI max supported frequency */
88 #define NPCX_ESPI_MAXFREQ_20 0
89 #define NPCX_ESPI_MAXFREQ_25 1
90 #define NPCX_ESPI_MAXFREQ_33 2
91 #define NPCX_ESPI_MAXFREQ_50 3
92 #define NPCX_ESPI_MAXFREQ_66 4
93
94 /* SLP_S3/SLP_S4/SLP_S5 Virtual Wire belong to Virtual Wire Index 2 */
95 #define ESPI_VW_SLP_SX_INDEX 0x02
96
97 /* Minimum delay before acknowledging a virtual wire */
98 #define NPCX_ESPI_VWIRE_ACK_DELAY 10ul /* 10 us */
99
100 /* OOB channel maximum payload size */
101 #define NPCX_ESPI_OOB_MAX_PAYLOAD 64
102 #define NPCX_OOB_RX_PACKAGE_LEN(hdr) (((hdr & 0xff000000) >> 24) | \
103 ((hdr & 0xf0000) >> 8))
104
105 /* Flash channel maximum payload size */
106 #define NPCX_ESPI_FLASH_MAX_RX_PAYLOAD DT_INST_PROP(0, rx_plsize)
107 #define NPCX_ESPI_FLASH_MAX_TX_PAYLOAD DT_INST_PROP(0, tx_plsize)
108
109 /* eSPI cycle type field for OOB and FLASH channels */
110 #define ESPI_FLASH_READ_CYCLE_TYPE 0x00
111 #define ESPI_FLASH_WRITE_CYCLE_TYPE 0x01
112 #define ESPI_FLASH_ERASE_CYCLE_TYPE 0x02
113 #define ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE 0x0f
114 #define ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE 0x06
115 #define ESPI_FLASH_HEADER_PCKT_SIZE 0x07
116 #define ESPI_FLASH_MAX_TIMEOUT 1000ul /* 1000 ms */
117 #define ESPI_OOB_GET_CYCLE_TYPE 0x21
118 #define ESPI_OOB_TAG 0x00
119 #define ESPI_OOB_MAX_TIMEOUT 500ul /* 500 ms */
120
121 /* eSPI bus interrupt configuration structure and macro function */
122 struct espi_bus_isr {
123 uint8_t status_bit; /* bit order in ESPISTS register */
124 uint8_t int_en_bit; /* bit order in ESPIIE register */
125 uint8_t wake_en_bit; /* bit order in ESPIWE register */
126 void (*bus_isr)(const struct device *dev); /* eSPI bus ISR */
127 };
128
129 #define NPCX_ESPI_BUS_INT_ITEM(event, isr) { \
130 .status_bit = NPCX_ESPISTS_##event, \
131 .int_en_bit = NPCX_ESPIIE_##event##IE, \
132 .wake_en_bit = NPCX_ESPIWE_##event##WE, \
133 .bus_isr = isr }
134
135 /* eSPI Virtual Wire Input (Master-to-Slave) signals configuration structure */
136 struct npcx_vw_in_config {
137 enum espi_vwire_signal sig; /* Virtual Wire signal */
138 uint8_t reg_idx; /* register index for VW signal */
139 uint8_t bitmask; /* VW signal bits-mask */
140 struct npcx_wui vw_wui; /* WUI mapping in MIWU modules for VW signal */
141 };
142
143 /* eSPI Virtual Wire Output (Slave-to-Master) signals configuration structure */
144 struct npcx_vw_out_config {
145 enum espi_vwire_signal sig; /* Virtual Wire signal */
146 uint8_t reg_idx; /* register index for VW signal */
147 uint8_t bitmask; /* VW signal bits-mask */
148 };
149
150 /*
151 * eSPI VW input/Output signal configuration tables. Please refer
152 * npcxn-espi-vws-map.dtsi device tree file for more detail.
153 */
154 static const struct npcx_vw_in_config vw_in_tbl[] = {
155 /* index 02h (In) */
156 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S3, vw_slp_s3),
157 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S4, vw_slp_s4),
158 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S5, vw_slp_s5),
159 /* index 03h (In) */
160 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_STAT, vw_sus_stat),
161 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_PLTRST, vw_plt_rst),
162 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_WARN, vw_oob_rst_warn),
163 /* index 07h (In) */
164 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_WARN, vw_host_rst_warn),
165 /* index 41h (In) */
166 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_WARN, vw_sus_warn),
167 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, vw_sus_pwrdn_ack),
168 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_A, vw_slp_a),
169 /* index 42h (In) */
170 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_LAN, vw_slp_lan),
171 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_WLAN, vw_slp_wlan),
172 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_warn))
173 /* index 4Ah (In) */
174 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_DNX_WARN, vw_dnx_warn),
175 #endif
176 };
177
178 static const struct npcx_vw_out_config vw_out_tbl[] = {
179 /* index 04h (Out) */
180 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_ACK, vw_oob_rst_ack),
181 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_WAKE, vw_wake),
182 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_PME, vw_pme),
183 /* index 05h (Out) */
184 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, vw_slv_boot_done),
185 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_FATAL, vw_err_fatal),
186 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_NON_FATAL, vw_err_non_fatal),
187 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS,
188 vw_slv_boot_sts_with_done),
189 /* index 06h (Out) */
190 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SCI, vw_sci),
191 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SMI, vw_smi),
192 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_ACK, vw_host_rst_ack),
193 /* index 40h (Out) */
194 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SUS_ACK, vw_sus_ack),
195 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_ack))
196 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_DNX_ACK, vw_dnx_ack),
197 #endif
198 };
199
200 /* Virtual wire GPIOs for platform level usage (High at Reset state) */
201 static const struct npcx_vw_out_config vw_out_gpio_tbl1[] = {
202 /* Only NPCX9 and later series support this feature */
203 #if defined(CONFIG_ESPI_NPCX_SUPP_VW_GPIO)
204 /* index 50h (Out) */
205 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_0, vw_slv_gpio_0),
206 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_1, vw_slv_gpio_1),
207 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_2, vw_slv_gpio_2),
208 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_3, vw_slv_gpio_3),
209 /* index 51h (Out) */
210 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_4, vw_slv_gpio_4),
211 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_5, vw_slv_gpio_5),
212 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_6, vw_slv_gpio_6),
213 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_7, vw_slv_gpio_7),
214 #endif
215 };
216
217 /* Callbacks for eSPI bus reset and Virtual Wire signals. */
218 static struct miwu_callback espi_rst_callback;
219 static struct miwu_callback vw_in_callback[ARRAY_SIZE(vw_in_tbl)];
220
221 /* eSPI VW service function forward declarations */
222 static int espi_npcx_receive_vwire(const struct device *dev,
223 enum espi_vwire_signal signal, uint8_t *level);
224 static int espi_npcx_send_vwire(const struct device *dev,
225 enum espi_vwire_signal signal, uint8_t level);
226 static void espi_vw_send_bootload_done(const struct device *dev);
227
228 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
229 static int espi_npcx_flash_parse_completion_with_data(const struct device *dev,
230 struct espi_flash_packet *pckt);
231 static void espi_npcx_flash_prepare_tx_header(const struct device *dev, int cyc_type,
232 int flash_addr, int flash_len, int tx_payload);
233 #endif
234
235 /* eSPI local initialization functions */
espi_init_wui_callback(const struct device * dev,struct miwu_callback * callback,const struct npcx_wui * wui,miwu_dev_callback_handler_t handler)236 static void espi_init_wui_callback(const struct device *dev,
237 struct miwu_callback *callback, const struct npcx_wui *wui,
238 miwu_dev_callback_handler_t handler)
239 {
240 /* VW signal which has no wake-up input source */
241 if (wui->table == NPCX_MIWU_TABLE_NONE) {
242 return;
243 }
244
245 /* Install callback function */
246 npcx_miwu_init_dev_callback(callback, wui, handler, dev);
247 npcx_miwu_manage_callback(callback, 1);
248
249 /* Configure MIWU setting and enable its interrupt */
250 npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
251 NPCX_MIWU_TRIG_BOTH);
252 }
253
254 /* eSPI local bus interrupt service functions */
espi_bus_err_isr(const struct device * dev)255 static void espi_bus_err_isr(const struct device *dev)
256 {
257 struct espi_reg *const inst = HAL_INSTANCE(dev);
258 uint32_t err = inst->ESPIERR;
259
260 LOG_ERR("eSPI Bus Error %08X", err);
261 /* Clear error status bits */
262 inst->ESPIERR = err;
263 }
264
espi_bus_inband_rst_isr(const struct device * dev)265 static void espi_bus_inband_rst_isr(const struct device *dev)
266 {
267 ARG_UNUSED(dev);
268 LOG_DBG("%s issued", __func__);
269 }
270
espi_bus_reset_isr(const struct device * dev)271 static void espi_bus_reset_isr(const struct device *dev)
272 {
273 ARG_UNUSED(dev);
274 LOG_DBG("%s issued", __func__);
275 /* Do nothing! This signal is handled in ESPI_RST VW signal ISR */
276 }
277
278 #if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND)
espi_npcx_flash_fake_request(const struct device * dev)279 static void espi_npcx_flash_fake_request(const struct device *dev)
280 {
281 struct espi_reg *const inst = HAL_INSTANCE(dev);
282 struct espi_npcx_data *const data = dev->data;
283
284 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AMTEN);
285
286 data->fake_req_flag = true;
287
288 espi_npcx_flash_prepare_tx_header(dev, ESPI_FLASH_READ_CYCLE_TYPE, 0, 16, 0);
289 }
290 #endif
291
espi_bus_cfg_update_isr(const struct device * dev)292 static void espi_bus_cfg_update_isr(const struct device *dev)
293 {
294 int chan;
295 struct espi_reg *const inst = HAL_INSTANCE(dev);
296 struct espi_npcx_data *const data = dev->data;
297 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
298 .evt_details = 0,
299 .evt_data = 0 };
300 /* If host enable bits are not sync with ready bits on slave side. */
301 uint8_t chg_mask = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_HCHANS_FIELD)
302 ^ GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_CHANS_FIELD);
303 chg_mask &= (ESPI_CHANNEL_VWIRE | ESPI_CHANNEL_OOB |
304 ESPI_CHANNEL_FLASH);
305
306 LOG_DBG("ESPI CFG Change Updated! 0x%02X", chg_mask);
307 /*
308 * If host enable/disable channel for VW/OOB/FLASH, EC should follow
309 * except Peripheral channel. It is handled after receiving PLTRST
310 * event separately.
311 */
312 for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT; chan++) {
313 /* Channel ready bit isn't sync with enabled bit on host side */
314 if (chg_mask & BIT(chan)) {
315 evt.evt_data = IS_BIT_SET(inst->ESPICFG,
316 NPCX_ESPI_HOST_CH_EN(chan));
317 evt.evt_details = BIT(chan);
318
319 #if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND)
320 if (chan == NPCX_ESPI_CH_FLASH && evt.evt_data == 1 &&
321 IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
322 espi_npcx_flash_fake_request(dev);
323 }
324 #endif
325
326 if (evt.evt_data) {
327 inst->ESPICFG |= BIT(chan);
328 } else {
329 inst->ESPICFG &= ~BIT(chan);
330 }
331
332 espi_send_callbacks(&data->callbacks, dev, evt);
333 }
334 }
335 LOG_DBG("ESPI CFG EC Updated! 0x%02X", GET_FIELD(inst->ESPICFG,
336 NPCX_ESPICFG_CHANS_FIELD));
337
338 /* If VW channel is enabled and ready, send bootload done VW signal */
339 if ((chg_mask & BIT(NPCX_ESPI_CH_VW)) && IS_BIT_SET(inst->ESPICFG,
340 NPCX_ESPI_HOST_CH_EN(NPCX_ESPI_CH_VW))) {
341 espi_vw_send_bootload_done(dev);
342 }
343
344 #if (defined(CONFIG_ESPI_FLASH_CHANNEL) && defined(CONFIG_ESPI_TAF))
345 /* If CONFIG_ESPI_TAF is set, set to auto or manual mode accroding
346 * to configuration.
347 */
348 if (IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_FLCHANMODE)) {
349 #if defined(CONFIG_ESPI_TAF_AUTO_MODE)
350 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
351 #else
352 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
353 #endif
354 }
355 #endif
356 }
357
358 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_bus_oob_rx_isr(const struct device * dev)359 static void espi_bus_oob_rx_isr(const struct device *dev)
360 {
361 struct espi_npcx_data *const data = dev->data;
362 #if defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
363 struct espi_reg *const inst = HAL_INSTANCE(dev);
364 struct espi_event evt = {
365 .evt_type = ESPI_BUS_EVENT_OOB_RECEIVED,
366 .evt_details = 0,
367 .evt_data = 0,
368 };
369
370 /* Get received package length and set to additional detail of event */
371 evt.evt_details = NPCX_OOB_RX_PACKAGE_LEN(inst->OOBRXBUF[0]);
372 espi_send_callbacks(&data->callbacks, dev, evt);
373 #else
374
375 LOG_DBG("%s", __func__);
376 k_sem_give(&data->oob_rx_lock);
377 #endif
378 }
379 #endif
380
381 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
382 #if defined(CONFIG_ESPI_TAF)
383 static struct espi_taf_pckt taf_pckt;
384
espi_taf_parse(const struct device * dev)385 static uint32_t espi_taf_parse(const struct device *dev)
386 {
387 struct espi_reg *const inst = HAL_INSTANCE(dev);
388 struct npcx_taf_head taf_head;
389 uint32_t taf_addr, head_data;
390 uint8_t i, roundsize;
391
392 /* Get type, length and tag from RX buffer */
393 head_data = inst->FLASHRXBUF[0];
394 taf_head = *(struct npcx_taf_head *)&head_data;
395
396 taf_pckt.type = taf_head.type;
397 taf_pckt.len = (((uint16_t)taf_head.tag_hlen & 0xF) << 8) | taf_head.llen;
398 taf_pckt.tag = taf_head.tag_hlen >> 4;
399
400 if ((taf_pckt.len == 0) && (taf_pckt.type == NPCX_ESPI_TAF_REQ_READ)) {
401 taf_pckt.len = KB(4);
402 }
403
404 /* Get address from RX buffer */
405 taf_addr = inst->FLASHRXBUF[1];
406 taf_pckt.addr = sys_cpu_to_be32(taf_addr);
407
408 /* Get written data if eSPI TAF write or RPMC OP1 */
409 if ((taf_pckt.type == NPCX_ESPI_TAF_REQ_WRITE) ||
410 (IS_ENABLED(CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT) &&
411 (taf_pckt.type == NPCX_ESPI_TAF_REQ_RPMC_OP1))) {
412 roundsize = DIV_ROUND_UP(taf_pckt.len, sizeof(uint32_t));
413 for (i = 0; i < roundsize; i++) {
414 taf_pckt.src[i] = inst->FLASHRXBUF[2 + i];
415 }
416 }
417
418 return (uint32_t)&taf_pckt;
419 }
420 #endif /* CONFIG_ESPI_TAF */
421
espi_bus_flash_rx_isr(const struct device * dev)422 static void espi_bus_flash_rx_isr(const struct device *dev)
423 {
424 struct espi_reg *const inst = HAL_INSTANCE(dev);
425 struct espi_npcx_data *const data = dev->data;
426
427 /* Controller Attached Flash Access */
428 if ((inst->ESPICFG & BIT(NPCX_ESPICFG_FLCHANMODE)) == 0) {
429 #ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
430 if (data->fake_req_flag == true) {
431 uint8_t pckt_buf[16];
432 struct espi_flash_packet pckt;
433
434 pckt.buf = &pckt_buf[0];
435 espi_npcx_flash_parse_completion_with_data(dev, &pckt);
436 data->fake_req_flag = false;
437 return;
438 }
439 #endif
440 k_sem_give(&data->flash_rx_lock);
441 } else { /* Target Attached Flash Access */
442 #if defined(CONFIG_ESPI_TAF)
443 struct espi_event evt = {
444 .evt_type = ESPI_BUS_TAF_NOTIFICATION,
445 .evt_details = ESPI_CHANNEL_FLASH,
446 .evt_data = espi_taf_parse(dev),
447 };
448 espi_send_callbacks(&data->callbacks, dev, evt);
449 #else
450 LOG_WRN("ESPI TAF not supported");
451 #endif
452 }
453 }
454 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
455
456 const struct espi_bus_isr espi_bus_isr_tbl[] = {
457 NPCX_ESPI_BUS_INT_ITEM(BERR, espi_bus_err_isr),
458 NPCX_ESPI_BUS_INT_ITEM(IBRST, espi_bus_inband_rst_isr),
459 NPCX_ESPI_BUS_INT_ITEM(ESPIRST, espi_bus_reset_isr),
460 NPCX_ESPI_BUS_INT_ITEM(CFGUPD, espi_bus_cfg_update_isr),
461 #if defined(CONFIG_ESPI_OOB_CHANNEL)
462 NPCX_ESPI_BUS_INT_ITEM(OOBRX, espi_bus_oob_rx_isr),
463 #endif
464 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
465 NPCX_ESPI_BUS_INT_ITEM(FLASHRX, espi_bus_flash_rx_isr),
466 #endif
467 };
468
espi_bus_generic_isr(const struct device * dev)469 static void espi_bus_generic_isr(const struct device *dev)
470 {
471 struct espi_reg *const inst = HAL_INSTANCE(dev);
472 int i;
473 uint32_t mask, status;
474
475 /*
476 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
477 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
478 */
479 mask = inst->ESPIIE | (1 << NPCX_ESPISTS_VWUPDW);
480 status = inst->ESPISTS & mask;
481
482 /* Clear pending bits of status register first */
483 inst->ESPISTS = status;
484
485 LOG_DBG("%s: 0x%08X", __func__, status);
486 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
487 struct espi_bus_isr entry = espi_bus_isr_tbl[i];
488
489 if (status & BIT(entry.status_bit)) {
490 if (entry.bus_isr != NULL) {
491 entry.bus_isr(dev);
492 }
493 }
494 }
495 }
496
497 /* eSPI local virtual-wire service functions */
espi_vw_config_input(const struct device * dev,const struct npcx_vw_in_config * config_in)498 static void espi_vw_config_input(const struct device *dev,
499 const struct npcx_vw_in_config *config_in)
500 {
501 struct espi_reg *const inst = HAL_INSTANCE(dev);
502 int idx = config_in->reg_idx;
503
504 if (IS_ENABLED(CONFIG_ESPI_NPCX_RESET_SLP_SX_VW_ON_ESPI_RST)) {
505 uint8_t vwire_index = GET_FIELD(inst->VWEVMS[idx], NPCX_VWEVMS_INDEX);
506
507 if (vwire_index == ESPI_VW_SLP_SX_INDEX) {
508 inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_ENESPIRST);
509 }
510 }
511
512 /* IE & WE bits are already set? */
513 if (IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_IE) &&
514 IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE)) {
515 return;
516 }
517
518 /* Set IE & WE bits in VWEVMS */
519 inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_IE) | BIT(NPCX_VWEVMS_WE);
520 LOG_DBG("VWEVMS%d 0x%08X", idx, inst->VWEVMS[idx]);
521 }
522
espi_vw_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out)523 static void espi_vw_config_output(const struct device *dev,
524 const struct npcx_vw_out_config *config_out)
525 {
526 struct espi_reg *const inst = HAL_INSTANCE(dev);
527 int idx = config_out->reg_idx;
528 uint8_t valid = GET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID);
529
530 /* Set valid bits for vw signal which we have declared in table. */
531 valid |= config_out->bitmask;
532 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID, valid);
533
534 /*
535 * Turn off hardware-wire feature which generates VW events that
536 * connected to hardware signals. We will set it manually by software.
537 */
538 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_HW_WIRE, 0);
539
540 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWEVSM[idx]);
541 }
542
espi_vw_gpio_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out,uint8_t init_level)543 static void espi_vw_gpio_config_output(const struct device *dev,
544 const struct npcx_vw_out_config *config_out,
545 uint8_t init_level)
546 {
547 struct espi_reg *const inst = HAL_INSTANCE(dev);
548 int idx = config_out->reg_idx;
549 uint8_t valid = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID);
550 uint8_t val = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE);
551
552 /* Set valid bits for vw signal which we have declared in table. */
553 valid |= config_out->bitmask;
554 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID, valid);
555
556 inst->VWGPSM[idx] |= BIT(NPCX_VWGPSM_INDEX_EN);
557
558 if (init_level) {
559 val |= config_out->bitmask;
560 } else {
561 val &= ~config_out->bitmask;
562 }
563
564 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE, val);
565
566 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWGPSM[idx]);
567 }
568
espi_vw_notify_system_state(const struct device * dev,enum espi_vwire_signal signal)569 static void espi_vw_notify_system_state(const struct device *dev,
570 enum espi_vwire_signal signal)
571 {
572 struct espi_npcx_data *const data = dev->data;
573 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
574 uint8_t wire = 0;
575
576 espi_npcx_receive_vwire(dev, signal, &wire);
577 if (!wire) {
578 data->sx_state = signal;
579 }
580
581 evt.evt_details = signal;
582 evt.evt_data = wire;
583 espi_send_callbacks(&data->callbacks, dev, evt);
584 }
585
espi_vw_notify_host_warning(const struct device * dev,enum espi_vwire_signal signal)586 static void espi_vw_notify_host_warning(const struct device *dev,
587 enum espi_vwire_signal signal)
588 {
589 uint8_t wire;
590
591 espi_npcx_receive_vwire(dev, signal, &wire);
592
593 k_busy_wait(NPCX_ESPI_VWIRE_ACK_DELAY);
594 switch (signal) {
595 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
596 espi_npcx_send_vwire(dev,
597 ESPI_VWIRE_SIGNAL_HOST_RST_ACK,
598 wire);
599 break;
600 case ESPI_VWIRE_SIGNAL_SUS_WARN:
601 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK,
602 wire);
603 break;
604 case ESPI_VWIRE_SIGNAL_OOB_RST_WARN:
605 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK,
606 wire);
607 break;
608 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_warn))
609 case ESPI_VWIRE_SIGNAL_DNX_WARN:
610 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_DNX_ACK, wire);
611 break;
612 #endif
613 default:
614 break;
615 }
616 }
617
espi_vw_notify_plt_rst(const struct device * dev)618 static void espi_vw_notify_plt_rst(const struct device *dev)
619 {
620 struct espi_npcx_data *const data = dev->data;
621 struct espi_reg *const inst = HAL_INSTANCE(dev);
622 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED,
623 ESPI_VWIRE_SIGNAL_PLTRST, 0
624 };
625 uint8_t wire = 0;
626
627 espi_npcx_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &wire);
628 LOG_DBG("VW_PLT_RST is %d!", wire);
629 if (wire) {
630 /* Set Peripheral Channel ready when PLTRST is de-asserted */
631 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCHANEN);
632 /* Configure all host sub-modules in host domain */
633 npcx_host_init_subs_host_domain();
634 }
635
636 /* PLT_RST will be received several times */
637 if (wire != data->plt_rst_asserted) {
638 data->plt_rst_asserted = wire;
639 evt.evt_data = wire;
640 espi_send_callbacks(&data->callbacks, dev, evt);
641 }
642 }
643
espi_vw_send_bootload_done(const struct device * dev)644 static void espi_vw_send_bootload_done(const struct device *dev)
645 {
646 int ret;
647 uint8_t boot_done;
648
649 ret = espi_npcx_receive_vwire(dev,
650 ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, &boot_done);
651 LOG_DBG("%s: %d", __func__, boot_done);
652 if (!ret && !boot_done) {
653 /* Send slave boot status bit with done bit at the same time. */
654 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS, 1);
655 }
656 }
657
espi_vw_generic_isr(const struct device * dev,struct npcx_wui * wui)658 static void espi_vw_generic_isr(const struct device *dev, struct npcx_wui *wui)
659 {
660 int idx;
661 enum espi_vwire_signal signal;
662
663 LOG_DBG("%s: WUI %d %d %d", __func__, wui->table, wui->group, wui->bit);
664 for (idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
665 if (wui->table == vw_in_tbl[idx].vw_wui.table &&
666 wui->group == vw_in_tbl[idx].vw_wui.group &&
667 wui->bit == vw_in_tbl[idx].vw_wui.bit) {
668 break;
669 }
670 }
671
672 if (idx == ARRAY_SIZE(vw_in_tbl)) {
673 LOG_ERR("Unknown VW event! %d %d %d", wui->table,
674 wui->group, wui->bit);
675 return;
676 }
677
678 signal = vw_in_tbl[idx].sig;
679 if (signal == ESPI_VWIRE_SIGNAL_SLP_S3
680 || signal == ESPI_VWIRE_SIGNAL_SLP_S4
681 || signal == ESPI_VWIRE_SIGNAL_SLP_S5
682 || signal == ESPI_VWIRE_SIGNAL_SLP_A) {
683 espi_vw_notify_system_state(dev, signal);
684 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_warn))
685 } else if (signal == ESPI_VWIRE_SIGNAL_HOST_RST_WARN
686 || signal == ESPI_VWIRE_SIGNAL_SUS_WARN
687 || signal == ESPI_VWIRE_SIGNAL_OOB_RST_WARN
688 || signal == ESPI_VWIRE_SIGNAL_DNX_WARN) {
689 #else
690 } else if (signal == ESPI_VWIRE_SIGNAL_HOST_RST_WARN
691 || signal == ESPI_VWIRE_SIGNAL_SUS_WARN
692 || signal == ESPI_VWIRE_SIGNAL_OOB_RST_WARN) {
693 #endif
694 espi_vw_notify_host_warning(dev, signal);
695 } else if (signal == ESPI_VWIRE_SIGNAL_PLTRST) {
696 espi_vw_notify_plt_rst(dev);
697 }
698 }
699
espi_vw_espi_rst_isr(const struct device * dev,struct npcx_wui * wui)700 static void espi_vw_espi_rst_isr(const struct device *dev, struct npcx_wui *wui)
701 {
702 struct espi_reg *const inst = HAL_INSTANCE(dev);
703 struct espi_npcx_data *const data = dev->data;
704 struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
705
706 data->espi_rst_level = IS_BIT_SET(inst->ESPISTS,
707 NPCX_ESPISTS_ESPIRST_LVL);
708 LOG_DBG("eSPI RST level is %d!", data->espi_rst_level);
709
710 evt.evt_data = data->espi_rst_level;
711 espi_send_callbacks(&data->callbacks, dev, evt);
712 }
713
714 /* eSPI api functions */
espi_npcx_configure(const struct device * dev,struct espi_cfg * cfg)715 static int espi_npcx_configure(const struct device *dev, struct espi_cfg *cfg)
716 {
717 struct espi_reg *const inst = HAL_INSTANCE(dev);
718
719 uint8_t max_freq = 0;
720 uint8_t cur_io_mode, io_mode = 0;
721
722 /* Configure eSPI frequency */
723 switch (cfg->max_freq) {
724 case 20:
725 max_freq = NPCX_ESPI_MAXFREQ_20;
726 break;
727 case 25:
728 max_freq = NPCX_ESPI_MAXFREQ_25;
729 break;
730 case 33:
731 max_freq = NPCX_ESPI_MAXFREQ_33;
732 break;
733 case 50:
734 max_freq = NPCX_ESPI_MAXFREQ_50;
735 break;
736 #ifdef CONFIG_SOC_SERIES_NPCX4
737 case 66:
738 max_freq = NPCX_ESPI_MAXFREQ_66;
739 break;
740 #endif
741 default:
742 return -EINVAL;
743 }
744 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD, max_freq);
745
746 /* Configure eSPI IO mode */
747 io_mode = (cfg->io_caps >> 1);
748 if (io_mode > 3) {
749 return -EINVAL;
750 }
751
752 cur_io_mode = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD);
753 if (io_mode != cur_io_mode) {
754 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD, io_mode);
755 }
756
757 /* Configure eSPI supported channels */
758 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
759 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCCHN_SUPP);
760 }
761
762 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
763 inst->ESPICFG |= BIT(NPCX_ESPICFG_VWCHN_SUPP);
764 }
765
766 if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
767 inst->ESPICFG |= BIT(NPCX_ESPICFG_OOBCHN_SUPP);
768 }
769
770 if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
771 inst->ESPICFG |= BIT(NPCX_ESPICFG_FLASHCHN_SUPP);
772 }
773
774 LOG_DBG("%s: %d %d ESPICFG: 0x%08X", __func__,
775 max_freq, io_mode, inst->ESPICFG);
776
777 return 0;
778 }
779
espi_npcx_channel_ready(const struct device * dev,enum espi_channel ch)780 static bool espi_npcx_channel_ready(const struct device *dev,
781 enum espi_channel ch)
782 {
783 struct espi_reg *const inst = HAL_INSTANCE(dev);
784 bool sts;
785
786 switch (ch) {
787 case ESPI_CHANNEL_PERIPHERAL:
788 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_PCHANEN);
789 break;
790 case ESPI_CHANNEL_VWIRE:
791 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_VWCHANEN);
792 break;
793 case ESPI_CHANNEL_OOB:
794 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_OOBCHANEN);
795 break;
796 case ESPI_CHANNEL_FLASH:
797 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_FLASHCHANEN);
798 break;
799 default:
800 sts = false;
801 break;
802 }
803
804 return sts;
805 }
806
espi_npcx_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)807 static int espi_npcx_send_vwire(const struct device *dev,
808 enum espi_vwire_signal signal, uint8_t level)
809 {
810 uint8_t reg_idx, bitmask, sig_idx, val = 0, vw_tbl_size;
811 struct espi_reg *const inst = HAL_INSTANCE(dev);
812 const struct npcx_vw_out_config *vw_tbl;
813 uint32_t reg_val;
814 char *reg_name;
815
816 if (signal >= ESPI_VWIRE_SIGNAL_COUNT) {
817 LOG_ERR("Invalid VW: %d", signal);
818 return -EINVAL;
819 }
820
821 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
822 vw_tbl = vw_out_gpio_tbl1;
823 vw_tbl_size = ARRAY_SIZE(vw_out_gpio_tbl1);
824 reg_name = "VWGPSM";
825 } else {
826 vw_tbl = vw_out_tbl;
827 vw_tbl_size = ARRAY_SIZE(vw_out_tbl);
828 reg_name = "VWEVSM";
829 }
830
831 /* Find signal in VW output table */
832 for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++) {
833 if (vw_tbl[sig_idx].sig == signal) {
834 break;
835 }
836 }
837
838 if (sig_idx == vw_tbl_size) {
839 LOG_ERR("%s signal %d is invalid", __func__, signal);
840 return -EIO;
841 }
842
843 reg_idx = vw_tbl[sig_idx].reg_idx;
844 bitmask = vw_tbl[sig_idx].bitmask;
845
846 /* Get wire field and set/clear wire bit */
847 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
848 val = GET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE);
849 } else {
850 val = GET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE);
851 }
852
853 if (level) {
854 val |= bitmask;
855 } else {
856 val &= ~bitmask;
857 }
858
859 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
860 SET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE, val);
861 reg_val = inst->VWGPSM[reg_idx];
862 } else {
863 SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
864 reg_val = inst->VWEVSM[reg_idx];
865 }
866
867 LOG_DBG("Send VW: %s%d 0x%08X", reg_name, reg_idx, reg_val);
868
869 return 0;
870 }
871
espi_npcx_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)872 static int espi_npcx_receive_vwire(const struct device *dev,
873 enum espi_vwire_signal signal, uint8_t *level)
874 {
875 struct espi_reg *const inst = HAL_INSTANCE(dev);
876 uint8_t reg_idx, bitmask, sig_idx, val;
877
878 /* Find signal in VW input table */
879 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++) {
880 if (vw_in_tbl[sig_idx].sig == signal) {
881 reg_idx = vw_in_tbl[sig_idx].reg_idx;
882 bitmask = vw_in_tbl[sig_idx].bitmask;
883
884 val = GET_FIELD(inst->VWEVMS[reg_idx],
885 NPCX_VWEVMS_WIRE);
886
887 if (IS_ENABLED(CONFIG_ESPI_VWIRE_VALID_BIT_CHECK)) {
888 val &= GET_FIELD(inst->VWEVMS[reg_idx],
889 NPCX_VWEVMS_VALID);
890 }
891
892 *level = !!(val & bitmask);
893 return 0;
894 }
895 }
896
897 /* Find signal in VW output table */
898 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++) {
899 if (vw_out_tbl[sig_idx].sig == signal) {
900 reg_idx = vw_out_tbl[sig_idx].reg_idx;
901 bitmask = vw_out_tbl[sig_idx].bitmask;
902
903 val = GET_FIELD(inst->VWEVSM[reg_idx],
904 NPCX_VWEVSM_WIRE);
905
906 if (IS_ENABLED(CONFIG_ESPI_VWIRE_VALID_BIT_CHECK)) {
907 val &= GET_FIELD(inst->VWEVSM[reg_idx],
908 NPCX_VWEVSM_VALID);
909 }
910
911 *level = !!(val & bitmask);
912 return 0;
913 }
914 }
915
916 LOG_ERR("%s Out of index %d", __func__, signal);
917 return -EIO;
918 }
919
espi_npcx_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)920 static int espi_npcx_manage_callback(const struct device *dev,
921 struct espi_callback *callback, bool set)
922 {
923 struct espi_npcx_data *const data = dev->data;
924
925 return espi_manage_callback(&data->callbacks, callback, set);
926 }
927
espi_npcx_read_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)928 static int espi_npcx_read_lpc_request(const struct device *dev,
929 enum lpc_peripheral_opcode op,
930 uint32_t *data)
931 {
932 ARG_UNUSED(dev);
933
934 return npcx_host_periph_read_request(op, data);
935 }
936
espi_npcx_write_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)937 static int espi_npcx_write_lpc_request(const struct device *dev,
938 enum lpc_peripheral_opcode op,
939 uint32_t *data)
940 {
941 ARG_UNUSED(dev);
942
943 return npcx_host_periph_write_request(op, data);
944 }
945
946 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_npcx_send_oob(const struct device * dev,struct espi_oob_packet * pckt)947 static int espi_npcx_send_oob(const struct device *dev,
948 struct espi_oob_packet *pckt)
949 {
950 struct espi_reg *const inst = HAL_INSTANCE(dev);
951 uint8_t *oob_buf = pckt->buf;
952 int sz_oob_tx = pckt->len;
953 int idx_tx_buf;
954 uint32_t oob_data;
955
956 /* Check out of OOB transmitted buffer size */
957 if (sz_oob_tx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
958 LOG_ERR("Out of OOB transmitted buffer: %d", sz_oob_tx);
959 return -EINVAL;
960 }
961
962 /* Check OOB Transmit Queue is empty? */
963 if (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
964 LOG_ERR("OOB channel is busy");
965 return -EBUSY;
966 }
967
968 /*
969 * GET_OOB header (first 4 bytes) in npcx 32-bits tx buffer
970 *
971 * [24:31] - LEN[0:7] Data length of GET_OOB request package
972 * [20:23] - TAG Tag of GET_OOB
973 * [16:19] - LEN[8:11] Ignore it since max payload is 64 bytes
974 * [8:15] - CYCLE_TYPE Cycle type of GET_OOB
975 * [0:7] - SZ_PACK Package size plus 3 bytes header. (Npcx only)
976 */
977 inst->OOBTXBUF[0] = (sz_oob_tx + 3)
978 | (ESPI_OOB_GET_CYCLE_TYPE << 8)
979 | (ESPI_OOB_TAG << 16)
980 | (sz_oob_tx << 24);
981
982 /* Write GET_OOB data into 32-bits tx buffer in little endian */
983 for (idx_tx_buf = 0; idx_tx_buf < sz_oob_tx/4; idx_tx_buf++,
984 oob_buf += 4)
985 inst->OOBTXBUF[idx_tx_buf + 1] = oob_buf[0]
986 | (oob_buf[1] << 8)
987 | (oob_buf[2] << 16)
988 | (oob_buf[3] << 24);
989
990 /* Write remaining bytes of package */
991 if (sz_oob_tx % 4) {
992 int i;
993
994 oob_data = 0;
995 for (i = 0; i < sz_oob_tx % 4; i++) {
996 oob_data |= (oob_buf[i] << (8 * i));
997 }
998 inst->OOBTXBUF[idx_tx_buf + 1] = oob_data;
999 }
1000
1001 /*
1002 * Notify host a new OOB packet is ready. Please don't write OOB_FREE
1003 * to 1 at the same tiem in case clear it unexpectedly.
1004 */
1005 oob_data = inst->OOBCTL & ~(BIT(NPCX_OOBCTL_OOB_FREE));
1006 oob_data |= BIT(NPCX_OOBCTL_OOB_AVAIL);
1007 inst->OOBCTL = oob_data;
1008
1009 while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
1010 ;
1011 }
1012
1013 LOG_DBG("%s issued!!", __func__);
1014 return 0;
1015 }
1016
espi_npcx_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)1017 static int espi_npcx_receive_oob(const struct device *dev,
1018 struct espi_oob_packet *pckt)
1019 {
1020 struct espi_reg *const inst = HAL_INSTANCE(dev);
1021 uint8_t *oob_buf = pckt->buf;
1022 uint32_t oob_data;
1023 int idx_rx_buf, sz_oob_rx;
1024
1025 /* Check eSPI bus status first */
1026 if (IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_BERR)) {
1027 LOG_ERR("%s: eSPI Bus Error: 0x%08X", __func__, inst->ESPIERR);
1028 return -EIO;
1029 }
1030
1031 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
1032 struct espi_npcx_data *const data = dev->data;
1033 int ret;
1034
1035 /* Wait until get oob package or timeout */
1036 ret = k_sem_take(&data->oob_rx_lock, K_MSEC(ESPI_OOB_MAX_TIMEOUT));
1037 if (ret == -EAGAIN) {
1038 LOG_ERR("%s: Timeout", __func__);
1039 return -ETIMEDOUT;
1040 }
1041 #endif
1042
1043 /*
1044 * PUT_OOB header (first 4 bytes) in npcx 32-bits rx buffer
1045 *
1046 * [24:31] - LEN[0:7] Data length of PUT_OOB request package
1047 * [20:23] - TAG Tag of PUT_OOB
1048 * [16:19] - LEN[8:11] Data length of PUT_OOB request package
1049 * [8:15] - CYCLE_TYPE Cycle type of PUT_OOB
1050 * [0:7] - SZ_PACK Reserved. (Npcx only)
1051 */
1052 oob_data = inst->OOBRXBUF[0];
1053 /* Get received package length first */
1054 sz_oob_rx = NPCX_OOB_RX_PACKAGE_LEN(oob_data);
1055
1056 /* Check OOB received buffer size */
1057 if (sz_oob_rx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
1058 LOG_ERR("Out of OOB received buffer: %d", sz_oob_rx);
1059 return -EINVAL;
1060 }
1061
1062 /* Set received size to package structure */
1063 pckt->len = sz_oob_rx;
1064
1065 /* Read PUT_OOB data into 32-bits rx buffer in little endian */
1066 for (idx_rx_buf = 0; idx_rx_buf < sz_oob_rx/4; idx_rx_buf++) {
1067 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
1068
1069 *(oob_buf++) = oob_data & 0xFF;
1070 *(oob_buf++) = (oob_data >> 8) & 0xFF;
1071 *(oob_buf++) = (oob_data >> 16) & 0xFF;
1072 *(oob_buf++) = (oob_data >> 24) & 0xFF;
1073 }
1074
1075 /* Read remaining bytes of package */
1076 if (sz_oob_rx % 4) {
1077 int i;
1078
1079 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
1080 for (i = 0; i < sz_oob_rx % 4; i++) {
1081 *(oob_buf++) = (oob_data >> (8 * i)) & 0xFF;
1082 }
1083 }
1084
1085 /* Notify host that OOB received buffer is free now. */
1086 inst->OOBCTL |= BIT(NPCX_OOBCTL_OOB_FREE);
1087 return 0;
1088 }
1089 #endif
1090
1091 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_npcx_flash_prepare_tx_header(const struct device * dev,int cyc_type,int flash_addr,int flash_len,int tx_payload)1092 static void espi_npcx_flash_prepare_tx_header(const struct device *dev,
1093 int cyc_type, int flash_addr, int flash_len, int tx_payload)
1094 {
1095 struct espi_reg *const inst = HAL_INSTANCE(dev);
1096
1097 /*
1098 * First 3 bytes of flash cycle command header in tx buffer
1099 *
1100 * [24:31] - LEN[0:7] = n Data length of flash cycle request
1101 * [16:23] - LEN[8:15] = 0 Ignore it since max buffer size is 64 bytes
1102 * [12:15] - TAG = 0 Tag of flash cycle command is always 0 here
1103 * [8:11] - CYCLE_TYPE = 0 Cycle type of flash command
1104 * [0:7] - SZ_PACK = 7 Overall tx package size. (Used internally.)
1105 */
1106 inst->FLASHTXBUF[0] = (flash_len << 24) |
1107 (cyc_type << 8) |
1108 (tx_payload + ESPI_FLASH_HEADER_PCKT_SIZE);
1109
1110 /*
1111 * Following 4 bytes of tager flash address in tx buffer
1112 *
1113 * [24:31] - ADDR[0:7] Start address of flash cycle command request
1114 * [16:23] - ADDR[15:8]
1115 * [8:15] - ADDR[23:16]
1116 * [0:7] - ADDR[31:24]
1117 */
1118 inst->FLASHTXBUF[1] = sys_cpu_to_be32(flash_addr);
1119
1120 }
1121
espi_npcx_flash_parse_completion(const struct device * dev)1122 static int espi_npcx_flash_parse_completion(const struct device *dev)
1123 {
1124 int cycle_type;
1125 struct espi_reg *const inst = HAL_INSTANCE(dev);
1126
1127 /*
1128 * First 3 bytes of flash cycle completion header in rx buffer
1129 *
1130 * [24:31] - LEN[0:7] Data length of flash cycle completion package
1131 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
1132 * [12:15] - TAG Tag of flash cycle completion package
1133 * [8:11] - CYCLE_TYPE Cycle type of flash completion
1134 * [0:7] - Reserved
1135 */
1136 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
1137 if (cycle_type == ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE) {
1138 return 0;
1139 }
1140
1141 return -EIO;
1142 }
1143
espi_npcx_flash_parse_completion_with_data(const struct device * dev,struct espi_flash_packet * pckt)1144 static int espi_npcx_flash_parse_completion_with_data(const struct device *dev,
1145 struct espi_flash_packet *pckt)
1146 {
1147 struct espi_reg *const inst = HAL_INSTANCE(dev);
1148 int cycle_type, sz_rx_payload;
1149
1150 /*
1151 * First 3 bytes of flash cycle completion header in rx buffer
1152 *
1153 * [24:31] - LEN[0:7] Data length of flash cycle completion package
1154 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
1155 * [12:15] - TAG Tag of flash cycle completion package
1156 * [8:11] - CYCLE_TYPE Cycle type of flash completion
1157 * [0:7] - Reserved
1158 *
1159 * The following is flash data/
1160 */
1161 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
1162 sz_rx_payload = inst->FLASHRXBUF[0] >> 24;
1163 if (cycle_type == ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE) {
1164 volatile uint32_t *rx_buf = &inst->FLASHRXBUF[1];
1165 uint8_t *buf = pckt->buf;
1166 uint32_t data;
1167
1168 /* Get data from flash RX buffer */
1169 for (int i = 0; i < sz_rx_payload / 4; i++, rx_buf++) {
1170 data = *rx_buf;
1171 for (int j = 0; j < 4; j++, buf++) {
1172 *buf = data & 0xff;
1173 data = data >> 8;
1174 }
1175 }
1176
1177 /* Get remaining bytes */
1178 if (sz_rx_payload % 4) {
1179 data = *rx_buf;
1180 for (int j = 0; j < sz_rx_payload % 4; j++, buf++) {
1181 *buf = data & 0xff;
1182 data = data >> 8;
1183 }
1184 }
1185
1186 return 0;
1187 }
1188
1189 return -EIO;
1190 }
1191
espi_npcx_flash_read(const struct device * dev,struct espi_flash_packet * pckt)1192 static int espi_npcx_flash_read(const struct device *dev,
1193 struct espi_flash_packet *pckt)
1194 {
1195 int ret;
1196 struct espi_reg *const inst = HAL_INSTANCE(dev);
1197 struct espi_npcx_data *const data = dev->data;
1198
1199 /* Check out of FLASH received buffer size */
1200 if (pckt->len > NPCX_ESPI_FLASH_MAX_RX_PAYLOAD) {
1201 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
1202 return -EINVAL;
1203 }
1204
1205 /* Check Flash Transmit Queue is empty? */
1206 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1207 LOG_ERR("flash channel is busy");
1208 return -EBUSY;
1209 }
1210
1211 /* Prepare FLASH_READ header in tx buffer */
1212 espi_npcx_flash_prepare_tx_header(dev,
1213 ESPI_FLASH_READ_CYCLE_TYPE,
1214 pckt->flash_addr,
1215 pckt->len,
1216 0);
1217
1218 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1219 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1220
1221 /* Wait until get flash package or timeout */
1222 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1223 if (ret == -EAGAIN) {
1224 LOG_ERR("%s: Timeout", __func__);
1225 return -ETIMEDOUT;
1226 }
1227
1228 return espi_npcx_flash_parse_completion_with_data(dev, pckt);
1229 }
1230
espi_npcx_flash_write(const struct device * dev,struct espi_flash_packet * pckt)1231 static int espi_npcx_flash_write(const struct device *dev,
1232 struct espi_flash_packet *pckt)
1233 {
1234 int ret;
1235 uint32_t tx_data;
1236 struct espi_reg *const inst = HAL_INSTANCE(dev);
1237 struct espi_npcx_data *const data = dev->data;
1238 volatile uint32_t *tx_buf = &inst->FLASHTXBUF[2];
1239 uint8_t *buf = pckt->buf;
1240
1241 /* Check out of FLASH transmitted buffer size */
1242 if (pckt->len > NPCX_ESPI_FLASH_MAX_TX_PAYLOAD) {
1243 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
1244 return -EINVAL;
1245 }
1246
1247 /* Check Flash Transmit Queue is empty? */
1248 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1249 LOG_ERR("flash channel is busy");
1250 return -EBUSY;
1251 }
1252
1253 /* Prepare FLASH_WRITE header in tx buffer */
1254 espi_npcx_flash_prepare_tx_header(dev,
1255 ESPI_FLASH_WRITE_CYCLE_TYPE,
1256 pckt->flash_addr,
1257 pckt->len,
1258 pckt->len);
1259
1260 /* Put package data to flash TX buffer */
1261 for (int i = 0; i < pckt->len / 4; i++, tx_buf++) {
1262 tx_data = 0;
1263 for (int j = 0; j < 4; j++, buf++) {
1264 tx_data |= (*buf << (j * 8));
1265 }
1266 *tx_buf = tx_data;
1267 }
1268
1269 /* Put remaining bytes to flash TX buffer */
1270 if (pckt->len % 4) {
1271 tx_data = 0;
1272 for (int j = 0; j < pckt->len % 4; j++, buf++) {
1273 tx_data |= (*buf << (j * 8));
1274 }
1275 *tx_buf = tx_data;
1276 }
1277
1278 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1279 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1280
1281 /* Wait until get flash package or timeout */
1282 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1283 if (ret == -EAGAIN) {
1284 LOG_ERR("%s: Timeout", __func__);
1285 return -ETIMEDOUT;
1286 }
1287
1288 /* Parse completion package in rx buffer */
1289 return espi_npcx_flash_parse_completion(dev);
1290 }
1291
espi_npcx_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)1292 static int espi_npcx_flash_erase(const struct device *dev,
1293 struct espi_flash_packet *pckt)
1294 {
1295 int ret;
1296 struct espi_reg *const inst = HAL_INSTANCE(dev);
1297 struct espi_npcx_data *const data = dev->data;
1298
1299 /* Check Flash Transmit Queue is empty? */
1300 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1301 LOG_ERR("flash channel is busy");
1302 return -EBUSY;
1303 }
1304
1305 /* Prepare FLASH_ERASE header in tx buffer */
1306 espi_npcx_flash_prepare_tx_header(dev,
1307 ESPI_FLASH_ERASE_CYCLE_TYPE,
1308 pckt->flash_addr,
1309 pckt->len,
1310 0);
1311
1312 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1313 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1314
1315 /* Wait until get flash package or timeout */
1316 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1317 if (ret == -EAGAIN) {
1318 LOG_ERR("%s: Timeout", __func__);
1319 return -ETIMEDOUT;
1320 }
1321
1322 /* Parse completion package in rx buffer */
1323 return espi_npcx_flash_parse_completion(dev);
1324 }
1325 #endif
1326
1327 /* Platform specific espi module functions */
npcx_espi_enable_interrupts(const struct device * dev)1328 void npcx_espi_enable_interrupts(const struct device *dev)
1329 {
1330 const struct espi_npcx_config *const config = dev->config;
1331
1332 /* Enable eSPI bus interrupt */
1333 irq_enable(DT_INST_IRQN(0));
1334
1335 /* Turn on all VW inputs' MIWU interrupts */
1336 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1337 npcx_miwu_irq_enable(&(vw_in_tbl[idx].vw_wui));
1338 }
1339
1340 npcx_miwu_irq_enable(&config->espi_rst_wui);
1341 }
1342
npcx_espi_disable_interrupts(const struct device * dev)1343 void npcx_espi_disable_interrupts(const struct device *dev)
1344 {
1345 const struct espi_npcx_config *const config = dev->config;
1346
1347 /* Disable eSPI bus interrupt */
1348 irq_disable(DT_INST_IRQN(0));
1349
1350 /* Turn off all VW inputs' MIWU interrupts */
1351 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1352 npcx_miwu_irq_disable(&(vw_in_tbl[idx].vw_wui));
1353 }
1354
1355 npcx_miwu_irq_disable(&config->espi_rst_wui);
1356 }
1357
1358 /* eSPI driver registration */
1359 static int espi_npcx_init(const struct device *dev);
1360
1361 static DEVICE_API(espi, espi_npcx_driver_api) = {
1362 .config = espi_npcx_configure,
1363 .get_channel_status = espi_npcx_channel_ready,
1364 .send_vwire = espi_npcx_send_vwire,
1365 .receive_vwire = espi_npcx_receive_vwire,
1366 .manage_callback = espi_npcx_manage_callback,
1367 .read_lpc_request = espi_npcx_read_lpc_request,
1368 .write_lpc_request = espi_npcx_write_lpc_request,
1369 #if defined(CONFIG_ESPI_OOB_CHANNEL)
1370 .send_oob = espi_npcx_send_oob,
1371 .receive_oob = espi_npcx_receive_oob,
1372 #endif
1373 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1374 .flash_read = espi_npcx_flash_read,
1375 .flash_write = espi_npcx_flash_write,
1376 .flash_erase = espi_npcx_flash_erase,
1377 #endif
1378 };
1379
1380 static struct espi_npcx_data espi_npcx_data;
1381
1382 PINCTRL_DT_INST_DEFINE(0);
1383 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
1384 "only one 'nuvoton_npcx_espi' compatible node may be present");
1385
1386 static const struct espi_npcx_config espi_npcx_config = {
1387 .base = DT_INST_REG_ADDR(0),
1388 .espi_rst_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, espi_rst_wui),
1389 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
1390 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
1391 };
1392
1393 DEVICE_DT_INST_DEFINE(0, &espi_npcx_init, NULL,
1394 &espi_npcx_data, &espi_npcx_config,
1395 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1396 &espi_npcx_driver_api);
1397
espi_npcx_init(const struct device * dev)1398 static int espi_npcx_init(const struct device *dev)
1399 {
1400 const struct espi_npcx_config *const config = dev->config;
1401 struct espi_npcx_data *const data = dev->data;
1402 struct espi_reg *const inst = HAL_INSTANCE(dev);
1403 const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
1404 int i, ret;
1405
1406 if (!device_is_ready(clk_dev)) {
1407 LOG_ERR("clock control device not ready");
1408 return -ENODEV;
1409 }
1410
1411 /* Turn on eSPI device clock first */
1412 ret = clock_control_on(clk_dev, (clock_control_subsys_t)
1413 &config->clk_cfg);
1414 if (ret < 0) {
1415 LOG_ERR("Turn on eSPI clock fail %d", ret);
1416 return ret;
1417 }
1418
1419 if (IS_ENABLED(CONFIG_ESPI_NPCX_BYPASS_CH_ENABLE_FATAL_ERROR)) {
1420 /* Enable the access to the NPCX_ONLY_ESPI_REG2 register */
1421 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_UNLOCK_REG2;
1422 inst->NPCX_ONLY_ESPI_REG2 &= ~BIT(NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG);
1423 /* Disable the access to the NPCX_ONLY_ESPI_REG2 register */
1424 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_LOCK_REG2;
1425 }
1426
1427 /* Enable events which share the same espi bus interrupt */
1428 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
1429 inst->ESPIIE |= BIT(espi_bus_isr_tbl[i].int_en_bit);
1430 inst->ESPIWE |= BIT(espi_bus_isr_tbl[i].wake_en_bit);
1431 }
1432
1433 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
1434 k_sem_init(&data->oob_rx_lock, 0, 1);
1435 #endif
1436
1437 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
1438 k_sem_init(&data->flash_rx_lock, 0, 1);
1439 #endif
1440
1441 /* Configure Virtual Wire input signals */
1442 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
1443 espi_vw_config_input(dev, &vw_in_tbl[i]);
1444 }
1445
1446 /* Configure Virtual Wire output signals */
1447 for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++) {
1448 espi_vw_config_output(dev, &vw_out_tbl[i]);
1449 }
1450
1451 /* Configure Virtual Wire GPIOs that are output high at reset state */
1452 for (i = 0; i < ARRAY_SIZE(vw_out_gpio_tbl1); i++) {
1453 espi_vw_gpio_config_output(dev, &vw_out_gpio_tbl1[i], 1);
1454 }
1455
1456 /* Configure wake-up input and callback for eSPI VW input signal */
1457 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
1458 espi_init_wui_callback(dev, &vw_in_callback[i],
1459 &vw_in_tbl[i].vw_wui, espi_vw_generic_isr);
1460 }
1461
1462 /* Configure wake-up input and callback for ESPI_RST signal */
1463 espi_init_wui_callback(dev, &espi_rst_callback,
1464 &config->espi_rst_wui, espi_vw_espi_rst_isr);
1465
1466 #if DT_NODE_HAS_PROP(DT_DRV_INST(0), vw_index_extend_set)
1467 uint8_t vw_ex_len = ARRAY_SIZE(espi_npcx_vw_ex_0);
1468 uint8_t dir, num, index;
1469
1470 for (i = 0; i < vw_ex_len; i++) {
1471 dir = espi_npcx_vw_ex_0[i].direction;
1472 num = espi_npcx_vw_ex_0[i].group_num;
1473 index = espi_npcx_vw_ex_0[i].index;
1474
1475 if (dir == ESPI_CONTROLLER_TO_TARGET) {
1476 if (num >= NPCX_VWEVMS_MAX) {
1477 LOG_ERR("Error Setting for VW extend MS group (%x)", num);
1478 return -EINVAL;
1479 }
1480 SET_FIELD(inst->VWEVMS[num], NPCX_VWEVMS_INDEX, index);
1481 SET_FIELD(inst->VWEVMS[num], NPCX_VWEVMS_VALID, 0x0);
1482 inst->VWEVMS[num] |= BIT(NPCX_VWEVMS_INDEX_EN);
1483 } else if (dir == ESPI_TARGET_TO_CONTROLLER) {
1484 if (num >= NPCX_VWEVSM_MAX) {
1485 LOG_ERR("Error Setting for VW extend SM group (%x)", num);
1486 return -EINVAL;
1487 }
1488 SET_FIELD(inst->VWEVSM[num], NPCX_VWEVSM_INDEX, index);
1489 SET_FIELD(inst->VWEVSM[num], NPCX_VWEVSM_VALID, 0x0);
1490 inst->VWEVSM[num] |= BIT(NPCX_VWEVSM_INDEX_EN);
1491 } else {
1492 LOG_ERR("Error Setting for VW extend direction (%x)", dir);
1493 return -EINVAL;
1494 }
1495 }
1496 #endif
1497
1498 /* Configure pin-mux for eSPI bus device */
1499 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1500 if (ret < 0) {
1501 LOG_ERR("eSPI pinctrl setup failed (%d)", ret);
1502 return ret;
1503 }
1504
1505 /* Configure host sub-modules which HW blocks belong to core domain */
1506 npcx_host_init_subs_core_domain(dev, &data->callbacks);
1507
1508 #if defined(CONFIG_ESPI_FLASH_CHANNEL) && defined(CONFIG_ESPI_TAF)
1509 npcx_init_taf(dev, &data->callbacks);
1510 #endif
1511
1512 /* eSPI Bus interrupt installation */
1513 IRQ_CONNECT(DT_INST_IRQN(0),
1514 DT_INST_IRQ(0, priority),
1515 espi_bus_generic_isr,
1516 DEVICE_DT_INST_GET(0), 0);
1517
1518 /* Enable eSPI bus interrupt */
1519 irq_enable(DT_INST_IRQN(0));
1520
1521 return 0;
1522 }
1523
