1/* 2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <st/f4/stm32f412.dtsi> 8 9/ { 10 soc { 11 compatible = "st,stm32f413", "st,stm32f4", "simple-bus"; 12 13 uart4: serial@40004c00 { 14 compatible ="st,stm32-uart"; 15 reg = <0x40004c00 0x400>; 16 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 17 resets = <&rctl STM32_RESET(APB1, 19U)>; 18 interrupts = <52 0>; 19 status = "disabled"; 20 }; 21 22 uart5: serial@40005000 { 23 compatible = "st,stm32-uart"; 24 reg = <0x40005000 0x400>; 25 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 26 resets = <&rctl STM32_RESET(APB1, 20U)>; 27 interrupts = <53 0>; 28 status = "disabled"; 29 }; 30 31 uart7: serial@40007800 { 32 compatible = "st,stm32-uart"; 33 reg = <0x40007800 0x400>; 34 clocks = <&rcc STM32_CLOCK(APB1, 30U)>; 35 resets = <&rctl STM32_RESET(APB1, 30U)>; 36 interrupts = <82 0>; 37 status = "disabled"; 38 }; 39 40 uart8: serial@40007c00 { 41 compatible = "st,stm32-uart"; 42 reg = <0x40007c00 0x400>; 43 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 44 resets = <&rctl STM32_RESET(APB1, 31U)>; 45 interrupts = <83 0>; 46 status = "disabled"; 47 }; 48 49 uart9: serial@40011800 { 50 compatible = "st,stm32-uart"; 51 reg = <0x40011800 0x400>; 52 clocks = <&rcc STM32_CLOCK(APB2, 6U)>; 53 resets = <&rctl STM32_RESET(APB2, 6U)>; 54 interrupts = <88 0>; 55 status = "disabled"; 56 }; 57 58 uart10: serial@40011c00 { 59 compatible = "st,stm32-uart"; 60 reg = <0x40011c00 0x400>; 61 clocks = <&rcc STM32_CLOCK(APB2, 7U)>; 62 resets = <&rctl STM32_RESET(APB2, 7U)>; 63 interrupts = <89 0>; 64 status = "disabled"; 65 }; 66 67 dac1: dac@40007400 { 68 compatible = "st,stm32-dac"; 69 reg = <0x40007400 0x400>; 70 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 71 status = "disabled"; 72 #io-channel-cells = <1>; 73 }; 74 75 can3: can@40006c00 { 76 compatible = "st,stm32-bxcan"; 77 reg = <0x40006c00 0x400>; 78 interrupts = <74 0>, <75 0>, <76 0>, <77 0>; 79 interrupt-names = "TX", "RX0", "RX1", "SCE"; 80 clocks = <&rcc STM32_CLOCK(APB1, 27U)>; 81 status = "disabled"; 82 }; 83 }; 84}; 85