1 /*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rz_gpio
8
9 #include <zephyr/device.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/irq.h>
13 #include "r_ioport.h"
14 #include <zephyr/kernel.h>
15 #include <zephyr/drivers/gpio/gpio_utils.h>
16 #include "gpio_renesas_rz.h"
17 #include <zephyr/logging/log.h>
18 LOG_MODULE_REGISTER(rz_gpio, CONFIG_GPIO_LOG_LEVEL);
19
20 #define LOG_DEV_ERR(dev, format, ...) LOG_ERR("%s:" #format, (dev)->name, ##__VA_ARGS__)
21 #define LOG_DEV_DBG(dev, format, ...) LOG_DBG("%s:" #format, (dev)->name, ##__VA_ARGS__)
22
23 struct gpio_rz_config {
24 struct gpio_driver_config common;
25 uint8_t ngpios;
26 uint8_t port_num;
27 bsp_io_port_t fsp_port;
28 const ioport_cfg_t *fsp_cfg;
29 const ioport_api_t *fsp_api;
30 const struct device *int_dev;
31 uint8_t tint_num[GPIO_RZ_MAX_TINT_NUM];
32 };
33
34 struct gpio_rz_data {
35 struct gpio_driver_data common;
36 sys_slist_t cb;
37 ioport_instance_ctrl_t *fsp_ctrl;
38 struct k_spinlock lock;
39 };
40
41 struct gpio_rz_tint_isr_data {
42 const struct device *gpio_dev;
43 gpio_pin_t pin;
44 };
45
46 struct gpio_rz_tint_data {
47 struct gpio_rz_tint_isr_data tint_data[GPIO_RZ_MAX_TINT_NUM];
48 uint32_t irq_set_edge;
49 };
50
51 struct gpio_rz_tint_config {
52 void (*gpio_int_init)(void);
53 };
54
55 static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags);
56
57 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_rz_pin_get_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t * flags)58 static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
59 {
60 const struct gpio_rz_config *config = dev->config;
61 bsp_io_port_pin_t port_pin = config->fsp_port | pin;
62
63 gpio_rz_pin_config_get_raw(port_pin, flags);
64 return 0;
65 }
66 #endif
67
68 /* Get previous pin's configuration, used by pin_configure/pin_interrupt_configure api */
gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin,uint32_t * flags)69 static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags)
70 {
71 bsp_io_port_t port = (port_pin >> 8U) & 0xFF;
72 gpio_pin_t pin = port_pin & 0xFF;
73 volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_BASE_GET;
74 volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_BASE_GET;
75
76 uint8_t adr_offset;
77 uint8_t p_value;
78 uint16_t pm_value;
79
80 adr_offset = (uint8_t)GPIO_RZ_REG_OFFSET(port, pin);
81
82 p_p = &p_p[adr_offset];
83 p_pm = &p_pm[adr_offset];
84
85 p_value = GPIO_RZ_P_VALUE_GET(*p_p, pin);
86 pm_value = GPIO_RZ_PM_VALUE_GET(*p_pm, pin);
87
88 if (p_value) {
89 *flags |= GPIO_OUTPUT_INIT_HIGH;
90 } else {
91 *flags |= GPIO_OUTPUT_INIT_LOW;
92 }
93
94 *flags |= ((pm_value << 16));
95 return 0;
96 }
97
gpio_rz_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)98 static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
99 {
100 const struct gpio_rz_config *config = dev->config;
101 struct gpio_rz_data *data = dev->data;
102 bsp_io_port_pin_t port_pin = config->fsp_port | pin;
103 uint32_t ioport_config_data = 0;
104 gpio_flags_t pre_flags;
105 fsp_err_t err;
106
107 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
108
109 if (!flags) {
110 /* Disconnect mode */
111 ioport_config_data = 0;
112 } else if (!(flags & GPIO_OPEN_DRAIN)) {
113 /* PM register */
114 ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET;
115 if (flags & GPIO_INPUT) {
116 if (flags & GPIO_OUTPUT) {
117 ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT;
118 } else {
119 ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_INPUT;
120 }
121 } else if (flags & GPIO_OUTPUT) {
122 ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET;
123 ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT;
124 }
125 /* P register */
126 if (!(flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW))) {
127 flags |= pre_flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW);
128 }
129
130 if (flags & GPIO_OUTPUT_INIT_HIGH) {
131 ioport_config_data |= IOPORT_CFG_PORT_OUTPUT_HIGH;
132 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
133 ioport_config_data &= ~(IOPORT_CFG_PORT_OUTPUT_HIGH);
134 }
135 /* PUPD register */
136 if (flags & GPIO_PULL_UP) {
137 ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE;
138 } else if (flags & GPIO_PULL_DOWN) {
139 ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE;
140 }
141
142 /* ISEL register */
143 if (flags & GPIO_INT_ENABLE) {
144 ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_INT_ENABLE;
145 } else if (flags & GPIO_INT_DISABLE) {
146 ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INT_DISABLE;
147 }
148
149 /* Drive Ability register */
150 ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flags);
151
152 /* Filter register, see in renesas-rz-gpio-ioport.h */
153 ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flags);
154 } else {
155 return -ENOTSUP;
156 }
157
158 err = config->fsp_api->pinCfg(data->fsp_ctrl, port_pin, ioport_config_data);
159 if (err != FSP_SUCCESS) {
160 return -EIO;
161 }
162 return 0;
163 }
164
gpio_rz_port_get_raw(const struct device * dev,gpio_port_value_t * value)165 static int gpio_rz_port_get_raw(const struct device *dev, gpio_port_value_t *value)
166 {
167 const struct gpio_rz_config *config = dev->config;
168 struct gpio_rz_data *data = dev->data;
169 fsp_err_t err;
170 ioport_size_t port_value;
171
172 err = config->fsp_api->portRead(data->fsp_ctrl, config->fsp_port, &port_value);
173 if (err != FSP_SUCCESS) {
174 return -EIO;
175 }
176 *value = (gpio_port_value_t)port_value;
177 return 0;
178 }
179
gpio_rz_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)180 static int gpio_rz_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
181 gpio_port_value_t value)
182 {
183 const struct gpio_rz_config *config = dev->config;
184 struct gpio_rz_data *data = dev->data;
185 ioport_size_t port_mask = (ioport_size_t)mask;
186 ioport_size_t port_value = (ioport_size_t)value;
187 fsp_err_t err;
188
189 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, port_value, port_mask);
190 if (err != FSP_SUCCESS) {
191 return -EIO;
192 }
193 return 0;
194 }
195
gpio_rz_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)196 static int gpio_rz_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
197 {
198 const struct gpio_rz_config *config = dev->config;
199 struct gpio_rz_data *data = dev->data;
200 ioport_size_t mask = (ioport_size_t)pins;
201 ioport_size_t value = (ioport_size_t)pins;
202 fsp_err_t err;
203
204 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask);
205 if (err != FSP_SUCCESS) {
206 return -EIO;
207 }
208 return 0;
209 }
210
gpio_rz_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)211 static int gpio_rz_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
212 {
213 const struct gpio_rz_config *config = dev->config;
214 struct gpio_rz_data *data = dev->data;
215 ioport_size_t mask = (ioport_size_t)pins;
216 ioport_size_t value = 0x00;
217 fsp_err_t err;
218
219 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask);
220 if (err != FSP_SUCCESS) {
221 return -EIO;
222 }
223 return 0;
224 }
225
gpio_rz_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)226 static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
227 {
228 const struct gpio_rz_config *config = dev->config;
229 struct gpio_rz_data *data = dev->data;
230 bsp_io_port_pin_t port_pin;
231 gpio_flags_t pre_flags;
232 ioport_size_t value = 0;
233 fsp_err_t err;
234
235 for (uint8_t idx = 0; idx < config->ngpios; idx++) {
236 if (pins & (1U << idx)) {
237 port_pin = config->fsp_port | idx;
238 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
239 if (pre_flags & GPIO_OUTPUT_INIT_HIGH) {
240 value &= (1U << idx);
241 } else if (pre_flags & GPIO_OUTPUT_INIT_LOW) {
242 value |= (1U << idx);
243 }
244 }
245 }
246 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value,
247 (ioport_size_t)pins);
248 if (err != FSP_SUCCESS) {
249 return -EIO;
250 }
251 return 0;
252 }
253
254 #define GPIO_RZ_HAS_INTERRUPT DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int)
255
256 #if GPIO_RZ_HAS_INTERRUPT
gpio_rz_int_disable(const struct device * dev,uint8_t tint_num)257 static int gpio_rz_int_disable(const struct device *dev, uint8_t tint_num)
258 {
259 struct gpio_rz_tint_data *data = dev->data;
260 volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
261 volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
262 volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
263
264 /* Get register offset base on interrupt number. */
265 tssr = &tssr[tint_num / 4];
266 titsr = &titsr[tint_num / 16];
267
268 irq_disable(GPIO_RZ_TINT_IRQ_GET(tint_num));
269 /* Disable interrupt and clear interrupt source. */
270 *tssr &= ~(0xFF << GPIO_RZ_TSSR_OFFSET(tint_num));
271 /* Reset interrupt dectect type to default. */
272 *titsr &= ~(0x3 << GPIO_RZ_TITSR_OFFSET(tint_num));
273
274 /* Clear interrupt detection status. */
275 if (data->irq_set_edge & BIT(tint_num)) {
276 *tscr &= ~BIT(tint_num);
277 data->irq_set_edge &= ~BIT(tint_num);
278 }
279 data->tint_data[tint_num].gpio_dev = NULL;
280 data->tint_data[tint_num].pin = UINT8_MAX;
281
282 return 0;
283 }
284
gpio_rz_int_enable(const struct device * int_dev,const struct device * gpio_dev,uint8_t tint_num,uint8_t irq_type,gpio_pin_t pin)285 static int gpio_rz_int_enable(const struct device *int_dev, const struct device *gpio_dev,
286 uint8_t tint_num, uint8_t irq_type, gpio_pin_t pin)
287 {
288 struct gpio_rz_tint_data *int_data = int_dev->data;
289 const struct gpio_rz_config *gpio_config = gpio_dev->config;
290 volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
291 volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
292
293 tssr = &tssr[tint_num / 4];
294 titsr = &titsr[tint_num / 16];
295 /* Select interrupt detect type. */
296 *titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(tint_num));
297 /* Select interrupt source base on port and pin number.*/
298 *tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(tint_num);
299
300 if (irq_type == GPIO_RZ_TINT_EDGE_RISING || irq_type == GPIO_RZ_TINT_EDGE_FALLING) {
301 int_data->irq_set_edge |= BIT(tint_num);
302 /* Clear interrupt status. */
303 R_INTC_IM33->TSCR &= ~BIT(tint_num);
304 }
305 int_data->tint_data[tint_num].gpio_dev = gpio_dev;
306 int_data->tint_data[tint_num].pin = pin;
307 irq_enable(GPIO_RZ_TINT_IRQ_GET(tint_num));
308
309 return 0;
310 }
311
gpio_rz_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)312 static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
313 enum gpio_int_mode mode, enum gpio_int_trig trig)
314 {
315 const struct gpio_rz_config *config = dev->config;
316 struct gpio_rz_data *data = dev->data;
317 bsp_io_port_pin_t port_pin = config->fsp_port | pin;
318 uint8_t tint_num = config->tint_num[pin];
319 uint8_t irq_type = 0;
320 gpio_flags_t pre_flags = 0;
321 k_spinlock_key_t key;
322
323 if (tint_num >= GPIO_RZ_MAX_TINT_NUM) {
324 LOG_DEV_ERR(dev, "Invalid TINT interrupt:%d >= %d", tint_num, GPIO_RZ_MAX_TINT_NUM);
325 }
326
327 if (pin > config->ngpios) {
328 return -EINVAL;
329 }
330
331 if (trig == GPIO_INT_TRIG_BOTH) {
332 return -ENOTSUP;
333 }
334
335 key = k_spin_lock(&data->lock);
336
337 if (mode == GPIO_INT_MODE_DISABLED) {
338 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
339 pre_flags |= GPIO_INT_DISABLE;
340 gpio_rz_pin_configure(dev, pin, pre_flags);
341 gpio_rz_int_disable(config->int_dev, tint_num);
342 goto exit_unlock;
343 }
344
345 if (mode == GPIO_INT_MODE_EDGE) {
346 irq_type = GPIO_RZ_TINT_EDGE_RISING;
347 if (trig == GPIO_INT_TRIG_LOW) {
348 irq_type = GPIO_RZ_TINT_EDGE_FALLING;
349 }
350 } else {
351 irq_type = GPIO_RZ_TINT_LEVEL_HIGH;
352 if (trig == GPIO_INT_TRIG_LOW) {
353 irq_type = GPIO_RZ_TINT_LEVEL_LOW;
354 }
355 }
356
357 /* Set register ISEL */
358 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
359 pre_flags |= GPIO_INT_ENABLE;
360 gpio_rz_pin_configure(dev, pin, pre_flags);
361 gpio_rz_int_enable(config->int_dev, dev, tint_num, irq_type, pin);
362
363 exit_unlock:
364 k_spin_unlock(&data->lock, key);
365 return 0;
366 }
367
gpio_rz_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)368 static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callback *callback,
369 bool set)
370 {
371 struct gpio_rz_data *data = dev->data;
372
373 return gpio_manage_callback(&data->cb, callback, set);
374 }
375
gpio_rz_isr(const struct device * dev,uint8_t pin)376 static void gpio_rz_isr(const struct device *dev, uint8_t pin)
377 {
378 struct gpio_rz_data *data = dev->data;
379
380 gpio_fire_callbacks(&data->cb, dev, BIT(pin));
381 }
382
gpio_rz_tint_isr(uint16_t irq,const struct device * dev)383 static void gpio_rz_tint_isr(uint16_t irq, const struct device *dev)
384 {
385 struct gpio_rz_tint_data *data = dev->data;
386 volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
387 uint8_t tint_num;
388
389 tint_num = irq - GPIO_RZ_TINT_IRQ_OFFSET;
390
391 if (!(*tscr & BIT(tint_num))) {
392 LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", tint_num);
393 return;
394 }
395
396 if (data->irq_set_edge & BIT(tint_num)) {
397 *tscr &= ~BIT(tint_num);
398 }
399
400 gpio_rz_isr(data->tint_data[tint_num].gpio_dev, data->tint_data[tint_num].pin);
401 }
402
gpio_rz_int_init(const struct device * dev)403 static int gpio_rz_int_init(const struct device *dev)
404 {
405 const struct gpio_rz_tint_config *config = dev->config;
406
407 config->gpio_int_init();
408 return 0;
409 }
410 #endif
411
412 static DEVICE_API(gpio, gpio_rz_driver_api) = {
413 .pin_configure = gpio_rz_pin_configure,
414 #ifdef CONFIG_GPIO_GET_CONFIG
415 .pin_get_config = gpio_rz_pin_get_config,
416 #endif
417 .port_get_raw = gpio_rz_port_get_raw,
418 .port_set_masked_raw = gpio_rz_port_set_masked_raw,
419 .port_set_bits_raw = gpio_rz_port_set_bits_raw,
420 .port_clear_bits_raw = gpio_rz_port_clear_bits_raw,
421 .port_toggle_bits = gpio_rz_port_toggle_bits,
422 #if GPIO_RZ_HAS_INTERRUPT
423 .pin_interrupt_configure = gpio_rz_pin_interrupt_configure,
424 .manage_callback = gpio_rz_manage_callback,
425 #endif
426 };
427
428 /*Initialize GPIO interrupt device*/
429 #define GPIO_RZ_TINT_ISR_DECLARE(irq_num, node_id) \
430 static void rz_gpio_isr_##irq_num(void *param) \
431 { \
432 gpio_rz_tint_isr(DT_IRQ_BY_IDX(node_id, irq_num, irq), param); \
433 }
434
435 #define GPIO_RZ_TINT_ISR_INIT(node_id, irq_num) LISTIFY(irq_num, \
436 GPIO_RZ_TINT_ISR_DECLARE, (), node_id)
437
438 #define GPIO_RZ_TINT_CONNECT(irq_num, node_id) \
439 IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, irq_num, irq), \
440 DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr_##irq_num, \
441 DEVICE_DT_GET(node_id), 0);
442
443 #define GPIO_RZ_TINT_CONNECT_FUNC(node_id) \
444 static void rz_gpio_tint_connect_func##node_id(void) \
445 { \
446 LISTIFY(DT_NUM_IRQS(node_id), \
447 GPIO_RZ_TINT_CONNECT, (;), \
448 node_id) \
449 }
450 /* Initialize GPIO device*/
451 #define GPIO_RZ_INT_INIT(node_id) \
452 GPIO_RZ_TINT_ISR_INIT(node_id, DT_NUM_IRQS(node_id)) \
453 GPIO_RZ_TINT_CONNECT_FUNC(node_id) \
454 static const struct gpio_rz_tint_config rz_gpio_tint_cfg_##node_id = { \
455 .gpio_int_init = rz_gpio_tint_connect_func##node_id, \
456 }; \
457 static struct gpio_rz_tint_data rz_gpio_tint_data_##node_id = {}; \
458 DEVICE_DT_DEFINE(node_id, gpio_rz_int_init, NULL, &rz_gpio_tint_data_##node_id, \
459 &rz_gpio_tint_cfg_##node_id, POST_KERNEL, \
460 UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL);
461
462 DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
463
464 #define VALUE_2X(i, _) UTIL_X2(i)
465 #define PIN_IRQ_GET(idx, inst) \
466 COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \
467 ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \
468 DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx)),), \
469 ())
470
471 #define PIN_IRQS_GET(inst) \
472 FOR_EACH_FIXED_ARG(PIN_IRQ_GET, (), inst, \
473 LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
474
475 #define RZG_GPIO_PORT_INIT(inst) \
476 static ioport_cfg_t g_ioport_##inst##_cfg = { \
477 .number_of_pins = 0, \
478 .p_pin_cfg_data = NULL, \
479 .p_extend = NULL, \
480 }; \
481 static const struct gpio_rz_config gpio_rz_##inst##_config = { \
482 .common = \
483 { \
484 .port_pin_mask = \
485 (gpio_port_pins_t)GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
486 }, \
487 .fsp_port = (uint32_t)DT_INST_REG_ADDR(inst), \
488 .port_num = (uint8_t)DT_NODE_CHILD_IDX(DT_DRV_INST(inst)), \
489 .ngpios = (uint8_t)DT_INST_PROP(inst, ngpios), \
490 .fsp_cfg = &g_ioport_##inst##_cfg, \
491 .fsp_api = &g_ioport_on_ioport, \
492 .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int)), \
493 .tint_num = {PIN_IRQS_GET(inst)}, \
494 }; \
495 static ioport_instance_ctrl_t g_ioport_##inst##_ctrl; \
496 static struct gpio_rz_data gpio_rz_##inst##_data = { \
497 .fsp_ctrl = &g_ioport_##inst##_ctrl, \
498 }; \
499 DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &gpio_rz_##inst##_data, &gpio_rz_##inst##_config, \
500 POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rz_driver_api);
501
502 DT_INST_FOREACH_STATUS_OKAY(RZG_GPIO_PORT_INIT)
503
