1 /*
2 * Copyright (c) 2018-2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT intel_gpio
8
9 /**
10 * @file
11 * @brief Intel GPIO Controller Driver
12 *
13 * The GPIO controller on Intel SoC serves
14 * both GPIOs and Pinmuxing function. This driver provides
15 * the GPIO function.
16 *
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
19 * we export GPIO_INTEL_NR_SUBDEVS devices to the kernel.
20 */
21
22 #include <errno.h>
23 #include <zephyr/drivers/gpio.h>
24 #include <soc.h>
25 #include <zephyr/sys/sys_io.h>
26 #include <zephyr/sys/__assert.h>
27 #include <zephyr/sys/slist.h>
28 #include <zephyr/sys/speculation.h>
29 #include <zephyr/irq.h>
30 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
31 #include <zephyr/acpi/acpi.h>
32 #include <zephyr/drivers/gpio/gpio_utils.h>
33
34 #define REG_MISCCFG 0x0010
35 #define MISCCFG_IRQ_ROUTE_POS 3
36
37 #define PAD_OWN_MASK 0x03
38 #define PAD_OWN_HOST 0
39 #define PAD_OWN_CSME 1
40 #define PAD_OWN_ISH 2
41 #define PAD_OWN_IE 3
42
43 #define PAD_HOST_SW_OWN_GPIO 1
44 #define PAD_HOST_SW_OWN_ACPI 0
45
46
47 #define PAD_CFG0_RXPADSTSEL BIT(29)
48 #define PAD_CFG0_RXRAW1 BIT(28)
49
50
51 #define PAD_CFG0_RXEVCFG_POS 25
52 #define PAD_CFG0_RXEVCFG_MASK (0x03 << PAD_CFG0_RXEVCFG_POS)
53 #define PAD_CFG0_RXEVCFG_LEVEL (0 << PAD_CFG0_RXEVCFG_POS)
54 #define PAD_CFG0_RXEVCFG_EDGE (1 << PAD_CFG0_RXEVCFG_POS)
55 #define PAD_CFG0_RXEVCFG_DRIVE0 (2 << PAD_CFG0_RXEVCFG_POS)
56
57 #define PAD_CFG0_PREGFRXSEL BIT(24)
58 #define PAD_CFG0_RXINV BIT(23)
59
60 #define PAD_CFG0_RXDIS BIT(9)
61 #define PAD_CFG0_TXDIS BIT(8)
62 #define PAD_CFG0_RXSTATE BIT(1)
63 #define PAD_CFG0_RXSTATE_POS 1
64 #define PAD_CFG0_TXSTATE BIT(0)
65 #define PAD_CFG0_TXSTATE_POS 0
66
67 #define PAD_CFG1_IOSTERM_POS 8
68 #define PAD_CFG1_IOSTERM_MASK (0x03 << PAD_CFG1_IOSTERM_POS)
69 #define PAD_CFG1_IOSTERM_FUNC (0 << PAD_CFG1_IOSTERM_POS)
70 #define PAD_CFG1_IOSTERM_DISPUD (1 << PAD_CFG1_IOSTERM_POS)
71 #define PAD_CFG1_IOSTERM_PU (2 << PAD_CFG1_IOSTERM_POS)
72 #define PAD_CFG1_IOSTERM_PD (3 << PAD_CFG1_IOSTERM_POS)
73
74 #define PAD_CFG1_TERM_POS 10
75 #define PAD_CFG1_TERM_MASK (0x0F << PAD_CFG1_TERM_POS)
76 #define PAD_CFG1_TERM_NONE (0x00 << PAD_CFG1_TERM_POS)
77 #define PAD_CFG1_TERM_PD_5K (0x02 << PAD_CFG1_TERM_POS)
78 #define PAD_CFG1_TERM_PD_20K (0x04 << PAD_CFG1_TERM_POS)
79 #define PAD_CFG1_TERM_NONE2 (0x08 << PAD_CFG1_TERM_POS)
80 #define PAD_CFG1_TERM_PU_1K (0x09 << PAD_CFG1_TERM_POS)
81 #define PAD_CFG1_TERM_PU_5K (0x0A << PAD_CFG1_TERM_POS)
82 #define PAD_CFG1_TERM_PU_2K (0x0B << PAD_CFG1_TERM_POS)
83 #define PAD_CFG1_TERM_PU_20K (0x0C << PAD_CFG1_TERM_POS)
84 #define PAD_CFG1_TERM_PU_1K_2K (0x0D << PAD_CFG1_TERM_POS)
85
86 #define PAD_CFG1_IOSSTATE_POS 14
87 #define PAD_CFG1_IOSSTATE_MASK (0x0F << PAD_CFG1_IOSSTATE_POS)
88 #define PAD_CFG1_IOSSTATE_IGNORE (0x0F << PAD_CFG1_IOSSTATE_POS)
89
90 /* Required by DEVICE_MMIO_NAMED_* macros */
91 #define DEV_CFG(_dev) \
92 ((const struct gpio_intel_config *)(_dev)->config)
93 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
94
95 struct gpio_intel_config {
96 /* gpio_driver_config needs to be first */
97 struct gpio_driver_config common;
98
99 DEVICE_MMIO_NAMED_ROM(reg_base);
100
101 #if !DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
102 uint8_t pin_offset;
103 uint8_t group_index;
104 uint8_t num_pins;
105 #endif
106 };
107
108 struct gpio_intel_data {
109 /* gpio_driver_data needs to be first */
110 struct gpio_driver_data common;
111
112 DEVICE_MMIO_NAMED_RAM(reg_base);
113
114 /* Pad base address */
115 uint32_t pad_base;
116
117 sys_slist_t cb;
118 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
119 uint32_t num_pins;
120 uint32_t pad_owner_reg;
121 uint32_t host_owner_reg;
122 uint32_t intr_stat_reg;
123 uint32_t base_num;
124 #endif
125 };
126
127 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
128 #define GPIO_REG_BASE_GET(dev) DEVICE_MMIO_NAMED_GET(dev, reg_base)
129
130 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
131
132 #define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
133
134 #define PIN_OFFSET_GET(dev) (0)
135
136 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
137
138 #define REG_PAD_HOST_SW_OWNER_GET(data) (data)->host_owner_reg
139
140 #define GPIO_BASE_GET(cdf) (0)
141
142 #define GPIO_INTERRUPT_BASE_GET(cfg) (0)
143
144 #define GPIO_GET_PIN_MAX(dev) ((struct gpio_intel_data *)(dev)->data)->num_pins
145 #else /* Non-ACPI */
146 #define GPIO_REG_BASE_GET(dev) GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base))
147
148 #define REG_GPI_INT_STS_BASE_GET(data) REG_GPI_INT_STS_BASE
149
150 #define REG_GPI_INT_EN_BASE_GET(data) REG_GPI_INT_EN_BASE
151
152 #define PIN_OFFSET_GET(dev) ((const struct gpio_intel_config *)(dev)->config)->pin_offset
153
154 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) GPIO_PAD_OWNERSHIP(pin, offset)
155
156 #define REG_PAD_HOST_SW_OWNER_GET(data) REG_PAD_HOST_SW_OWNER
157
158 #define GPIO_BASE_GET(cdf) GPIO_BASE(((const struct gpio_intel_config *)(dev)->config))
159
160 #define GPIO_INTERRUPT_BASE_GET(cfg) GPIO_INTERRUPT_BASE(cfg)
161
162 #define GPIO_GET_PIN_MAX(dev) ((const struct gpio_intel_config *)(dev)->config)->num_pins
163 #endif
164
regs(const struct device * dev)165 static inline mm_reg_t regs(const struct device *dev)
166 {
167 return GPIO_REG_BASE_GET(dev);
168 }
169
170 #if !DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
pad_base(const struct device * dev)171 static inline mm_reg_t pad_base(const struct device *dev)
172 {
173 return GPIO_PAD_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base));
174 }
175 #endif
176
177 #ifdef CONFIG_GPIO_INTEL_CHECK_PERMS
178 /**
179 * @brief Check if host has permission to alter this GPIO pin.
180 *
181 * @param "struct device *dev" Device struct
182 * @param "uint32_t raw_pin" Raw GPIO pin
183 *
184 * @return true if host owns the GPIO pin, false otherwise
185 */
check_perm(const struct device * dev,uint32_t raw_pin)186 static bool check_perm(const struct device *dev, uint32_t raw_pin)
187 {
188 struct gpio_intel_data *data = dev->data;
189 uint32_t offset, val, pin_offset;
190
191 pin_offset = PIN_OFFSET_GET(dev);
192 /* First is to establish that host software owns the pin */
193
194 /* read the Pad Ownership register related to the pin */
195 offset = GPIO_PAD_OWNERSHIP_GET(data, raw_pin, pin_offset);
196
197 val = sys_read32(regs(dev) + offset);
198
199 /* get the bits about ownership */
200 offset = GPIO_OWNERSHIP_BIT(raw_pin);
201 val = (val >> offset) & PAD_OWN_MASK;
202 if (val) {
203 /* PAD_OWN_HOST == 0, so !0 => false*/
204 return false;
205 }
206
207 /* Also need to make sure the function of pad is GPIO */
208 offset = data->pad_base + (raw_pin << 4);
209 val = sys_read32(regs(dev) + offset);
210 if (val & PAD_CFG0_PMODE_MASK) {
211 /* mode is not zero => not functioning as GPIO */
212 return false;
213 }
214
215 return true;
216 }
217 #else
218 #define check_perm(...) (1)
219 #endif
220
221 /*
222 * as the kernel initializes the subdevices, we add them
223 * to the list of devices to check at ISR time.
224 */
225
226 static bool first_inst = true;
227
gpio_intel_isr(const struct device * dev)228 static void gpio_intel_isr(const struct device *dev)
229 {
230 const struct gpio_intel_config *cfg;
231 struct gpio_intel_data *data;
232 struct gpio_callback *cb, *tmp;
233 uint32_t reg, int_sts, cur_mask, acc_mask;
234
235 cfg = dev->config;
236 data = dev->data;
237
238 reg = regs(dev) + REG_GPI_INT_STS_BASE_GET(data) + GPIO_INTERRUPT_BASE_GET(cfg);
239 int_sts = sys_read32(reg);
240 acc_mask = 0U;
241
242 SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {
243 cur_mask = int_sts & cb->pin_mask;
244 acc_mask |= cur_mask;
245 if (cur_mask) {
246 __ASSERT(cb->handler, "No callback handler!");
247 cb->handler(dev, cb, cur_mask);
248 }
249 }
250
251 /* clear handled interrupt bits */
252 sys_write32(acc_mask, reg);
253 }
254
gpio_intel_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)255 static int gpio_intel_config(const struct device *dev,
256 gpio_pin_t pin, gpio_flags_t flags)
257 {
258 struct gpio_intel_data *data = dev->data;
259 uint32_t raw_pin, reg, cfg0, cfg1;
260
261 /* Only support push-pull mode */
262 if ((flags & GPIO_SINGLE_ENDED) != 0U) {
263 return -ENOTSUP;
264 }
265
266 pin = k_array_index_sanitize(pin, GPIO_GET_PIN_MAX(dev) + 1);
267
268 raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
269
270 if (!check_perm(dev, raw_pin)) {
271 return -EINVAL;
272 }
273
274 /* read in pad configuration register */
275 reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
276 cfg0 = sys_read32(reg);
277 cfg1 = sys_read32(reg + 4);
278
279 /* don't override RX to 1 */
280 cfg0 &= ~(PAD_CFG0_RXRAW1);
281
282 /* set input/output */
283 if ((flags & GPIO_INPUT) != 0U) {
284 /* clear RX disable bit */
285 cfg0 &= ~PAD_CFG0_RXDIS;
286 } else {
287 /* set RX disable bit */
288 cfg0 |= PAD_CFG0_RXDIS;
289 }
290
291 if ((flags & GPIO_OUTPUT) != 0U) {
292 /* pin to output */
293
294 /* set pin output if desired */
295 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
296 cfg0 |= PAD_CFG0_TXSTATE;
297 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
298 cfg0 &= ~PAD_CFG0_TXSTATE;
299 }
300
301 /* clear TX disable bit */
302 cfg0 &= ~PAD_CFG0_TXDIS;
303 } else {
304 /* set TX disable bit */
305 cfg0 |= PAD_CFG0_TXDIS;
306 }
307
308 /* pull-up or pull-down */
309 cfg1 &= ~(PAD_CFG1_TERM_MASK | PAD_CFG1_IOSTERM_MASK);
310 if ((flags & GPIO_PULL_UP) != 0U) {
311 cfg1 |= (PAD_CFG1_TERM_PU_20K | PAD_CFG1_IOSTERM_PU);
312 } else if ((flags & GPIO_PULL_DOWN) != 0U) {
313 cfg1 |= (PAD_CFG1_TERM_PD_20K | PAD_CFG1_IOSTERM_PD);
314 } else {
315 cfg1 |= (PAD_CFG1_TERM_NONE | PAD_CFG1_IOSTERM_FUNC);
316 }
317
318 /* IO Standby state to TX,RX enabled */
319 cfg1 &= ~PAD_CFG1_IOSSTATE_MASK;
320
321 /* write back pad configuration register after all changes */
322 sys_write32(cfg0, reg);
323 sys_write32(cfg1, reg + 4);
324
325 return 0;
326 }
327
gpio_intel_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)328 static int gpio_intel_pin_interrupt_configure(const struct device *dev,
329 gpio_pin_t pin,
330 enum gpio_int_mode mode,
331 enum gpio_int_trig trig)
332 {
333 struct gpio_intel_data *data = dev->data;
334 uint32_t raw_pin, cfg0, cfg1;
335 uint32_t reg, reg_en, reg_sts;
336
337 /* no double-edge triggering according to data sheet */
338 if (trig == GPIO_INT_TRIG_BOTH) {
339 return -ENOTSUP;
340 }
341
342 pin = k_array_index_sanitize(pin, GPIO_GET_PIN_MAX(dev) + 1);
343
344 raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
345
346 if (!check_perm(dev, raw_pin)) {
347 return -EINVAL;
348 }
349
350 /* set owner to GPIO driver mode for legacy interrupt mode */
351 reg = regs(dev) + REG_PAD_HOST_SW_OWNER_GET(data) + GPIO_BASE_GET(dev);
352
353 sys_bitfield_set_bit(reg, raw_pin);
354
355 /* read in pad configuration register */
356 reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
357
358 cfg0 = sys_read32(reg);
359 cfg1 = sys_read32(reg + 4);
360
361 reg_en = regs(dev) + REG_GPI_INT_EN_BASE_GET(data) + GPIO_BASE_GET(dev);
362
363 /* disable interrupt bit first before setup */
364 sys_bitfield_clear_bit(reg_en, raw_pin);
365
366 /* clear (by setting) interrupt status bit */
367 reg_sts = regs(dev) + REG_GPI_INT_STS_BASE_GET(data) + GPIO_BASE_GET(dev);
368 sys_bitfield_set_bit(reg_sts, raw_pin);
369
370 /* clear level/edge configuration bits */
371 cfg0 &= ~PAD_CFG0_RXEVCFG_MASK;
372
373 if (mode == GPIO_INT_MODE_DISABLED) {
374 /* set RX conf to drive 0 */
375 cfg0 |= PAD_CFG0_RXEVCFG_DRIVE0;
376 } else {
377 /* cannot enable interrupt without pin as input */
378 if ((cfg0 & PAD_CFG0_RXDIS) != 0U) {
379 return -ENOTSUP;
380 }
381
382 /*
383 * Do not enable interrupt with pin as output.
384 * Hardware does not seem to support triggering
385 * interrupt by setting line as both input/output
386 * and then setting output to desired level.
387 * So just say not supported.
388 */
389 if ((cfg0 & PAD_CFG0_TXDIS) == 0U) {
390 return -ENOTSUP;
391 }
392
393 if (mode == GPIO_INT_MODE_LEVEL) {
394 /* level trigger */
395 cfg0 |= PAD_CFG0_RXEVCFG_LEVEL;
396 } else {
397 /* edge trigger */
398 cfg0 |= PAD_CFG0_RXEVCFG_EDGE;
399 }
400
401 /* invert pin for active low triggering */
402 if (trig == GPIO_INT_TRIG_LOW) {
403 cfg0 |= PAD_CFG0_RXINV;
404 } else {
405 cfg0 &= ~PAD_CFG0_RXINV;
406 }
407 }
408
409 /* write back pad configuration register after all changes */
410 sys_write32(cfg0, reg);
411 sys_write32(cfg1, reg + 4);
412
413 if (mode != GPIO_INT_MODE_DISABLED) {
414 /* enable interrupt bit */
415 sys_bitfield_set_bit(reg_en, raw_pin);
416 }
417
418 return 0;
419 }
420
gpio_intel_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)421 static int gpio_intel_manage_callback(const struct device *dev,
422 struct gpio_callback *callback,
423 bool set)
424 {
425 struct gpio_intel_data *data = dev->data;
426
427 return gpio_manage_callback(&data->cb, callback, set);
428 }
429
port_get_raw(const struct device * dev,uint32_t mask,uint32_t * value,bool read_tx)430 static int port_get_raw(const struct device *dev, uint32_t mask,
431 uint32_t *value,
432 bool read_tx)
433 {
434 struct gpio_intel_data *data = dev->data;
435 uint32_t pin, raw_pin, reg_addr, reg_val, cmp;
436
437 if (read_tx) {
438 cmp = PAD_CFG0_TXSTATE;
439 } else {
440 cmp = PAD_CFG0_RXSTATE;
441 }
442
443 *value = 0;
444 while (mask != 0U) {
445 pin = find_lsb_set(mask) - 1;
446
447 if (pin >= GPIO_GET_PIN_MAX(dev)) {
448 break;
449 }
450
451 mask &= ~BIT(pin);
452
453 raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
454
455 if (!check_perm(dev, raw_pin)) {
456 continue;
457 }
458
459 reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
460 reg_val = sys_read32(reg_addr);
461
462 if ((reg_val & cmp) != 0U) {
463 *value |= BIT(pin);
464 }
465 }
466
467 return 0;
468 }
469
port_set_raw(const struct device * dev,uint32_t mask,uint32_t value)470 static int port_set_raw(const struct device *dev, uint32_t mask,
471 uint32_t value)
472 {
473 struct gpio_intel_data *data = dev->data;
474 uint32_t pin, raw_pin, reg_addr, reg_val;
475
476 while (mask != 0) {
477 pin = find_lsb_set(mask) - 1;
478
479 if (pin >= GPIO_GET_PIN_MAX(dev)) {
480 break;
481 }
482
483 mask &= ~BIT(pin);
484
485 raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
486
487 if (!check_perm(dev, raw_pin)) {
488 continue;
489 }
490
491 reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
492 reg_val = sys_read32(reg_addr);
493
494 if ((value & BIT(pin)) != 0) {
495 reg_val |= PAD_CFG0_TXSTATE;
496 } else {
497 reg_val &= ~PAD_CFG0_TXSTATE;
498 }
499
500 sys_write32(reg_val, reg_addr);
501 }
502
503 return 0;
504 }
505
gpio_intel_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)506 static int gpio_intel_port_set_masked_raw(const struct device *dev,
507 uint32_t mask,
508 uint32_t value)
509 {
510 uint32_t port_val;
511
512 port_get_raw(dev, mask, &port_val, true);
513
514 port_val = (port_val & ~mask) | (mask & value);
515
516 port_set_raw(dev, mask, port_val);
517
518 return 0;
519 }
520
gpio_intel_port_set_bits_raw(const struct device * dev,uint32_t mask)521 static int gpio_intel_port_set_bits_raw(const struct device *dev,
522 uint32_t mask)
523 {
524 return gpio_intel_port_set_masked_raw(dev, mask, mask);
525 }
526
gpio_intel_port_clear_bits_raw(const struct device * dev,uint32_t mask)527 static int gpio_intel_port_clear_bits_raw(const struct device *dev,
528 uint32_t mask)
529 {
530 return gpio_intel_port_set_masked_raw(dev, mask, 0);
531 }
532
gpio_intel_port_toggle_bits(const struct device * dev,uint32_t mask)533 static int gpio_intel_port_toggle_bits(const struct device *dev,
534 uint32_t mask)
535 {
536 uint32_t port_val;
537
538 port_get_raw(dev, mask, &port_val, true);
539
540 port_val ^= mask;
541
542 port_set_raw(dev, mask, port_val);
543
544 return 0;
545 }
546
gpio_intel_port_get_raw(const struct device * dev,uint32_t * value)547 static int gpio_intel_port_get_raw(const struct device *dev,
548 uint32_t *value)
549 {
550 return port_get_raw(dev, 0xFFFFFFFF, value, false);
551 }
552
553 static const struct gpio_driver_api gpio_intel_api = {
554 .pin_configure = gpio_intel_config,
555 .manage_callback = gpio_intel_manage_callback,
556 .port_get_raw = gpio_intel_port_get_raw,
557 .port_set_masked_raw = gpio_intel_port_set_masked_raw,
558 .port_set_bits_raw = gpio_intel_port_set_bits_raw,
559 .port_clear_bits_raw = gpio_intel_port_clear_bits_raw,
560 .port_toggle_bits = gpio_intel_port_toggle_bits,
561 .pin_interrupt_configure = gpio_intel_pin_interrupt_configure,
562 };
563
564 /* We need support either DTS or ACPI base resource enumeration at time.*/
565 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
566
gpio_intel_acpi_enum(const struct device * dev,int bank_idx,char * hid,char * uid)567 static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hid, char *uid)
568 {
569 int ret;
570 struct gpio_acpi_res res;
571 struct gpio_intel_data *data = dev->data;
572
573 ret = soc_acpi_gpio_resource_get(bank_idx, hid, uid, &res);
574 if (ret) {
575 return ret;
576 }
577
578 device_map(&data->reg_base, res.reg_base, res.len, K_MEM_CACHE_NONE);
579
580 data->num_pins = res.num_pins;
581 data->pad_owner_reg = res.pad_owner_reg;
582 data->host_owner_reg = res.host_owner_reg;
583 data->intr_stat_reg = res.intr_stat_reg;
584 data->base_num = res.base_num;
585 data->pad_base = res.pad_base;
586
587 /* Note that all controllers are using the same IRQ line.
588 * So we can just use the values from the first instance.
589 */
590 if (first_inst) {
591 irq_connect_dynamic(res.irq, DT_INST_IRQ(0, priority),
592 (void (*)(const void *))gpio_intel_isr, dev, res.irq_flags);
593 irq_enable(res.irq);
594 first_inst = false;
595 }
596
597 if (IS_ENABLED(CONFIG_SOC_APOLLO_LAKE)) {
598 /* route to IRQ 14 */
599 sys_bitfield_clear_bit(regs(dev) + REG_MISCCFG, MISCCFG_IRQ_ROUTE_POS);
600 }
601
602 return 0;
603 }
604
605 #define GPIO_INIT_FN_DEFINE(n) \
606 static int gpio_intel_init##n(const struct device *dev) \
607 { \
608 return gpio_intel_acpi_enum(dev, DT_INST_PROP(n, group_index), \
609 ACPI_DT_HID(DT_DRV_INST(n)), ACPI_DT_UID(DT_DRV_INST(n))); \
610 }
611
612 #define GPIO_MMIO_ROM_INIT(n)
613
614 #define GPIO_INIT_CONFIG(n) \
615 static const struct gpio_intel_config gpio_intel_cfg_##n = { \
616 .common = \
617 { \
618 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
619 }, \
620 }
621 #else
622
gpio_intel_dts_init(const struct device * dev)623 static int gpio_intel_dts_init(const struct device *dev)
624 {
625 struct gpio_intel_data *data = dev->data;
626
627 #ifdef CONFIG_SOC_APOLLO_LAKE
628 /*
629 * On Apollo Lake, each GPIO controller has more than 32 pins.
630 * But Zephyr API can only manipulate 32 pins per controller.
631 * So the workaround is to divide each hardware GPIO controller
632 * into 32-pin blocks so each block has a GPIO driver instance.
633 * Compounding to the issue is that there cannot be two device
634 * tree nodes with same register address. So another workaround
635 * is to increment the register addresses by 1 for each block.
636 * So when mapping the address, the lowest 8-bit needs to be
637 * masked to get the actual hardware address. Hence the weird
638 * code below.
639 */
640
641 const struct gpio_intel_config *cfg = dev->config;
642
643 device_map(&data->reg_base,
644 cfg->reg_base.phys_addr & ~0xFFU,
645 cfg->reg_base.size,
646 K_MEM_CACHE_NONE);
647 #else
648 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);
649 #endif
650 data->pad_base = pad_base(dev);
651
652 if (first_inst) {
653 /* Note that all controllers are using the same IRQ line.
654 * So we can just use the values from the first instance.
655 */
656 IRQ_CONNECT(DT_INST_IRQN(0),
657 DT_INST_IRQ(0, priority),
658 gpio_intel_isr, dev,
659 DT_INST_IRQ(0, sense));
660
661 irq_enable(DT_INST_IRQN(0));
662
663 first_inst = false;
664 }
665
666 if (IS_ENABLED(CONFIG_SOC_APOLLO_LAKE)) {
667 /* route to IRQ 14 */
668 sys_bitfield_clear_bit(regs(dev) + REG_MISCCFG,
669 MISCCFG_IRQ_ROUTE_POS);
670 }
671 return 0;
672 }
673
674 #define GPIO_INIT_FN_DEFINE(n) \
675 static int gpio_intel_init##n(const struct device *dev) \
676 { \
677 return gpio_intel_dts_init(dev); \
678 }
679
680 #define GPIO_MMIO_ROM_INIT(n) DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),
681
682 #define GPIO_INIT_CONFIG(n) \
683 static const struct gpio_intel_config gpio_intel_cfg_##n = { \
684 .common = \
685 { \
686 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
687 }, \
688 GPIO_MMIO_ROM_INIT(n).pin_offset = DT_INST_PROP(n, pin_offset), \
689 .group_index = DT_INST_PROP_OR(n, group_index, 0), \
690 .num_pins = DT_INST_PROP(n, ngpios), \
691 }
692
693 #endif
694
695 #define GPIO_INTEL_DEV_CFG_DATA(n) \
696 GPIO_INIT_FN_DEFINE(n) \
697 GPIO_INIT_CONFIG(n); \
698 static struct gpio_intel_data gpio_intel_data_##n; \
699 \
700 DEVICE_DT_INST_DEFINE(n, gpio_intel_init##n, NULL, &gpio_intel_data_##n, \
701 &gpio_intel_cfg_##n, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
702 &gpio_intel_api);
703
704 /* "sub" devices. no more than GPIO_INTEL_NR_SUBDEVS of these! */
705 DT_INST_FOREACH_STATUS_OKAY(GPIO_INTEL_DEV_CFG_DATA)
706
