1/* 2 * Copyright (c) 2016 Cadence Design Systems, Inc. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6/** 7 * @file 8 * @brief Linker command/script file 9 * 10 * Linker script for the Xtensa platform. 11 */ 12 13#include <zephyr/linker/sections.h> 14 15#include <zephyr/devicetree.h> 16#include <zephyr/linker/linker-defs.h> 17#include <zephyr/linker/linker-tool.h> 18 19#define RAMABLE_REGION RAM :sram0_phdr 20#define ROMABLE_REGION srom1_seg :srom1_phdr 21 22MEMORY 23{ 24 dram1_0_seg : org = 0x3FFC0000, len = 0x20000 25 dram0_0_seg : org = 0x3FFE0000, len = 0x20000 26 iram0_0_seg : org = 0x40000000, len = 0x178 27 iram0_1_seg : org = 0x40000178, len = 0x8 28 iram0_2_seg : org = 0x40000180, len = 0x38 29 iram0_3_seg : org = 0x400001B8, len = 0x8 30 iram0_4_seg : org = 0x400001C0, len = 0x38 31 iram0_5_seg : org = 0x400001F8, len = 0x8 32 iram0_6_seg : org = 0x40000200, len = 0x38 33 iram0_7_seg : org = 0x40000238, len = 0x8 34 iram0_8_seg : org = 0x40000240, len = 0x38 35 iram0_9_seg : org = 0x40000278, len = 0x8 36 iram0_10_seg : org = 0x40000280, len = 0x38 37 iram0_11_seg : org = 0x400002B8, len = 0x8 38 iram0_12_seg : org = 0x400002C0, len = 0x38 39 iram0_13_seg : org = 0x400002F8, len = 0x8 40 iram0_14_seg : org = 0x40000300, len = 0x38 41 iram0_15_seg : org = 0x40000338, len = 0x8 42 iram0_16_seg : org = 0x40000340, len = 0x38 43 iram0_17_seg : org = 0x40000378, len = 0x48 44 iram0_18_seg : org = 0x400003C0, len = 0x40 45 iram0_19_seg : org = 0x40000400, len = 0x1FC00 46 srom0_seg : org = 0x50000000, len = 0x300 47 srom1_seg : org = 0x50000300, len = 0xFFFD00 48 RAM : org = 0x60000000, len = 0x4000000 49#ifdef CONFIG_GEN_ISR_TABLES 50 IDT_LIST : org = 0x3ffbe000, len = 0x2000 51#endif 52} 53 54PHDRS 55{ 56 dram1_0_phdr PT_LOAD; 57 dram1_0_bss_phdr PT_LOAD; 58 dram0_0_phdr PT_LOAD; 59 dram0_0_bss_phdr PT_LOAD; 60 iram0_0_phdr PT_LOAD; 61 iram0_1_phdr PT_LOAD; 62 iram0_2_phdr PT_LOAD; 63 iram0_3_phdr PT_LOAD; 64 iram0_4_phdr PT_LOAD; 65 iram0_5_phdr PT_LOAD; 66 iram0_6_phdr PT_LOAD; 67 iram0_7_phdr PT_LOAD; 68 iram0_8_phdr PT_LOAD; 69 iram0_9_phdr PT_LOAD; 70 iram0_10_phdr PT_LOAD; 71 iram0_11_phdr PT_LOAD; 72 iram0_12_phdr PT_LOAD; 73 iram0_13_phdr PT_LOAD; 74 iram0_14_phdr PT_LOAD; 75 iram0_15_phdr PT_LOAD; 76 iram0_16_phdr PT_LOAD; 77 iram0_17_phdr PT_LOAD; 78 iram0_18_phdr PT_LOAD; 79 iram0_19_phdr PT_LOAD; 80 srom0_phdr PT_LOAD; 81 srom1_phdr PT_LOAD; 82 sram0_phdr PT_LOAD; 83 sram0_bss_phdr PT_LOAD; 84} 85 86 87/* Default entry point: */ 88ENTRY(CONFIG_KERNEL_ENTRY) 89 90/* Memory boundary addresses: */ 91_memmap_mem_dram1_start = 0x3ffc0000; 92_memmap_mem_dram1_end = 0x3ffe0000; 93_memmap_mem_dram0_start = 0x3ffe0000; 94_memmap_mem_dram0_end = 0x40000000; 95_memmap_mem_iram0_start = 0x40000000; 96_memmap_mem_iram0_end = 0x40020000; 97_memmap_mem_srom_start = 0x50000000; 98_memmap_mem_srom_end = 0x51000000; 99_memmap_mem_sram_start = 0x60000000; 100_memmap_mem_sram_end = 0x64000000; 101 102/* Memory segment boundary addresses: */ 103_memmap_seg_dram1_0_start = 0x3ffc0000; 104_memmap_seg_dram1_0_max = 0x3ffe0000; 105_memmap_seg_dram0_0_start = 0x3ffe0000; 106_memmap_seg_dram0_0_max = 0x40000000; 107_memmap_seg_iram0_0_start = 0x40000000; 108_memmap_seg_iram0_0_max = 0x40000178; 109_memmap_seg_iram0_1_start = 0x40000178; 110_memmap_seg_iram0_1_max = 0x40000180; 111_memmap_seg_iram0_2_start = 0x40000180; 112_memmap_seg_iram0_2_max = 0x400001b8; 113_memmap_seg_iram0_3_start = 0x400001b8; 114_memmap_seg_iram0_3_max = 0x400001c0; 115_memmap_seg_iram0_4_start = 0x400001c0; 116_memmap_seg_iram0_4_max = 0x400001f8; 117_memmap_seg_iram0_5_start = 0x400001f8; 118_memmap_seg_iram0_5_max = 0x40000200; 119_memmap_seg_iram0_6_start = 0x40000200; 120_memmap_seg_iram0_6_max = 0x40000238; 121_memmap_seg_iram0_7_start = 0x40000238; 122_memmap_seg_iram0_7_max = 0x40000240; 123_memmap_seg_iram0_8_start = 0x40000240; 124_memmap_seg_iram0_8_max = 0x40000278; 125_memmap_seg_iram0_9_start = 0x40000278; 126_memmap_seg_iram0_9_max = 0x40000280; 127_memmap_seg_iram0_10_start = 0x40000280; 128_memmap_seg_iram0_10_max = 0x400002b8; 129_memmap_seg_iram0_11_start = 0x400002b8; 130_memmap_seg_iram0_11_max = 0x400002c0; 131_memmap_seg_iram0_12_start = 0x400002c0; 132_memmap_seg_iram0_12_max = 0x400002f8; 133_memmap_seg_iram0_13_start = 0x400002f8; 134_memmap_seg_iram0_13_max = 0x40000300; 135_memmap_seg_iram0_14_start = 0x40000300; 136_memmap_seg_iram0_14_max = 0x40000338; 137_memmap_seg_iram0_15_start = 0x40000338; 138_memmap_seg_iram0_15_max = 0x40000340; 139_memmap_seg_iram0_16_start = 0x40000340; 140_memmap_seg_iram0_16_max = 0x40000378; 141_memmap_seg_iram0_17_start = 0x40000378; 142_memmap_seg_iram0_17_max = 0x400003c0; 143_memmap_seg_iram0_18_start = 0x400003c0; 144_memmap_seg_iram0_18_max = 0x40000400; 145_memmap_seg_iram0_19_start = 0x40000400; 146_memmap_seg_iram0_19_max = 0x40020000; 147_memmap_seg_srom0_start = 0x50000000; 148_memmap_seg_srom0_max = 0x50000300; 149_memmap_seg_srom1_start = 0x50000300; 150_memmap_seg_srom1_max = 0x51000000; 151_memmap_seg_sram0_start = 0x60000000; 152_memmap_seg_sram0_max = 0x64000000; 153 154_rom_store_table = 0; 155PROVIDE(_memmap_vecbase_reset = 0x40000000); 156PROVIDE(_memmap_reset_vector = 0x50000000); 157/* Various memory-map dependent cache attribute settings: */ 158_memmap_cacheattr_wb_base = 0x00001110; 159_memmap_cacheattr_wt_base = 0x00001110; 160_memmap_cacheattr_bp_base = 0x00002220; 161_memmap_cacheattr_unused_mask = 0xFFFF000F; 162_memmap_cacheattr_wb_trapnull = 0x2222111F; 163_memmap_cacheattr_wba_trapnull = 0x2222111F; 164_memmap_cacheattr_wbna_trapnull = 0x2222111F; 165_memmap_cacheattr_wt_trapnull = 0x2222111F; 166_memmap_cacheattr_bp_trapnull = 0x2222222F; 167_memmap_cacheattr_wb_strict = 0xFFFF111F; 168_memmap_cacheattr_wt_strict = 0xFFFF111F; 169_memmap_cacheattr_bp_strict = 0xFFFF222F; 170_memmap_cacheattr_wb_allvalid = 0x22221112; 171_memmap_cacheattr_wt_allvalid = 0x22221112; 172_memmap_cacheattr_bp_allvalid = 0x22222222; 173PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); 174 175SECTIONS 176{ 177 178#include <zephyr/linker/rel-sections.ld> 179 180#ifdef CONFIG_LLEXT 181#include <zephyr/linker/llext-sections.ld> 182#endif 183 184#ifdef CONFIG_GEN_ISR_TABLES 185#include <zephyr/linker/intlist.ld> 186#endif 187 188 .dram1.rodata : ALIGN(4) 189 { 190 _dram1_rodata_start = ABSOLUTE(.); 191 *(.dram1.rodata) 192 _dram1_rodata_end = ABSOLUTE(.); 193 } >dram1_0_seg :dram1_0_phdr 194 195 .dram1.literal : ALIGN(4) 196 { 197 _dram1_literal_start = ABSOLUTE(.); 198 *(.dram1.literal) 199 _dram1_literal_end = ABSOLUTE(.); 200 } >dram1_0_seg :dram1_0_phdr 201 202 .dram1.data : ALIGN(4) 203 { 204 _dram1_data_start = ABSOLUTE(.); 205 *(.dram1.data) 206 _dram1_data_end = ABSOLUTE(.); 207 } >dram1_0_seg :dram1_0_phdr 208 209 .dram1.bss (NOLOAD) : ALIGN(8) 210 { 211 . = ALIGN (8); 212 _dram1_bss_start = ABSOLUTE(.); 213 *(.dram1.bss) 214 . = ALIGN (8); 215 _dram1_bss_end = ABSOLUTE(.); 216 _memmap_seg_dram1_0_end = ALIGN(0x8); 217 } >dram1_0_seg :dram1_0_bss_phdr 218 219 .dram0.rodata : ALIGN(4) 220 { 221 _dram0_rodata_start = ABSOLUTE(.); 222 *(.dram0.rodata) 223 _dram0_rodata_end = ABSOLUTE(.); 224 } >dram0_0_seg :dram0_0_phdr 225 226 .dram0.literal : ALIGN(4) 227 { 228 _dram0_literal_start = ABSOLUTE(.); 229 *(.dram0.literal) 230 _dram0_literal_end = ABSOLUTE(.); 231 } >dram0_0_seg :dram0_0_phdr 232 233 .dram0.data : ALIGN(4) 234 { 235 _dram0_data_start = ABSOLUTE(.); 236 *(.dram0.data) 237 _dram0_data_end = ABSOLUTE(.); 238 } >dram0_0_seg :dram0_0_phdr 239 240 .dram0.bss (NOLOAD) : ALIGN(8) 241 { 242 . = ALIGN (8); 243 _dram0_bss_start = ABSOLUTE(.); 244 *(.dram0.bss) 245 . = ALIGN (8); 246 _dram0_bss_end = ABSOLUTE(.); 247 _memmap_seg_dram0_0_end = ALIGN(0x8); 248 } >dram0_0_seg :dram0_0_bss_phdr 249 250 .WindowVectors.text : ALIGN(4) 251 { 252 _WindowVectors_text_start = ABSOLUTE(.); 253 KEEP (*(.WindowVectors.text)) 254 _WindowVectors_text_end = ABSOLUTE(.); 255 _memmap_seg_iram0_0_end = ALIGN(0x8); 256 } >iram0_0_seg :iram0_0_phdr 257 258 .Level2InterruptVector.literal : ALIGN(4) 259 { 260 _Level2InterruptVector_literal_start = ABSOLUTE(.); 261 *(.Level2InterruptVector.literal) 262 _Level2InterruptVector_literal_end = ABSOLUTE(.); 263 _memmap_seg_iram0_1_end = ALIGN(0x8); 264 } >iram0_1_seg :iram0_1_phdr 265 266 .Level2InterruptVector.text : ALIGN(4) 267 { 268 _Level2InterruptVector_text_start = ABSOLUTE(.); 269 KEEP (*(.Level2InterruptVector.text)) 270 _Level2InterruptVector_text_end = ABSOLUTE(.); 271 _memmap_seg_iram0_2_end = ALIGN(0x8); 272 } >iram0_2_seg :iram0_2_phdr 273 274 .Level3InterruptVector.literal : ALIGN(4) 275 { 276 _Level3InterruptVector_literal_start = ABSOLUTE(.); 277 *(.Level3InterruptVector.literal) 278 _Level3InterruptVector_literal_end = ABSOLUTE(.); 279 _memmap_seg_iram0_3_end = ALIGN(0x8); 280 } >iram0_3_seg :iram0_3_phdr 281 282 .Level3InterruptVector.text : ALIGN(4) 283 { 284 _Level3InterruptVector_text_start = ABSOLUTE(.); 285 KEEP (*(.Level3InterruptVector.text)) 286 _Level3InterruptVector_text_end = ABSOLUTE(.); 287 _memmap_seg_iram0_4_end = ALIGN(0x8); 288 } >iram0_4_seg :iram0_4_phdr 289 290 .Level4InterruptVector.literal : ALIGN(4) 291 { 292 _Level4InterruptVector_literal_start = ABSOLUTE(.); 293 *(.Level4InterruptVector.literal) 294 _Level4InterruptVector_literal_end = ABSOLUTE(.); 295 _memmap_seg_iram0_5_end = ALIGN(0x8); 296 } >iram0_5_seg :iram0_5_phdr 297 298 .Level4InterruptVector.text : ALIGN(4) 299 { 300 _Level4InterruptVector_text_start = ABSOLUTE(.); 301 KEEP (*(.Level4InterruptVector.text)) 302 _Level4InterruptVector_text_end = ABSOLUTE(.); 303 _memmap_seg_iram0_6_end = ALIGN(0x8); 304 } >iram0_6_seg :iram0_6_phdr 305 306 .Level5InterruptVector.literal : ALIGN(4) 307 { 308 _Level5InterruptVector_literal_start = ABSOLUTE(.); 309 *(.Level5InterruptVector.literal) 310 _Level5InterruptVector_literal_end = ABSOLUTE(.); 311 _memmap_seg_iram0_7_end = ALIGN(0x8); 312 } >iram0_7_seg :iram0_7_phdr 313 314 .Level5InterruptVector.text : ALIGN(4) 315 { 316 _Level5InterruptVector_text_start = ABSOLUTE(.); 317 KEEP (*(.Level5InterruptVector.text)) 318 _Level5InterruptVector_text_end = ABSOLUTE(.); 319 _memmap_seg_iram0_8_end = ALIGN(0x8); 320 } >iram0_8_seg :iram0_8_phdr 321 322 .DebugExceptionVector.literal : ALIGN(4) 323 { 324 _DebugExceptionVector_literal_start = ABSOLUTE(.); 325 *(.DebugExceptionVector.literal) 326 _DebugExceptionVector_literal_end = ABSOLUTE(.); 327 _memmap_seg_iram0_9_end = ALIGN(0x8); 328 } >iram0_9_seg :iram0_9_phdr 329 330 .DebugExceptionVector.text : ALIGN(4) 331 { 332 _DebugExceptionVector_text_start = ABSOLUTE(.); 333 KEEP (*(.DebugExceptionVector.text)) 334 _DebugExceptionVector_text_end = ABSOLUTE(.); 335 _memmap_seg_iram0_10_end = ALIGN(0x8); 336 } >iram0_10_seg :iram0_10_phdr 337 338 .NMIExceptionVector.literal : ALIGN(4) 339 { 340 _NMIExceptionVector_literal_start = ABSOLUTE(.); 341 *(.NMIExceptionVector.literal) 342 _NMIExceptionVector_literal_end = ABSOLUTE(.); 343 _memmap_seg_iram0_11_end = ALIGN(0x8); 344 } >iram0_11_seg :iram0_11_phdr 345 346 .NMIExceptionVector.text : ALIGN(4) 347 { 348 _NMIExceptionVector_text_start = ABSOLUTE(.); 349 KEEP (*(.NMIExceptionVector.text)) 350 _NMIExceptionVector_text_end = ABSOLUTE(.); 351 _memmap_seg_iram0_12_end = ALIGN(0x8); 352 } >iram0_12_seg :iram0_12_phdr 353 354 .KernelExceptionVector.literal : ALIGN(4) 355 { 356 _KernelExceptionVector_literal_start = ABSOLUTE(.); 357 *(.KernelExceptionVector.literal) 358 _KernelExceptionVector_literal_end = ABSOLUTE(.); 359 _memmap_seg_iram0_13_end = ALIGN(0x8); 360 } >iram0_13_seg :iram0_13_phdr 361 362 .KernelExceptionVector.text : ALIGN(4) 363 { 364 _KernelExceptionVector_text_start = ABSOLUTE(.); 365 KEEP (*(.KernelExceptionVector.text)) 366 _KernelExceptionVector_text_end = ABSOLUTE(.); 367 _memmap_seg_iram0_14_end = ALIGN(0x8); 368 } >iram0_14_seg :iram0_14_phdr 369 370 .UserExceptionVector.literal : ALIGN(4) 371 { 372 _UserExceptionVector_literal_start = ABSOLUTE(.); 373 *(.UserExceptionVector.literal) 374 _UserExceptionVector_literal_end = ABSOLUTE(.); 375 _memmap_seg_iram0_15_end = ALIGN(0x8); 376 } >iram0_15_seg :iram0_15_phdr 377 378 .UserExceptionVector.text : ALIGN(4) 379 { 380 _UserExceptionVector_text_start = ABSOLUTE(.); 381 KEEP (*(.UserExceptionVector.text)) 382 _UserExceptionVector_text_end = ABSOLUTE(.); 383 _memmap_seg_iram0_16_end = ALIGN(0x8); 384 } >iram0_16_seg :iram0_16_phdr 385 386 .DoubleExceptionVector.literal : ALIGN(4) 387 { 388 _DoubleExceptionVector_literal_start = ABSOLUTE(.); 389 *(.DoubleExceptionVector.literal) 390 _DoubleExceptionVector_literal_end = ABSOLUTE(.); 391 _memmap_seg_iram0_17_end = ALIGN(0x8); 392 } >iram0_17_seg :iram0_17_phdr 393 394 .DoubleExceptionVector.text : ALIGN(4) 395 { 396 _DoubleExceptionVector_text_start = ABSOLUTE(.); 397 KEEP (*(.DoubleExceptionVector.text)) 398 _DoubleExceptionVector_text_end = ABSOLUTE(.); 399 _memmap_seg_iram0_18_end = ALIGN(0x8); 400 } >iram0_18_seg :iram0_18_phdr 401 402 .iram0.text : ALIGN(4) 403 { 404 _iram0_text_start = ABSOLUTE(.); 405 *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) 406 _iram0_text_end = ABSOLUTE(.); 407 _memmap_seg_iram0_19_end = ALIGN(0x8); 408 } >iram0_19_seg :iram0_19_phdr 409 410 .ResetVector.text : ALIGN(4) 411 { 412 __rom_region_start = ABSOLUTE(.); 413 _ResetVector_text_start = ABSOLUTE(.); 414 KEEP (*(.ResetVector.text)) 415 _ResetVector_text_end = ABSOLUTE(.); 416 _memmap_seg_srom0_end = ALIGN(0x8); 417 } >srom0_seg :srom0_phdr 418 419#ifdef CONFIG_CODE_DATA_RELOCATION 420#include <linker_relocate.ld> 421#endif 422 423 .srom.rodata : ALIGN(4) 424 { 425 _srom_rodata_start = ABSOLUTE(.); 426 *(.srom.rodata) 427 _srom_rodata_end = ABSOLUTE(.); 428 } >srom1_seg :srom1_phdr 429 430 .srom.text : ALIGN(4) 431 { 432 _srom_text_start = ABSOLUTE(.); 433 *(.srom.literal .srom.text) 434 _srom_text_end = ABSOLUTE(.); 435 _memmap_seg_srom1_end = ALIGN(0x8); 436 __rom_region_end = ABSOLUTE(.); 437 } >srom1_seg :srom1_phdr 438 439 .sram.rodata : ALIGN(4) 440 { 441 _image_ram_start = ABSOLUTE(.); 442 _sram_rodata_start = ABSOLUTE(.); 443 *(.sram.rodata) 444 _sram_rodata_end = ABSOLUTE(.); 445 } >RAM :sram0_phdr 446 447#include <zephyr/linker/common-rom.ld> 448/* Located in generated directory. This file is populated by calling 449 * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs. 450 */ 451#include <snippets-rom-sections.ld> 452 453 .rodata : ALIGN(4) 454 { 455 __rodata_region_start = ABSOLUTE(.); 456 *(.rodata) 457 *(.rodata.*) 458 *(.gnu.linkonce.r.*) 459 *(.rodata1) 460 461 . = ALIGN(4); 462 #include <snippets-rodata.ld> 463 . = ALIGN(4); 464 465 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); 466 KEEP (*(.xt_except_table)) 467 KEEP (*(.gcc_except_table .gcc_except_table.*)) 468 *(.gnu.linkonce.e.*) 469 *(.gnu.version_r) 470 KEEP (*(.eh_frame)) 471 /* C++ constructor and destructor tables, properly ordered: */ 472 KEEP (*crtbegin.o(.ctors)) 473 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 474 KEEP (*(SORT(.ctors.*))) 475 KEEP (*(.ctors)) 476 KEEP (*crtbegin.o(.dtors)) 477 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 478 KEEP (*(SORT(.dtors.*))) 479 KEEP (*(.dtors)) 480 /* C++ exception handlers table: */ 481 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 482 *(.xt_except_desc) 483 *(.gnu.linkonce.h.*) 484 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); 485 *(.xt_except_desc_end) 486 *(.dynamic) 487 *(.gnu.version_d) 488 . = ALIGN(4); /* this table MUST be 4-byte aligned */ 489 _bss_table_start = ABSOLUTE(.); 490 LONG(_dram1_bss_start) 491 LONG(_dram1_bss_end) 492 LONG(_dram0_bss_start) 493 LONG(_dram0_bss_end) 494 LONG(_bss_start) 495 LONG(_bss_end) 496 _bss_table_end = ABSOLUTE(.); 497 __rodata_region_end = ABSOLUTE(.); 498 } >RAM :sram0_phdr 499 500 .sram.text : ALIGN(4) 501 { 502 _sram_text_start = ABSOLUTE(.); 503 *(.sram.literal .sram.text) 504 _sram_text_end = ABSOLUTE(.); 505 } >RAM :sram0_phdr 506 507 __text_region_start = ALIGN(4); 508 .text : ALIGN(4) 509 { 510 _stext = .; 511 _text_start = ABSOLUTE(.); 512 *(.entry.text) 513 *(.init.literal) 514 KEEP(*(.init)) 515 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) 516 *(.fini.literal) 517 KEEP(*(.fini)) 518 *(.gnu.version) 519 _text_end = ABSOLUTE(.); 520 _etext = .; 521 } >RAM :sram0_phdr 522 __text_region_end = .; 523 524 .sram.data : ALIGN(4) 525 { 526 _sram_data_start = ABSOLUTE(.); 527 *(.sram.data) 528 _sram_data_end = ABSOLUTE(.); 529 } >RAM :sram0_phdr 530 531 .noinit : ALIGN(4) 532 { 533 *(.noinit) 534 *(.noinit.*) 535 } >RAM :sram0_phdr 536 537#include <snippets-sections.ld> 538 539 .data : ALIGN(4) 540 { 541 __data_start = ABSOLUTE(.); 542 *(.data) 543 *(.data.*) 544 *(.gnu.linkonce.d.*) 545 KEEP(*(.gnu.linkonce.d.*personality*)) 546 *(.data1) 547 *(.sdata) 548 *(.sdata.*) 549 *(.gnu.linkonce.s.*) 550 *(.sdata2) 551 *(.sdata2.*) 552 *(.gnu.linkonce.s2.*) 553 KEEP(*(.jcr)) 554 555 . = ALIGN(4); 556 #include <snippets-rwdata.ld> 557 . = ALIGN(4); 558 559#ifdef CONFIG_CODE_DATA_RELOCATION 560#include <linker_sram_data_relocate.ld> 561#endif 562 . = ALIGN(4); 563 564 __data_end = ABSOLUTE(.); 565 } >RAM :sram0_phdr 566 567#include <snippets-data-sections.ld> 568 569#include <zephyr/linker/common-ram.ld> 570 571 .tm_clone_table : 572 { 573 *(.tm_clone_table) 574 } >RAM :sram0_phdr 575 576#include <snippets-ram-sections.ld> 577 578 .bss (NOLOAD) : ALIGN(8) 579 { 580 . = ALIGN (8); 581 _bss_start = ABSOLUTE(.); 582 *(.dynsbss) 583 *(.sbss) 584 *(.sbss.*) 585 *(.gnu.linkonce.sb.*) 586 *(.scommon) 587 *(.sbss2) 588 *(.sbss2.*) 589 *(.gnu.linkonce.sb2.*) 590 *(.dynbss) 591 *(.bss) 592 *(.bss.*) 593 *(.gnu.linkonce.b.*) 594 *(COMMON) 595 *(.sram.bss) 596#ifdef CONFIG_CODE_DATA_RELOCATION 597#include <linker_sram_bss_relocate.ld> 598#endif 599 . = ALIGN (8); 600 _bss_end = ABSOLUTE(.); 601 _end = ALIGN(0x8); 602 _image_ram_end = ABSOLUTE(.); 603 PROVIDE(end = ALIGN(0x8)); 604 _stack_sentry = ALIGN(0x8); 605 _memmap_seg_sram0_end = ALIGN(0x8); 606 } >RAM :sram0_bss_phdr 607 __stack = 0x64000000; 608 _heap_sentry = 0x64000000; 609 .comment 0 : { *(.comment) } 610 .debug 0 : { *(.debug) } 611 .line 0 : { *(.line) } 612 .debug_srcinfo 0 : { *(.debug_srcinfo) } 613 .debug_sfnames 0 : { *(.debug_sfnames) } 614 .debug_aranges 0 : { *(.debug_aranges) } 615 .debug_pubnames 0 : { *(.debug_pubnames) } 616 .debug_info 0 : { *(.debug_info) } 617 .debug_abbrev 0 : { *(.debug_abbrev) } 618 .debug_line 0 : { *(.debug_line) } 619 .debug_frame 0 : { *(.debug_frame) } 620 .debug_str 0 : { *(.debug_str) } 621 .debug_loc 0 : { *(.debug_loc) } 622 .debug_macinfo 0 : { *(.debug_macinfo) } 623 .debug_weaknames 0 : { *(.debug_weaknames) } 624 .debug_funcnames 0 : { *(.debug_funcnames) } 625 .debug_typenames 0 : { *(.debug_typenames) } 626 .debug_varnames 0 : { *(.debug_varnames) } 627 .debug_ranges 0 : { *(.debug_ranges) } 628 .debug_addr 0 : { *(.debug_addr) } 629 .debug_line_str 0 : { *(.debug_line_str) } 630 .debug_loclists 0 : { *(.debug_loclists) } 631 .debug_macro 0 : { *(.debug_macro) } 632 .debug_names 0 : { *(.debug_names) } 633 .debug_rnglists 0 : { *(.debug_rnglists) } 634 .debug_str_offsets 0 : { *(.debug_str_offsets) } 635 .debug_sup 0 : { *(.debug_sup) } 636 .xtensa.info 0 : { *(.xtensa.info) } 637 .xt.insn 0 : 638 { 639 KEEP (*(.xt.insn)) 640 KEEP (*(.gnu.linkonce.x.*)) 641 } 642 .xt.prop 0 : 643 { 644 KEEP (*(.xt.prop)) 645 KEEP (*(.xt.prop.*)) 646 KEEP (*(.gnu.linkonce.prop.*)) 647 } 648 .xt.lit 0 : 649 { 650 KEEP (*(.xt.lit)) 651 KEEP (*(.xt.lit.*)) 652 KEEP (*(.gnu.linkonce.p.*)) 653 } 654 .debug.xt.callgraph 0 : 655 { 656 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) 657 } 658 659 /DISCARD/ : { *(.note.GNU-stack) } 660} 661
