1/*
2 * Copyright (c) 2019 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* nRF-specific defines. */
8#if defined(CONFIG_CPU_HAS_NRF_IDAU) && CONFIG_ARM_NSC_REGION_BASE_ADDRESS == 0
9	/* This SOC needs the NSC region to be at the end of an SPU region. */
10	#define __NSC_ALIGN (ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE) \
11			- MAX(32, (1 << LOG2CEIL(__sg_size))))
12	#define NSC_ALIGN \
13		. =  (__NSC_ALIGN + ((ABSOLUTE(.) > __NSC_ALIGN) \
14				? CONFIG_NRF_SPU_FLASH_REGION_SIZE : 0))
15	#define NSC_ALIGN_END . = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE)
16#endif /* CONFIG_CPU_HAS_NRF_IDAU && CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 */
17
18#ifndef NSC_ALIGN
19#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0
20	#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)
21#else
22	/* The ARM SAU requires regions to be 32-byte-aligned. */
23	#define NSC_ALIGN . = ALIGN(32)
24#endif /* CONFIG_ARM_NSC_REGION_BASE_ADDRESS */
25#endif /* !NSC_ALIGN */
26
27#ifndef NSC_ALIGN_END
28	#define NSC_ALIGN_END . = ALIGN(32)
29#endif
30
31SECTION_PROLOGUE(.gnu.sgstubs,,)
32{
33	NSC_ALIGN;
34	__sg_start = .;
35	/* No input section necessary, since the Secure Entry Veneers are
36	   automatically placed after the .gnu.sgstubs output section. */
37} GROUP_LINK_IN(ROMABLE_REGION)
38__sg_end = .;
39__sg_size = __sg_end - __sg_start;
40NSC_ALIGN_END;
41__nsc_size = . - __sg_start;
42
43/* nRF-specific ASSERT. */
44#ifdef CONFIG_CPU_HAS_NRF_IDAU
45	#define NRF_SG_START (__sg_start % CONFIG_NRF_SPU_FLASH_REGION_SIZE)
46	#define NRF_SG_SIZE (CONFIG_NRF_SPU_FLASH_REGION_SIZE - NRF_SG_START)
47	ASSERT((__sg_size == 0)
48		|| (((1 << LOG2CEIL(NRF_SG_SIZE)) == NRF_SG_SIZE) /* Pow of 2 */
49			&& (NRF_SG_SIZE >= 32)
50			&& (NRF_SG_SIZE <= 4096)),
51		"The Non-Secure Callable region size must be a power of 2 \
52between 32 and 4096 bytes.")
53#endif
54