| /hal_nxp-3.5.0/mcux/mcux-sdk/CMSIS/Include/ |
| D | core_cm3.h | 762 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_sc300.h | 747 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_cm4.h | 820 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_cm7.h | 1040 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_armv8mml.h | 1015 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_cm33.h | 1015 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_cm35p.h | 1015 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_armv81mml.h | 1096 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/CMSIS/Core/Include/ |
| D | core_cm4.h | 825 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_cm7.h | 1049 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| D | core_cm33.h | 1023 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 50071 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 50069 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 50071 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_ca53.h | 50083 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| D | MIMX8MN6_cm7.h | 50069 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 50071 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 50069 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM2/ |
| D | MIMX8MM2_cm4.h | 68887 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM1/ |
| D | MIMX8MM1_cm4.h | 68887 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM3/ |
| D | MIMX8MM3_cm4.h | 68887 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM4/ |
| D | MIMX8MM4_cm4.h | 68887 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM5/ |
| D | MIMX8MM5_cm4.h | 68887 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM6/ |
| D | MIMX8MM6_cm4.h | 68887 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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| D | MIMX8MM6_ca53.h | 68352 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ member
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