/Zephyr-Core-3.5.0/soc/sparc/gr716a/ |
D | linker.ld | 39 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/soc/sparc/leon3/ |
D | linker.ld | 30 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/nios2/ |
D | linker.ld | 44 #define ROMABLE_REGION FLASH macro 46 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/arc/v2/ |
D | linker.ld | 18 #define ROMABLE_REGION ICCM macro 23 #define ROMABLE_REGION FLASH macro 27 #define ROMABLE_REGION SRAM macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/mips/ |
D | linker.ld | 18 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/scripts/ |
D | linker.ld | 22 #define ROMABLE_REGION FLASH macro 24 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/soc/arm64/nxp_imx/mimx9/ |
D | linker.ld | 22 #define ROMABLE_REGION FLASH macro 24 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/arm/cortex_a_r/scripts/ |
D | linker.ld | 23 #define ROMABLE_REGION FLASH macro 25 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/ |
D | linker.ld | 17 #define ROMABLE_REGION ROM macro 19 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/arm/cortex_m/scripts/ |
D | linker.ld | 23 #define ROMABLE_REGION FLASH macro 25 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/common/ |
D | linker.ld | 24 #define ROMABLE_REGION ROM macro 26 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/andes_v5/ae350/ |
D | linker.ld | 25 #define ROMABLE_REGION ROM macro 27 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/boards/x86/qemu_x86/ |
D | qemu_x86_tiny.ld | 79 #define ROMABLE_REGION ROM macro 82 #define ROMABLE_REGION RAM macro 588 #define ROMABLE_REGION FLASH macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/x86/ia32/ |
D | linker.ld | 48 #define ROMABLE_REGION ROM macro 51 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/soc/riscv/openisa_rv32m1/ |
D | linker.ld | 25 #define ROMABLE_REGION ROM macro
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/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/ |
D | xtensa-cavs-linker.ld | 324 #define ROMABLE_REGION RAM macro 377 #define ROMABLE_REGION ucram macro
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/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/ |
D | ace-link.ld | 294 #define ROMABLE_REGION ram macro 345 #define ROMABLE_REGION ucram macro
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/Zephyr-Core-3.5.0/include/zephyr/arch/x86/intel64/ |
D | linker.ld | 9 #define ROMABLE_REGION RAM macro
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/Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/ |
D | mcuboot.ld | 32 #define ROMABLE_REGION dram_seg macro
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D | default.ld | 23 #define ROMABLE_REGION ROM macro
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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32/ |
D | mcuboot.ld | 30 #define ROMABLE_REGION dram_seg macro
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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s3/ |
D | default_appcpu.ld | 21 #define ROMABLE_REGION iram0_0_seg macro
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D | mcuboot.ld | 30 #define ROMABLE_REGION dram_seg macro
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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s2/ |
D | mcuboot.ld | 30 #define ROMABLE_REGION dram_seg macro
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D | default.ld | 38 #define ROMABLE_REGION ROM macro
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