Home
last modified time | relevance | path

Searched defs:PSCCTL0_CLR (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1236 __O uint32_t PSCCTL0_CLR; /**< clock clear register 0, offset: 0x70 */ member
2722 __O uint32_t PSCCTL0_CLR; /**< clock clear register 0, offset: 0x70 */ member
DMIMXRT685S_cm33.h6947 __O uint32_t PSCCTL0_CLR; /**< clock clear register 0, offset: 0x70 */ member
8452 __O uint32_t PSCCTL0_CLR; /**< clock clear register 0, offset: 0x70 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6947 __O uint32_t PSCCTL0_CLR; /**< clock clear register 0, offset: 0x70 */ member
8452 __O uint32_t PSCCTL0_CLR; /**< clock clear register 0, offset: 0x70 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1913 __O uint32_t PSCCTL0_CLR; /**< Clock Control 0 Clear, offset: 0x70 */ member
4112 __IO uint32_t PSCCTL0_CLR; /**< Clock Clear 0, offset: 0x70 */ member
DMIMXRT595S_cm33.h8151 __O uint32_t PSCCTL0_CLR; /**< Clock Control 0 Clear, offset: 0x70 */ member
10369 __IO uint32_t PSCCTL0_CLR; /**< Clock Clear 0, offset: 0x70 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h8150 __O uint32_t PSCCTL0_CLR; /**< Clock Control 0 Clear, offset: 0x70 */ member
10368 __IO uint32_t PSCCTL0_CLR; /**< Clock Clear 0, offset: 0x70 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h8147 __O uint32_t PSCCTL0_CLR; /**< Clock Control 0 Clear, offset: 0x70 */ member
10365 __IO uint32_t PSCCTL0_CLR; /**< Clock Clear 0, offset: 0x70 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16938 …__IO uint32_t PSCCTL0_CLR; /**< VDD2_COMP Peripheral Clock Control 0 Clear, … member
20230 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
21543 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT735S_hifi1.h10660 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
11992 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT735S_cm33_core1.h10696 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
12028 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT735S_cm33_core0.h17493 …__IO uint32_t PSCCTL0_CLR; /**< VDD2_COMP Peripheral Clock Control 0 Clear, … member
20802 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h16938 …__IO uint32_t PSCCTL0_CLR; /**< VDD2_COMP Peripheral Clock Control 0 Clear, … member
20230 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
21543 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT798S_hifi1.h10660 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
11992 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT798S_cm33_core1.h10696 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
12028 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT798S_hifi4.h17432 …__IO uint32_t PSCCTL0_CLR; /**< VDD2_COMP Peripheral Clock Control 0 Clear, … member
20741 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT798S_cm33_core0.h17493 …__IO uint32_t PSCCTL0_CLR; /**< VDD2_COMP Peripheral Clock Control 0 Clear, … member
20802 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h16938 …__IO uint32_t PSCCTL0_CLR; /**< VDD2_COMP Peripheral Clock Control 0 Clear, … member
20230 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
21543 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT758S_cm33_core1.h10696 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
12028 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT758S_hifi1.h10660 …__IO uint32_t PSCCTL0_CLR; /**< VDD1_SENSE Peripheral Clock Control 0 Clear,… member
11992 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
DMIMXRT758S_cm33_core0.h17493 …__IO uint32_t PSCCTL0_CLR; /**< VDD2_COMP Peripheral Clock Control 0 Clear, … member
20802 …__IO uint32_t PSCCTL0_CLR; /**< VDDN_COM Peripheral Clock 0 Clear, offset: 0… member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h19962 __O uint32_t PSCCTL0_CLR; /**< Peripheral clock clear 0, offset: 0x70 */ member
21419 __O uint32_t PSCCTL0_CLR; /**< Peripheral clock clear 0, offset: 0x70 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h19962 __O uint32_t PSCCTL0_CLR; /**< Peripheral clock clear 0, offset: 0x70 */ member
21419 __O uint32_t PSCCTL0_CLR; /**< Peripheral clock clear 0, offset: 0x70 */ member