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Searched defs:PSCCTL0 (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1228 __IO uint32_t PSCCTL0; /**< clock control register 0, offset: 0x10 */ member
2714 __IO uint32_t PSCCTL0; /**< clock control register 0, offset: 0x10 */ member
DMIMXRT685S_cm33.h6939 __IO uint32_t PSCCTL0; /**< clock control register 0, offset: 0x10 */ member
8444 __IO uint32_t PSCCTL0; /**< clock control register 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6939 __IO uint32_t PSCCTL0; /**< clock control register 0, offset: 0x10 */ member
8444 __IO uint32_t PSCCTL0; /**< clock control register 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1905 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
4104 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
DMIMXRT595S_cm33.h8143 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
10361 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h8142 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
10360 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h8139 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
10357 __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16924 …__IO uint32_t PSCCTL0; /**< VDD2_COMP Peripheral Clock Control 0, offset… member
20224 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
21539 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT735S_hifi1.h10654 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
11988 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT735S_cm33_core1.h10690 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
12024 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT735S_cm33_core0.h17479 …__IO uint32_t PSCCTL0; /**< VDD2_COMP Peripheral Clock Control 0, offset… member
20798 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h16924 …__IO uint32_t PSCCTL0; /**< VDD2_COMP Peripheral Clock Control 0, offset… member
20224 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
21539 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT798S_hifi1.h10654 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
11988 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT798S_cm33_core1.h10690 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
12024 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT798S_hifi4.h17418 …__IO uint32_t PSCCTL0; /**< VDD2_COMP Peripheral Clock Control 0, offset… member
20737 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT798S_cm33_core0.h17479 …__IO uint32_t PSCCTL0; /**< VDD2_COMP Peripheral Clock Control 0, offset… member
20798 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h16924 …__IO uint32_t PSCCTL0; /**< VDD2_COMP Peripheral Clock Control 0, offset… member
20224 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
21539 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT758S_cm33_core1.h10690 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
12024 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT758S_hifi1.h10654 …__IO uint32_t PSCCTL0; /**< VDD1_SENSE Peripheral Clock Control 0, offse… member
11988 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
DMIMXRT758S_cm33_core0.h17479 …__IO uint32_t PSCCTL0; /**< VDD2_COMP Peripheral Clock Control 0, offset… member
20798 __IO uint32_t PSCCTL0; /**< VDDN_COM Peripheral clock 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h19954 __IO uint32_t PSCCTL0; /**< clock control 0, offset: 0x10 */ member
21411 __IO uint32_t PSCCTL0; /**< Peripheral clock control 0, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h19954 __IO uint32_t PSCCTL0; /**< clock control 0, offset: 0x10 */ member
21411 __IO uint32_t PSCCTL0; /**< Peripheral clock control 0, offset: 0x10 */ member