1 /* dw_i2c.c - I2C file for Design Ware */
2
3 /*
4 * Copyright (c) 2015 Intel Corporation
5 * Copyright (c) 2022 Andrei-Edward Popa
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9 #include <stddef.h>
10 #include <zephyr/types.h>
11 #include <stdlib.h>
12 #include <stdbool.h>
13
14 #include <zephyr/drivers/i2c.h>
15 #include <zephyr/kernel.h>
16 #include <zephyr/init.h>
17 #include <zephyr/pm/device.h>
18 #include <zephyr/arch/cpu.h>
19 #include <string.h>
20
21 #if defined(CONFIG_PINCTRL)
22 #include <zephyr/drivers/pinctrl.h>
23 #endif
24 #if defined(CONFIG_RESET)
25 #include <zephyr/drivers/reset.h>
26 #endif
27
28 #include <errno.h>
29 #include <zephyr/sys/sys_io.h>
30
31 #include <zephyr/sys/util.h>
32
33 #if defined(CONFIG_I2C_DW_LPSS_DMA)
34 #include <zephyr/drivers/dma.h>
35 #include <zephyr/drivers/dma/dma_intel_lpss.h>
36 #endif
37
38 #ifdef CONFIG_IOAPIC
39 #include <zephyr/drivers/interrupt_controller/ioapic.h>
40 #endif
41
42 #include "i2c_dw.h"
43 #include "i2c_dw_registers.h"
44 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
45 #include <zephyr/logging/log.h>
46 #include <zephyr/irq.h>
47 LOG_MODULE_REGISTER(i2c_dw);
48
49 #include "i2c-priv.h"
50
get_regs(const struct device * dev)51 static inline uint32_t get_regs(const struct device *dev)
52 {
53 return (uint32_t)DEVICE_MMIO_GET(dev);
54 }
55
56 #ifdef CONFIG_I2C_DW_LPSS_DMA
i2c_dw_enable_idma(const struct device * dev,bool enable)57 void i2c_dw_enable_idma(const struct device *dev, bool enable)
58 {
59 uint32_t reg;
60 uint32_t reg_base = get_regs(dev);
61
62 if (enable) {
63 write_dma_cr(DW_IC_DMA_ENABLE, reg_base);
64 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
65 } else {
66 reg = read_dma_cr(reg_base);
67 reg &= ~DW_IC_DMA_ENABLE;
68 write_dma_cr(reg, reg_base);
69 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
70 }
71 }
72
cb_i2c_idma_transfer(const struct device * dma,void * user_data,uint32_t channel,int status)73 void cb_i2c_idma_transfer(const struct device *dma, void *user_data, uint32_t channel, int status)
74 {
75 const struct device *dev = (const struct device *)user_data;
76 const struct i2c_dw_rom_config *const rom = dev->config;
77 struct i2c_dw_dev_config *const dw = dev->data;
78
79 dma_stop(rom->dma_dev, channel);
80 i2c_dw_enable_idma(dev, false);
81
82 if (status) {
83 dw->xfr_status = true;
84 } else {
85 dw->xfr_status = false;
86 }
87 }
88
i2c_dw_set_fifo_th(const struct device * dev,uint8_t fifo_depth)89 void i2c_dw_set_fifo_th(const struct device *dev, uint8_t fifo_depth)
90 {
91 uint32_t reg_base = get_regs(dev);
92
93 write_tdlr(fifo_depth, reg_base);
94 write_rdlr(fifo_depth - 1, reg_base);
95 }
96
i2c_dw_dr_phy_addr(const struct device * dev)97 inline void *i2c_dw_dr_phy_addr(const struct device *dev)
98 {
99 struct i2c_dw_dev_config *const dw = dev->data;
100
101 return (void *)(dw->phy_addr + DW_IC_REG_DATA_CMD);
102 }
103
i2c_dw_idma_rx_transfer(const struct device * dev)104 int32_t i2c_dw_idma_rx_transfer(const struct device *dev)
105 {
106 struct i2c_dw_dev_config *const dw = dev->data;
107 const struct i2c_dw_rom_config *const rom = dev->config;
108
109 struct dma_config dma_cfg = {0};
110 struct dma_block_config dma_block_cfg = {0};
111
112 if (!device_is_ready(rom->dma_dev)) {
113 LOG_DBG("DMA device is not ready");
114 return -ENODEV;
115 }
116
117 dma_cfg.dma_slot = 1U;
118 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
119 dma_cfg.source_data_size = 1U;
120 dma_cfg.dest_data_size = 1U;
121 dma_cfg.source_burst_length = 1U;
122 dma_cfg.dest_burst_length = 1U;
123 dma_cfg.dma_callback = cb_i2c_idma_transfer;
124 dma_cfg.user_data = (void *)dev;
125 dma_cfg.complete_callback_en = 0U;
126 dma_cfg.error_callback_dis = 0U;
127 dma_cfg.block_count = 1U;
128 dma_cfg.head_block = &dma_block_cfg;
129
130 dma_block_cfg.block_size = dw->xfr_len;
131 dma_block_cfg.dest_address = (uint64_t)&dw->xfr_buf[0];
132 dma_block_cfg.source_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
133 dw->xfr_status = false;
134
135 if (dma_config(rom->dma_dev, DMA_INTEL_LPSS_RX_CHAN, &dma_cfg)) {
136 LOG_DBG("Error transfer");
137 return -EIO;
138 }
139
140 if (dma_start(rom->dma_dev, DMA_INTEL_LPSS_RX_CHAN)) {
141 LOG_DBG("Error transfer");
142 return -EIO;
143 }
144
145 i2c_dw_enable_idma(dev, true);
146 i2c_dw_set_fifo_th(dev, 1);
147
148 return 0;
149 }
150
i2c_dw_idma_tx_transfer(const struct device * dev,uint64_t data)151 int32_t i2c_dw_idma_tx_transfer(const struct device *dev, uint64_t data)
152 {
153 const struct i2c_dw_rom_config *const rom = dev->config;
154 struct i2c_dw_dev_config *const dw = dev->data;
155
156 struct dma_config dma_cfg = {0};
157 struct dma_block_config dma_block_cfg = {0};
158
159 if (!device_is_ready(rom->dma_dev)) {
160 LOG_DBG("DMA device is not ready");
161 return -ENODEV;
162 }
163
164 dma_cfg.dma_slot = 0U;
165 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
166 dma_cfg.source_data_size = 1U;
167 dma_cfg.dest_data_size = 1U;
168 dma_cfg.source_burst_length = 1U;
169 dma_cfg.dest_burst_length = 1U;
170 dma_cfg.dma_callback = cb_i2c_idma_transfer;
171 dma_cfg.user_data = (void *)dev;
172 dma_cfg.complete_callback_en = 0U;
173 dma_cfg.error_callback_dis = 0U;
174 dma_cfg.block_count = 1U;
175 dma_cfg.head_block = &dma_block_cfg;
176
177 dma_block_cfg.block_size = 1;
178 dma_block_cfg.source_address = (uint64_t)&data;
179 dma_block_cfg.dest_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
180 dw->xfr_status = false;
181
182 if (dma_config(rom->dma_dev, DMA_INTEL_LPSS_TX_CHAN, &dma_cfg)) {
183 LOG_DBG("Error transfer");
184 return -EIO;
185 }
186
187 if (dma_start(rom->dma_dev, DMA_INTEL_LPSS_TX_CHAN)) {
188 LOG_DBG("Error transfer");
189 return -EIO;
190 }
191 i2c_dw_enable_idma(dev, true);
192 i2c_dw_set_fifo_th(dev, 1);
193
194 return 0;
195 }
196 #endif
197
i2c_dw_data_ask(const struct device * dev)198 static inline void i2c_dw_data_ask(const struct device *dev)
199 {
200 struct i2c_dw_dev_config *const dw = dev->data;
201 uint32_t data;
202 int tx_empty;
203 int rx_empty;
204 int cnt;
205 int rx_buffer_depth, tx_buffer_depth;
206 union ic_comp_param_1_register ic_comp_param_1;
207 uint32_t reg_base = get_regs(dev);
208
209 /* No more bytes to request, so command queue is no longer needed */
210 if (dw->request_bytes == 0U) {
211 clear_bit_intr_mask_tx_empty(reg_base);
212 return;
213 }
214
215 /* Get the FIFO depth that could be from 2 to 256 from HW spec */
216 ic_comp_param_1.raw = read_comp_param_1(reg_base);
217 rx_buffer_depth = ic_comp_param_1.bits.rx_buffer_depth + 1;
218 tx_buffer_depth = ic_comp_param_1.bits.tx_buffer_depth + 1;
219
220 /* How many bytes we can actually ask */
221 rx_empty = (rx_buffer_depth - read_rxflr(reg_base)) - dw->rx_pending;
222
223 if (rx_empty < 0) {
224 /* RX FIFO expected to be full.
225 * So don't request any bytes, yet.
226 */
227 return;
228 }
229
230 /* How many empty slots in TX FIFO (as command queue) */
231 tx_empty = tx_buffer_depth - read_txflr(reg_base);
232
233 /* Figure out how many bytes we can request */
234 cnt = MIN(rx_buffer_depth, dw->request_bytes);
235 cnt = MIN(MIN(tx_empty, rx_empty), cnt);
236
237 while (cnt > 0) {
238 /* Tell controller to get another byte */
239 data = IC_DATA_CMD_CMD;
240
241 /* Send RESTART if needed */
242 if (dw->xfr_flags & I2C_MSG_RESTART) {
243 data |= IC_DATA_CMD_RESTART;
244 dw->xfr_flags &= ~(I2C_MSG_RESTART);
245 }
246
247 /* After receiving the last byte, send STOP if needed */
248 if ((dw->xfr_flags & I2C_MSG_STOP) && (dw->request_bytes == 1U)) {
249 data |= IC_DATA_CMD_STOP;
250 }
251
252 #ifdef CONFIG_I2C_TARGET
253 clear_bit_intr_mask_tx_empty(reg_base);
254 #endif /* CONFIG_I2C_TARGET */
255
256 write_cmd_data(data, reg_base);
257
258 dw->rx_pending++;
259 dw->request_bytes--;
260 cnt--;
261 }
262 }
263
i2c_dw_data_read(const struct device * dev)264 static void i2c_dw_data_read(const struct device *dev)
265 {
266 struct i2c_dw_dev_config *const dw = dev->data;
267 uint32_t reg_base = get_regs(dev);
268
269 #ifdef CONFIG_I2C_DW_LPSS_DMA
270 if (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
271 i2c_dw_idma_rx_transfer(dev);
272 dw->xfr_len = 0;
273 dw->rx_pending = 0;
274 }
275 #else
276 while (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
277 dw->xfr_buf[0] = (uint8_t)read_cmd_data(reg_base);
278
279 dw->xfr_buf++;
280 dw->xfr_len--;
281 dw->rx_pending--;
282
283 if (dw->xfr_len == 0U) {
284 break;
285 }
286 }
287 #endif
288 /* Nothing to receive anymore */
289 if (dw->xfr_len == 0U) {
290 dw->state &= ~I2C_DW_CMD_RECV;
291 return;
292 }
293 }
294
i2c_dw_data_send(const struct device * dev)295 static int i2c_dw_data_send(const struct device *dev)
296 {
297 struct i2c_dw_dev_config *const dw = dev->data;
298 uint32_t data = 0U;
299 uint32_t reg_base = get_regs(dev);
300
301 /* Nothing to send anymore, mask the interrupt */
302 if (dw->xfr_len == 0U) {
303 clear_bit_intr_mask_tx_empty(reg_base);
304
305 dw->state &= ~I2C_DW_CMD_SEND;
306
307 return 0;
308 }
309
310 while (test_bit_status_tfnt(reg_base) && (dw->xfr_len > 0)) {
311 /* We have something to transmit to a specific host */
312 data = dw->xfr_buf[0];
313
314 /* Send RESTART if needed */
315 if (dw->xfr_flags & I2C_MSG_RESTART) {
316 data |= IC_DATA_CMD_RESTART;
317 dw->xfr_flags &= ~(I2C_MSG_RESTART);
318 }
319
320 /* Send STOP if needed */
321 if ((dw->xfr_len == 1U) && (dw->xfr_flags & I2C_MSG_STOP)) {
322 data |= IC_DATA_CMD_STOP;
323 }
324
325 #ifdef CONFIG_I2C_DW_LPSS_DMA
326 i2c_dw_idma_tx_transfer(dev, data);
327 #else
328 write_cmd_data(data, reg_base);
329 #endif
330 dw->xfr_len--;
331 dw->xfr_buf++;
332
333 if (test_bit_intr_stat_tx_abrt(reg_base)) {
334 return -EIO;
335 }
336 }
337
338 return 0;
339 }
340
i2c_dw_transfer_complete(const struct device * dev)341 static inline void i2c_dw_transfer_complete(const struct device *dev)
342 {
343 struct i2c_dw_dev_config *const dw = dev->data;
344 uint32_t value;
345 uint32_t reg_base = get_regs(dev);
346
347 write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);
348 value = read_clr_intr(reg_base);
349
350 k_sem_give(&dw->device_sync_sem);
351 }
352
353 #ifdef CONFIG_I2C_TARGET
354 static inline uint8_t i2c_dw_read_byte_non_blocking(const struct device *dev);
355 static inline void i2c_dw_write_byte_non_blocking(const struct device *dev, uint8_t data);
356 static void i2c_dw_slave_read_clear_intr_bits(const struct device *dev);
357 #endif
358
i2c_dw_isr(const struct device * port)359 static void i2c_dw_isr(const struct device *port)
360 {
361 struct i2c_dw_dev_config *const dw = port->data;
362 union ic_interrupt_register intr_stat;
363 uint32_t value;
364 int ret = 0;
365 uint32_t reg_base = get_regs(port);
366
367 /* Cache ic_intr_stat for processing, so there is no need to read
368 * the register multiple times.
369 */
370 intr_stat.raw = read_intr_stat(reg_base);
371
372 /*
373 * Causes of an interrupt:
374 * - STOP condition is detected
375 * - Transfer is aborted
376 * - Transmit FIFO is empty
377 * - Transmit FIFO has overflowed
378 * - Receive FIFO is full
379 * - Receive FIFO has overflowed
380 * - Received FIFO has underrun
381 * - Transmit data is required (tx_req)
382 * - Receive data is available (rx_avail)
383 */
384
385 LOG_DBG("I2C: interrupt received");
386
387 /* Check if we are configured as a master device */
388 if (test_bit_con_master_mode(reg_base)) {
389 #ifdef CONFIG_I2C_DW_LPSS_DMA
390 uint32_t stat = sys_read32(reg_base + IDMA_REG_INTR_STS);
391
392 if (stat & IDMA_TX_RX_CHAN_MASK) {
393 const struct i2c_dw_rom_config *const rom = port->config;
394 /* Handle the DMA interrupt */
395 dma_intel_lpss_isr(rom->dma_dev);
396 }
397 #endif
398
399 /* Bail early if there is any error. */
400 if ((DW_INTR_STAT_TX_ABRT | DW_INTR_STAT_TX_OVER | DW_INTR_STAT_RX_OVER |
401 DW_INTR_STAT_RX_UNDER) &
402 intr_stat.raw) {
403 dw->state = I2C_DW_CMD_ERROR;
404 goto done;
405 }
406
407 /* Check if the RX FIFO reached threshold */
408 if (intr_stat.bits.rx_full) {
409 i2c_dw_data_read(port);
410 }
411
412 #ifdef CONFIG_I2C_TARGET
413 /* Check if the TX FIFO is ready for commands.
414 * TX FIFO also serves as command queue where read requests
415 * are written to TX FIFO.
416 */
417 if ((dw->xfr_flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
418 set_bit_intr_mask_tx_empty(reg_base);
419 }
420 #endif /* CONFIG_I2C_TARGET */
421
422 if (intr_stat.bits.tx_empty) {
423 if ((dw->xfr_flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
424 ret = i2c_dw_data_send(port);
425 } else {
426 i2c_dw_data_ask(port);
427 }
428
429 /* If STOP is not expected, finish processing this
430 * message if there is nothing left to do anymore.
431 */
432 if (((dw->xfr_len == 0U) && !(dw->xfr_flags & I2C_MSG_STOP)) ||
433 (ret != 0)) {
434 goto done;
435 }
436 }
437
438 /* STOP detected: finish processing this message */
439 if (intr_stat.bits.stop_det) {
440 value = read_clr_stop_det(reg_base);
441 goto done;
442 }
443
444 } else {
445 #ifdef CONFIG_I2C_TARGET
446 const struct i2c_target_callbacks *slave_cb = dw->slave_cfg->callbacks;
447 uint32_t slave_activity = test_bit_status_activity(reg_base);
448 uint8_t data;
449
450 i2c_dw_slave_read_clear_intr_bits(port);
451
452 if (intr_stat.bits.rx_full) {
453 if (dw->state != I2C_DW_CMD_SEND) {
454 dw->state = I2C_DW_CMD_SEND;
455 if (slave_cb->write_requested) {
456 slave_cb->write_requested(dw->slave_cfg);
457 }
458 }
459 /* FIFO needs to be drained here so we don't miss the next interrupt */
460 do {
461 data = i2c_dw_read_byte_non_blocking(port);
462 if (slave_cb->write_received) {
463 slave_cb->write_received(dw->slave_cfg, data);
464 }
465 } while (test_bit_status_rfne(reg_base));
466 }
467
468 if (intr_stat.bits.rd_req) {
469 if (slave_activity) {
470 read_clr_rd_req(reg_base);
471 dw->state = I2C_DW_CMD_RECV;
472 if (slave_cb->read_requested) {
473 slave_cb->read_requested(dw->slave_cfg, &data);
474 i2c_dw_write_byte_non_blocking(port, data);
475 }
476 if (slave_cb->read_processed) {
477 slave_cb->read_processed(dw->slave_cfg, &data);
478 }
479 }
480 }
481 #endif
482 }
483
484 return;
485
486 done:
487 i2c_dw_transfer_complete(port);
488 }
489
i2c_dw_setup(const struct device * dev,uint16_t slave_address)490 static int i2c_dw_setup(const struct device *dev, uint16_t slave_address)
491 {
492 struct i2c_dw_dev_config *const dw = dev->data;
493 uint32_t value;
494 union ic_con_register ic_con;
495 union ic_tar_register ic_tar;
496 uint32_t reg_base = get_regs(dev);
497
498 ic_con.raw = 0U;
499
500 /* Disable the device controller to be able set TAR */
501 clear_bit_enable_en(reg_base);
502
503 /* Disable interrupts */
504 write_intr_mask(0, reg_base);
505
506 /* Clear interrupts */
507 value = read_clr_intr(reg_base);
508
509 /* Set master or slave mode - (initialization = slave) */
510 if (I2C_MODE_CONTROLLER & dw->app_config) {
511 /*
512 * Make sure to set both the master_mode and slave_disable_bit
513 * to both 0 or both 1
514 */
515 LOG_DBG("I2C: host configured as Master Device");
516 ic_con.bits.master_mode = 1U;
517 ic_con.bits.slave_disable = 1U;
518 } else {
519 return -EINVAL;
520 }
521
522 ic_con.bits.restart_en = 1U;
523
524 /* Set addressing mode - (initialization = 7 bit) */
525 if (I2C_ADDR_10_BITS & dw->app_config) {
526 LOG_DBG("I2C: using 10-bit address");
527 ic_con.bits.addr_master_10bit = 1U;
528 ic_con.bits.addr_slave_10bit = 1U;
529 }
530
531 /* Setup the clock frequency and speed mode */
532 switch (I2C_SPEED_GET(dw->app_config)) {
533 case I2C_SPEED_STANDARD:
534 LOG_DBG("I2C: speed set to STANDARD");
535 write_ss_scl_lcnt(dw->lcnt, reg_base);
536 write_ss_scl_hcnt(dw->hcnt, reg_base);
537 ic_con.bits.speed = I2C_DW_SPEED_STANDARD;
538
539 break;
540 case I2C_SPEED_FAST:
541 __fallthrough;
542 case I2C_SPEED_FAST_PLUS:
543 LOG_DBG("I2C: speed set to FAST or FAST_PLUS");
544 write_fs_scl_lcnt(dw->lcnt, reg_base);
545 write_fs_scl_hcnt(dw->hcnt, reg_base);
546 ic_con.bits.speed = I2C_DW_SPEED_FAST;
547
548 break;
549 case I2C_SPEED_HIGH:
550 if (!dw->support_hs_mode) {
551 return -EINVAL;
552 }
553
554 LOG_DBG("I2C: speed set to HIGH");
555 write_hs_scl_lcnt(dw->lcnt, reg_base);
556 write_hs_scl_hcnt(dw->hcnt, reg_base);
557 ic_con.bits.speed = I2C_DW_SPEED_HIGH;
558
559 break;
560 default:
561 LOG_DBG("I2C: invalid speed requested");
562 return -EINVAL;
563 }
564
565 LOG_DBG("I2C: lcnt = %d", dw->lcnt);
566 LOG_DBG("I2C: hcnt = %d", dw->hcnt);
567
568 /* Set the IC_CON register */
569 write_con(ic_con.raw, reg_base);
570
571 /* Set RX fifo threshold level.
572 * Setting it to zero automatically triggers interrupt
573 * RX_FULL whenever there is data received.
574 *
575 * TODO: extend the threshold for multi-byte RX.
576 */
577 write_rx_tl(0, reg_base);
578
579 /* Set TX fifo threshold level.
580 * TX_EMPTY interrupt is triggered only when the
581 * TX FIFO is truly empty. So that we can let
582 * the controller do the transfers for longer period
583 * before we need to fill the FIFO again. This may
584 * cause some pauses during transfers, but this keeps
585 * the device from interrupting often.
586 */
587 write_tx_tl(0, reg_base);
588
589 ic_tar.raw = read_tar(reg_base);
590
591 if (test_bit_con_master_mode(reg_base)) {
592 /* Set address of target slave */
593 ic_tar.bits.ic_tar = slave_address;
594 } else {
595 /* Set slave address for device */
596 write_sar(slave_address, reg_base);
597 }
598
599 /* If I2C is being operated in master mode and I2C_DYNAMIC_TAR_UPDATE
600 * configuration parameter is set to Yes (1), the ic_10bitaddr_master
601 * bit in ic_tar register would control whether the DW_apb_i2c starts
602 * its transfers in 7-bit or 10-bit addressing mode.
603 */
604 if (I2C_MODE_CONTROLLER & dw->app_config) {
605 if (I2C_ADDR_10_BITS & dw->app_config) {
606 ic_tar.bits.ic_10bitaddr_master = 1U;
607 } else {
608 ic_tar.bits.ic_10bitaddr_master = 0U;
609 }
610 }
611
612 write_tar(ic_tar.raw, reg_base);
613
614 return 0;
615 }
616
i2c_dw_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t slave_address)617 static int i2c_dw_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
618 uint16_t slave_address)
619 {
620 struct i2c_dw_dev_config *const dw = dev->data;
621 struct i2c_msg *cur_msg = msgs;
622 uint8_t msg_left = num_msgs;
623 uint8_t pflags;
624 int ret;
625 uint32_t reg_base = get_regs(dev);
626 uint32_t value = 0;
627
628 __ASSERT_NO_MSG(msgs);
629 if (!num_msgs) {
630 return 0;
631 }
632
633 ret = k_mutex_lock(&dw->bus_mutex, K_FOREVER);
634 if (ret != 0) {
635 return ret;
636 }
637
638 /* First step, check if there is current activity */
639 if (test_bit_status_activity(reg_base) || (dw->state & I2C_DW_BUSY)) {
640 ret = -EBUSY;
641 goto error;
642 }
643
644 dw->state |= I2C_DW_BUSY;
645
646 ret = i2c_dw_setup(dev, slave_address);
647 if (ret) {
648 goto error;
649 }
650
651 /* Enable controller */
652 set_bit_enable_en(reg_base);
653
654 /*
655 * While waiting at device_sync_sem, kernel can switch to idle
656 * task which in turn can call pm_system_suspend() hook of Power
657 * Management App (PMA).
658 * pm_device_busy_set() call here, would indicate to PMA that it should
659 * not execute PM policies that would turn off this ip block, causing an
660 * ongoing hw transaction to be left in an inconsistent state.
661 * Note : This is just a sample to show a possible use of the API, it is
662 * upto the driver expert to see, if he actually needs it here, or
663 * somewhere else, or not needed as the driver's suspend()/resume()
664 * can handle everything
665 */
666 pm_device_busy_set(dev);
667
668 /* Process all the messages */
669 while (msg_left > 0) {
670 /* Workaround for I2C scanner as DW HW does not support 0 byte transfers.*/
671 if ((cur_msg->len == 0) && (cur_msg->buf != NULL)) {
672 cur_msg->len = 1;
673 }
674
675 pflags = dw->xfr_flags;
676
677 dw->xfr_buf = cur_msg->buf;
678 dw->xfr_len = cur_msg->len;
679 dw->xfr_flags = cur_msg->flags;
680 dw->rx_pending = 0U;
681
682 /* Need to RESTART if changing transfer direction */
683 if ((pflags & I2C_MSG_RW_MASK) != (dw->xfr_flags & I2C_MSG_RW_MASK)) {
684 dw->xfr_flags |= I2C_MSG_RESTART;
685 }
686
687 dw->state &= ~(I2C_DW_CMD_SEND | I2C_DW_CMD_RECV);
688
689 if ((dw->xfr_flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
690 dw->state |= I2C_DW_CMD_SEND;
691 dw->request_bytes = 0U;
692 } else {
693 dw->state |= I2C_DW_CMD_RECV;
694 dw->request_bytes = dw->xfr_len;
695 }
696
697 /* Enable interrupts to trigger ISR */
698 if (test_bit_con_master_mode(reg_base)) {
699 /* Enable necessary interrupts */
700 write_intr_mask((DW_ENABLE_TX_INT_I2C_MASTER | DW_ENABLE_RX_INT_I2C_MASTER),
701 reg_base);
702 } else {
703 /* Enable necessary interrupts */
704 write_intr_mask(DW_ENABLE_TX_INT_I2C_SLAVE, reg_base);
705 }
706
707 /* Wait for transfer to be done */
708 ret = k_sem_take(&dw->device_sync_sem, K_MSEC(CONFIG_I2C_DW_RW_TIMEOUT_MS));
709 if (ret != 0) {
710 write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);
711 value = read_clr_intr(reg_base);
712 break;
713 }
714
715 if (dw->state & I2C_DW_CMD_ERROR) {
716 ret = -EIO;
717 break;
718 }
719
720 /* Something wrong if there is something left to do */
721 if (dw->xfr_len > 0) {
722 ret = -EIO;
723 break;
724 }
725
726 cur_msg++;
727 msg_left--;
728 }
729
730 pm_device_busy_clear(dev);
731
732 error:
733 dw->state = I2C_DW_STATE_READY;
734 k_mutex_unlock(&dw->bus_mutex);
735
736 return ret;
737 }
738
i2c_dw_runtime_configure(const struct device * dev,uint32_t config)739 static int i2c_dw_runtime_configure(const struct device *dev, uint32_t config)
740 {
741 struct i2c_dw_dev_config *const dw = dev->data;
742 const struct i2c_dw_rom_config *const rom = dev->config;
743 uint32_t value = 0U;
744 uint32_t rc = 0U;
745 uint32_t reg_base = get_regs(dev);
746
747 dw->app_config = config;
748
749 /* Make sure we have a supported speed for the DesignWare model */
750 /* and have setup the clock frequency and speed mode */
751 switch (I2C_SPEED_GET(dw->app_config)) {
752 case I2C_SPEED_STANDARD:
753 /* Following the directions on DW spec page 59, IC_SS_SCL_LCNT
754 * must have register values larger than IC_FS_SPKLEN + 7
755 */
756 value = I2C_STD_LCNT + rom->lcnt_offset;
757 if (value <= (read_fs_spklen(reg_base) + 7)) {
758 value = read_fs_spklen(reg_base) + 8;
759 }
760
761 dw->lcnt = value;
762
763 /* Following the directions on DW spec page 59, IC_SS_SCL_HCNT
764 * must have register values larger than IC_FS_SPKLEN + 5
765 */
766 value = I2C_STD_HCNT + rom->hcnt_offset;
767 if (value <= (read_fs_spklen(reg_base) + 5)) {
768 value = read_fs_spklen(reg_base) + 6;
769 }
770
771 dw->hcnt = value;
772 break;
773 case I2C_SPEED_FAST:
774 /*
775 * Following the directions on DW spec page 59, IC_FS_SCL_LCNT
776 * must have register values larger than IC_FS_SPKLEN + 7
777 */
778 value = I2C_FS_LCNT + rom->lcnt_offset;
779 if (value <= (read_fs_spklen(reg_base) + 7)) {
780 value = read_fs_spklen(reg_base) + 8;
781 }
782
783 dw->lcnt = value;
784
785 /*
786 * Following the directions on DW spec page 59, IC_FS_SCL_HCNT
787 * must have register values larger than IC_FS_SPKLEN + 5
788 */
789 value = I2C_FS_HCNT + rom->hcnt_offset;
790 if (value <= (read_fs_spklen(reg_base) + 5)) {
791 value = read_fs_spklen(reg_base) + 6;
792 }
793
794 dw->hcnt = value;
795 break;
796 case I2C_SPEED_FAST_PLUS:
797 /*
798 * Following the directions on DW spec page 59, IC_FS_SCL_LCNT
799 * must have register values larger than IC_FS_SPKLEN + 7
800 */
801 value = I2C_FSP_LCNT + rom->lcnt_offset;
802 if (value <= (read_fs_spklen(reg_base) + 7)) {
803 value = read_fs_spklen(reg_base) + 8;
804 }
805
806 dw->lcnt = value;
807
808 /*
809 * Following the directions on DW spec page 59, IC_FS_SCL_HCNT
810 * must have register values larger than IC_FS_SPKLEN + 5
811 */
812 value = I2C_FSP_HCNT + rom->hcnt_offset;
813 if (value <= (read_fs_spklen(reg_base) + 5)) {
814 value = read_fs_spklen(reg_base) + 6;
815 }
816
817 dw->hcnt = value;
818 break;
819 case I2C_SPEED_HIGH:
820 if (dw->support_hs_mode) {
821 value = I2C_HS_LCNT + rom->lcnt_offset;
822 if (value <= (read_hs_spklen(reg_base) + 7)) {
823 value = read_hs_spklen(reg_base) + 8;
824 }
825
826 dw->lcnt = value;
827
828 value = I2C_HS_HCNT + rom->hcnt_offset;
829 if (value <= (read_hs_spklen(reg_base) + 5)) {
830 value = read_hs_spklen(reg_base) + 6;
831 }
832
833 dw->hcnt = value;
834 } else {
835 rc = -EINVAL;
836 }
837 break;
838 default:
839 /* TODO change */
840 rc = -EINVAL;
841 }
842
843 /*
844 * Clear any interrupts currently waiting in the controller
845 */
846 value = read_clr_intr(reg_base);
847
848 /*
849 * TEMPORARY HACK - The I2C does not work in any mode other than Master
850 * currently. This "hack" forces us to always be configured for master
851 * mode, until we can verify that Slave mode works correctly.
852 */
853 dw->app_config |= I2C_MODE_CONTROLLER;
854
855 return rc;
856 }
857
858 #ifdef CONFIG_I2C_TARGET
i2c_dw_read_byte_non_blocking(const struct device * dev)859 static inline uint8_t i2c_dw_read_byte_non_blocking(const struct device *dev)
860 {
861 uint32_t reg_base = get_regs(dev);
862
863 if (!test_bit_status_rfne(reg_base)) { /* Rx FIFO must not be empty */
864 return -EIO;
865 }
866
867 return (uint8_t)read_cmd_data(reg_base);
868 }
869
i2c_dw_write_byte_non_blocking(const struct device * dev,uint8_t data)870 static inline void i2c_dw_write_byte_non_blocking(const struct device *dev, uint8_t data)
871 {
872 uint32_t reg_base = get_regs(dev);
873
874 if (!test_bit_status_tfnt(reg_base)) { /* Tx FIFO must not be full */
875 return;
876 }
877
878 write_cmd_data(data, reg_base);
879 }
880
i2c_dw_set_master_mode(const struct device * dev)881 static int i2c_dw_set_master_mode(const struct device *dev)
882 {
883 union ic_comp_param_1_register ic_comp_param_1;
884 uint32_t reg_base = get_regs(dev);
885 union ic_con_register ic_con;
886
887 clear_bit_enable_en(reg_base);
888
889 ic_con.bits.master_mode = 1U;
890 ic_con.bits.slave_disable = 1U;
891 ic_con.bits.rx_fifo_full = 0U;
892 write_con(ic_con.raw, reg_base);
893
894 set_bit_enable_en(reg_base);
895
896 ic_comp_param_1.raw = read_comp_param_1(reg_base);
897
898 write_tx_tl(ic_comp_param_1.bits.tx_buffer_depth + 1, reg_base);
899 write_rx_tl(ic_comp_param_1.bits.rx_buffer_depth + 1, reg_base);
900
901 return 0;
902 }
903
i2c_dw_set_slave_mode(const struct device * dev,uint8_t addr)904 static int i2c_dw_set_slave_mode(const struct device *dev, uint8_t addr)
905 {
906 uint32_t reg_base = get_regs(dev);
907 union ic_con_register ic_con;
908
909 ic_con.raw = read_con(reg_base);
910
911 clear_bit_enable_en(reg_base);
912
913 ic_con.bits.master_mode = 0U;
914 ic_con.bits.slave_disable = 0U;
915 ic_con.bits.rx_fifo_full = 1U;
916 ic_con.bits.restart_en = 1U;
917 ic_con.bits.stop_det = 1U;
918
919 write_con(ic_con.raw, reg_base);
920 write_sar(addr, reg_base);
921 write_intr_mask(~DW_INTR_MASK_RESET, reg_base);
922
923 set_bit_enable_en(reg_base);
924
925 write_tx_tl(0, reg_base);
926 write_rx_tl(0, reg_base);
927
928 LOG_DBG("I2C: Host registered as Slave Device");
929
930 return 0;
931 }
932
i2c_dw_slave_register(const struct device * dev,struct i2c_target_config * cfg)933 static int i2c_dw_slave_register(const struct device *dev, struct i2c_target_config *cfg)
934 {
935 struct i2c_dw_dev_config *const dw = dev->data;
936 uint32_t reg_base = get_regs(dev);
937 int ret;
938
939 dw->slave_cfg = cfg;
940 ret = i2c_dw_set_slave_mode(dev, cfg->address);
941 write_intr_mask(DW_INTR_MASK_RX_FULL | DW_INTR_MASK_RD_REQ | DW_INTR_MASK_TX_ABRT |
942 DW_INTR_MASK_STOP_DET,
943 reg_base);
944
945 return ret;
946 }
947
i2c_dw_slave_unregister(const struct device * dev,struct i2c_target_config * cfg)948 static int i2c_dw_slave_unregister(const struct device *dev, struct i2c_target_config *cfg)
949 {
950 struct i2c_dw_dev_config *const dw = dev->data;
951 int ret;
952
953 dw->state = I2C_DW_STATE_READY;
954 ret = i2c_dw_set_master_mode(dev);
955
956 return ret;
957 }
958
i2c_dw_slave_read_clear_intr_bits(const struct device * dev)959 static void i2c_dw_slave_read_clear_intr_bits(const struct device *dev)
960 {
961 struct i2c_dw_dev_config *const dw = dev->data;
962 union ic_interrupt_register intr_stat;
963 uint32_t reg_base = get_regs(dev);
964
965 const struct i2c_target_callbacks *slave_cb = dw->slave_cfg->callbacks;
966
967 intr_stat.raw = read_intr_stat(reg_base);
968
969 if (intr_stat.bits.tx_abrt) {
970 read_clr_tx_abrt(reg_base);
971 dw->state = I2C_DW_STATE_READY;
972 }
973
974 if (intr_stat.bits.rx_under) {
975 read_clr_rx_under(reg_base);
976 dw->state = I2C_DW_STATE_READY;
977 }
978
979 if (intr_stat.bits.rx_over) {
980 read_clr_rx_over(reg_base);
981 dw->state = I2C_DW_STATE_READY;
982 }
983
984 if (intr_stat.bits.tx_over) {
985 read_clr_tx_over(reg_base);
986 dw->state = I2C_DW_STATE_READY;
987 }
988
989 if (intr_stat.bits.rx_done) {
990 read_clr_rx_done(reg_base);
991 dw->state = I2C_DW_STATE_READY;
992 }
993
994 if (intr_stat.bits.activity) {
995 read_clr_activity(reg_base);
996 dw->state = I2C_DW_STATE_READY;
997 }
998
999 if (intr_stat.bits.stop_det) {
1000 read_clr_stop_det(reg_base);
1001 dw->state = I2C_DW_STATE_READY;
1002 if (slave_cb->stop) {
1003 slave_cb->stop(dw->slave_cfg);
1004 }
1005 }
1006
1007 if (intr_stat.bits.start_det) {
1008 read_clr_start_det(reg_base);
1009 dw->state = I2C_DW_STATE_READY;
1010 }
1011
1012 if (intr_stat.bits.gen_call) {
1013 read_clr_gen_call(reg_base);
1014 dw->state = I2C_DW_STATE_READY;
1015 }
1016 }
1017 #endif /* CONFIG_I2C_TARGET */
1018
1019 static DEVICE_API(i2c, funcs) = {
1020 .configure = i2c_dw_runtime_configure,
1021 .transfer = i2c_dw_transfer,
1022 #ifdef CONFIG_I2C_TARGET
1023 .target_register = i2c_dw_slave_register,
1024 .target_unregister = i2c_dw_slave_unregister,
1025 #endif /* CONFIG_I2C_TARGET */
1026 #ifdef CONFIG_I2C_RTIO
1027 .iodev_submit = i2c_iodev_submit_fallback,
1028 #endif
1029 };
1030
i2c_dw_initialize(const struct device * dev)1031 static int i2c_dw_initialize(const struct device *dev)
1032 {
1033 const struct i2c_dw_rom_config *const rom = dev->config;
1034 struct i2c_dw_dev_config *const dw = dev->data;
1035 union ic_con_register ic_con;
1036 int ret = 0;
1037
1038 #if defined(CONFIG_RESET)
1039 if (rom->reset.dev) {
1040 ret = reset_line_toggle_dt(&rom->reset);
1041 if (ret) {
1042 return ret;
1043 }
1044 }
1045 #endif
1046
1047 #if defined(CONFIG_PINCTRL)
1048 ret = pinctrl_apply_state(rom->pcfg, PINCTRL_STATE_DEFAULT);
1049 if (ret) {
1050 return ret;
1051 }
1052 #endif
1053
1054 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
1055 if (rom->pcie) {
1056 struct pcie_bar mbar;
1057
1058 if (rom->pcie->bdf == PCIE_BDF_NONE) {
1059 return -EINVAL;
1060 }
1061
1062 pcie_probe_mbar(rom->pcie->bdf, 0, &mbar);
1063 pcie_set_cmd(rom->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
1064
1065 device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size, K_MEM_CACHE_NONE);
1066
1067 pcie_set_cmd(rom->pcie->bdf, PCIE_CONF_CMDSTAT_MASTER, true);
1068
1069 #ifdef CONFIG_I2C_DW_LPSS_DMA
1070 uintptr_t base;
1071
1072 base = DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET;
1073 dma_intel_lpss_set_base(rom->dma_dev, base);
1074 dma_intel_lpss_setup(rom->dma_dev);
1075
1076 /* Assign physical & virtual address to dma instance */
1077 dw->phy_addr = mbar.phys_addr;
1078 dw->base_addr = (uint32_t)(DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET);
1079 sys_write32((uint32_t)dw->phy_addr,
1080 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_LOW);
1081 sys_write32((uint32_t)(dw->phy_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT),
1082 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_HI);
1083 LOG_DBG("i2c instance physical addr: [0x%lx], virtual addr: [0x%lx]", dw->phy_addr,
1084 dw->base_addr);
1085 #endif
1086 } else
1087 #endif
1088 {
1089 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
1090 }
1091
1092 k_sem_init(&dw->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1093 k_mutex_init(&dw->bus_mutex);
1094
1095 uint32_t reg_base = get_regs(dev);
1096
1097 clear_bit_enable_en(reg_base);
1098
1099 /* verify that we have a valid DesignWare register first */
1100 if (read_comp_type(reg_base) != I2C_DW_MAGIC_KEY) {
1101 LOG_DBG("I2C: DesignWare magic key not found, check base "
1102 "address. Stopping initialization");
1103 return -EIO;
1104 }
1105
1106 /*
1107 * grab the default value on initialization. This should be set to the
1108 * IC_MAX_SPEED_MODE in the hardware. If it does support high speed we
1109 * can move provide support for it
1110 */
1111 ic_con.raw = read_con(reg_base);
1112 if (ic_con.bits.speed == I2C_DW_SPEED_HIGH) {
1113 LOG_DBG("I2C: high speed supported");
1114 dw->support_hs_mode = true;
1115 } else {
1116 LOG_DBG("I2C: high speed NOT supported");
1117 dw->support_hs_mode = false;
1118 }
1119
1120 rom->config_func(dev);
1121
1122 dw->app_config = I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(rom->bitrate);
1123
1124 if (i2c_dw_runtime_configure(dev, dw->app_config) != 0) {
1125 LOG_DBG("I2C: Cannot set default configuration");
1126 return -EIO;
1127 }
1128
1129 dw->state = I2C_DW_STATE_READY;
1130
1131 return ret;
1132 }
1133
1134 #if defined(CONFIG_PINCTRL)
1135 #define PINCTRL_DW_DEFINE(n) PINCTRL_DT_INST_DEFINE(n)
1136 #define PINCTRL_DW_CONFIG(n) .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
1137 #else
1138 #define PINCTRL_DW_DEFINE(n)
1139 #define PINCTRL_DW_CONFIG(n)
1140 #endif
1141
1142 #if defined(CONFIG_RESET)
1143 #define RESET_DW_CONFIG(n) \
1144 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, resets), \
1145 (.reset = RESET_DT_SPEC_INST_GET(n),))
1146 #else
1147 #define RESET_DW_CONFIG(n)
1148 #endif
1149
1150 #define I2C_DW_INIT_PCIE0(n)
1151 #define I2C_DW_INIT_PCIE1(n) DEVICE_PCIE_INST_INIT(n, pcie),
1152 #define I2C_DW_INIT_PCIE(n) _CONCAT(I2C_DW_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1153
1154 #define I2C_DEFINE_PCIE0(n)
1155 #define I2C_DEFINE_PCIE1(n) DEVICE_PCIE_INST_DECLARE(n)
1156 #define I2C_PCIE_DEFINE(n) _CONCAT(I2C_DEFINE_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1157
1158 #define I2C_DW_IRQ_FLAGS_SENSE0(n) 0
1159 #define I2C_DW_IRQ_FLAGS_SENSE1(n) DT_INST_IRQ(n, sense)
1160 #define I2C_DW_IRQ_FLAGS_SENSE(n) _CONCAT(I2C_DW_IRQ_FLAGS_SENSE, DT_INST_IRQ_HAS_CELL(n, sense))
1161 #define I2C_DW_IRQ_FLAGS(n) I2C_DW_IRQ_FLAGS_SENSE(n)(n)
1162
1163 /* not PCI(e) */
1164 #define I2C_DW_IRQ_CONFIG_PCIE0(n) \
1165 static void i2c_config_##n(const struct device *port) \
1166 { \
1167 ARG_UNUSED(port); \
1168 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_dw_isr, \
1169 DEVICE_DT_INST_GET(n), I2C_DW_IRQ_FLAGS(n)); \
1170 irq_enable(DT_INST_IRQN(n)); \
1171 }
1172
1173 /* PCI(e) with auto IRQ detection */
1174 #define I2C_DW_IRQ_CONFIG_PCIE1(n) \
1175 static void i2c_config_##n(const struct device *port) \
1176 { \
1177 BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
1178 "Only runtime IRQ configuration is supported"); \
1179 BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
1180 "DW I2C PCI needs CONFIG_DYNAMIC_INTERRUPTS"); \
1181 const struct i2c_dw_rom_config *const dev_cfg = port->config; \
1182 unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
1183 if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
1184 return; \
1185 } \
1186 pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, DT_INST_IRQ(n, priority), \
1187 (void (*)(const void *))i2c_dw_isr, \
1188 DEVICE_DT_INST_GET(n), I2C_DW_IRQ_FLAGS(n)); \
1189 pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
1190 }
1191
1192 #define I2C_DW_IRQ_CONFIG(n) _CONCAT(I2C_DW_IRQ_CONFIG_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1193
1194 #define I2C_CONFIG_REG_INIT_PCIE0(n) DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),
1195 #define I2C_CONFIG_REG_INIT_PCIE1(n)
1196 #define I2C_CONFIG_REG_INIT(n) _CONCAT(I2C_CONFIG_REG_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1197
1198 #define I2C_CONFIG_DMA_INIT(n) \
1199 COND_CODE_1(CONFIG_I2C_DW_LPSS_DMA, \
1200 (COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
1201 (.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(n, 0)),), \
1202 ())), ())
1203
1204 #define I2C_DEVICE_INIT_DW(n) \
1205 PINCTRL_DW_DEFINE(n); \
1206 I2C_PCIE_DEFINE(n); \
1207 static void i2c_config_##n(const struct device *port); \
1208 static const struct i2c_dw_rom_config i2c_config_dw_##n = { \
1209 I2C_CONFIG_REG_INIT(n).config_func = i2c_config_##n, \
1210 .bitrate = DT_INST_PROP(n, clock_frequency), \
1211 .lcnt_offset = (int16_t)DT_INST_PROP_OR(n, lcnt_offset, 0), \
1212 .hcnt_offset = (int16_t)DT_INST_PROP_OR(n, hcnt_offset, 0), \
1213 RESET_DW_CONFIG(n) PINCTRL_DW_CONFIG(n) I2C_DW_INIT_PCIE(n) \
1214 I2C_CONFIG_DMA_INIT(n)}; \
1215 static struct i2c_dw_dev_config i2c_##n##_runtime; \
1216 I2C_DEVICE_DT_INST_DEFINE(n, i2c_dw_initialize, NULL, &i2c_##n##_runtime, \
1217 &i2c_config_dw_##n, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
1218 &funcs); \
1219 I2C_DW_IRQ_CONFIG(n)
1220
1221 DT_INST_FOREACH_STATUS_OKAY(I2C_DEVICE_INIT_DW)
1222
