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Searched defs:CPUSS_RAM2_CTL0 (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/
Dstartup_cm0plus.S27 #define CPUSS_RAM2_CTL0 0x402013a0 macro
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/
Dstartup_cm0plus.s35 CPUSS_RAM2_CTL0 EQU 0x402013a0 define
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/
Dstartup_cm0plus.s56 CPUSS_RAM2_CTL0 EQU 0x402013a0 define
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h791 #define CPUSS_RAM2_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_devi… macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h524 #define CPUSS_RAM2_CTL0 ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_CTL0)) macro