Home
last modified time | relevance | path

Searched refs:mode (Results 1 – 25 of 213) sorted by relevance

123456789

/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/codesafe/src/crypto_api/cc3x_sym/api/
Dmbedtls_hash_ext_dma.c39 hashMode_t mode; in mbedtls_hash_ext_dma_init() local
44 mode = HASH_SHA1; in mbedtls_hash_ext_dma_init()
47 mode = HASH_SHA224; in mbedtls_hash_ext_dma_init()
50 mode = HASH_SHA256; in mbedtls_hash_ext_dma_init()
61 drvRc = InitHashExtDma(mode, dataSize); in mbedtls_hash_ext_dma_init()
74 hashMode_t mode; in mbedtls_hash_ext_dma_finish() local
89 mode = HASH_SHA1; in mbedtls_hash_ext_dma_finish()
92 mode = HASH_SHA224; in mbedtls_hash_ext_dma_finish()
95 mode = HASH_SHA256; in mbedtls_hash_ext_dma_finish()
102 error = FinishHashExtDma(mode, digestBuffer); in mbedtls_hash_ext_dma_finish()
Dmbedtls_aes_ext_dma.c61 aesMode_t mode; in mbedtls_aes_ext_dma_init() local
101 mode = CC2DriverAesMode(operationMode); in mbedtls_aes_ext_dma_init()
103 drvRc = AesExtDmaInit((cryptoDirection_t)encryptDecryptFlag, mode, keySizeId); in mbedtls_aes_ext_dma_init()
117 aesMode_t mode; in mbedtls_aes_ext_dma_set_key() local
153 mode = CC2DriverAesMode(operationMode); in mbedtls_aes_ext_dma_set_key()
155 drvRc = AesExtDmaSetKey(mode, keyBuffer, keySizeId); in mbedtls_aes_ext_dma_set_key()
219 aesMode_t mode; in mbedtls_aes_ext_dma_set_iv() local
237 mode = CC2DriverAesMode(operationMode); in mbedtls_aes_ext_dma_set_iv()
240 drvRc = AesExtDmaSetIv(mode, ivBuff); in mbedtls_aes_ext_dma_set_iv()
263 aesMode_t mode; in mbedtls_aes_ext_dma_finish() local
[all …]
/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/codesafe/src/mbedtls_api/
Daes_alt.c161 int mode, in mbedtls_aes_crypt_ecb() argument
175 if (MBEDTLS_AES_ENCRYPT != mode && MBEDTLS_AES_DECRYPT != mode) in mbedtls_aes_crypt_ecb()
177 CC_PAL_LOG_ERR("Mode %d is not supported\n", mode); in mbedtls_aes_crypt_ecb()
183 if (((MBEDTLS_AES_ENCRYPT == mode) && (CRYPTO_DIRECTION_ENCRYPT != aesCtx->dir)) || in mbedtls_aes_crypt_ecb()
184 ((MBEDTLS_AES_DECRYPT == mode) && (CRYPTO_DIRECTION_DECRYPT != aesCtx->dir))) in mbedtls_aes_crypt_ecb()
187 … CC_PAL_LOG_ERR("Key & operation mode mismatch: mode = %d. aesCtx->dir = %d\n", mode, aesCtx->dir); in mbedtls_aes_crypt_ecb()
191 aesCtx->mode = CIPHER_ECB; in mbedtls_aes_crypt_ecb()
215 int mode, in mbedtls_aes_crypt_cbc() argument
238 if (MBEDTLS_AES_ENCRYPT != mode && MBEDTLS_AES_DECRYPT != mode) in mbedtls_aes_crypt_cbc()
240 CC_PAL_LOG_ERR("Mode %d is not supported\n", mode); in mbedtls_aes_crypt_cbc()
[all …]
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Driver/DriverTemplates/
DDriver_ETH_PHY.c75 static int32_t ARM_ETH_PHY_SetMode(uint32_t mode) in ARM_ETH_PHY_SetMode() argument
77 switch (mode & ARM_ETH_PHY_SPEED_Msk) in ARM_ETH_PHY_SetMode()
87 switch (mode & ARM_ETH_PHY_DUPLEX_Msk) in ARM_ETH_PHY_SetMode()
95 if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE) in ARM_ETH_PHY_SetMode()
99 if (mode & ARM_ETH_PHY_LOOPBACK) in ARM_ETH_PHY_SetMode()
103 if (mode & ARM_ETH_PHY_ISOLATE) in ARM_ETH_PHY_SetMode()
/trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/
Dcycfg_qspi_memslot.c37 .mode = 0x01U,
55 .mode = 0xFFFFFFFFU,
73 .mode = 0xFFFFFFFFU,
91 .mode = 0xFFFFFFFFU,
109 .mode = 0xFFFFFFFFU,
127 .mode = 0xFFFFFFFFU,
145 .mode = 0xFFFFFFFFU,
163 .mode = 0xFFFFFFFFU,
181 .mode = 0xFFFFFFFFU,
/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/host/src/cc3x_sbromlib/
Dbsv_crypto_driver.h129 bsvAesMode_t mode,
140 bsvCryptoMode_t mode,
144 bsvCryptoMode_t mode,
154 bsvCryptoMode_t mode,
170 bsvAesMode_t mode,
181 bsvAesMode_t mode,
187 bsvAesMode_t mode,
196 bsvAesMode_t mode,
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Core/Source/
Dirq_ctrl_gic.c146 __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { in IRQ_SetMode() argument
155 val = (mode & IRQ_MODE_TRIG_Msk); in IRQ_SetMode()
166 val = (mode & IRQ_MODE_MODEL_Msk); in IRQ_SetMode()
172 val = mode & IRQ_MODE_TYPE_Msk; in IRQ_SetMode()
179 val = mode & IRQ_MODE_DOMAIN_Msk; in IRQ_SetMode()
197 val = mode & IRQ_MODE_CPU_Msk; in IRQ_SetMode()
222 uint32_t mode; in IRQ_GetMode() local
226 mode = IRQ_MODE_TYPE_IRQ; in IRQ_GetMode()
233 mode |= IRQ_MODE_TRIG_EDGE; in IRQ_GetMode()
236 mode |= IRQ_MODE_TRIG_LEVEL; in IRQ_GetMode()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/native_drivers/
Dintegrity_checker_drv.c108 enum integrity_checker_mode_t mode, in check_mode_is_supported() argument
113 uint32_t bitmask = (1 << (mode + 3 * (is_compute))); in check_mode_is_supported()
115 if (mode > INTEGRITY_CHECKER_MODE_SHA256) { in check_mode_is_supported()
154 enum integrity_checker_mode_t mode, in integrity_checker_compute_value() argument
168 err = check_mode_is_supported(dev, mode, true); in integrity_checker_compute_value()
173 if (value_size != mode_sizes[mode]) { in integrity_checker_compute_value()
195 iccval |= (mode & 0b111) << 1; in integrity_checker_compute_value()
222 for (int idx = 0; idx < mode_sizes[mode] / sizeof(uint32_t); idx++) { in integrity_checker_compute_value()
228 *value_len = mode_sizes[mode]; in integrity_checker_compute_value()
235 enum integrity_checker_mode_t mode, in integrity_checker_check_value() argument
[all …]
/trusted-firmware-m-latest/platform/ext/accelerator/cc312/cc312-rom/psa_driver_api/src/
Dcc3xx_internal_cipher.c55 cc3xx_aes_mode_t mode; in cc3xx_internal_aes_setup() local
68 mode = CC3XX_AES_MODE_CBC; in cc3xx_internal_aes_setup()
71 mode = CC3XX_AES_MODE_ECB; in cc3xx_internal_aes_setup()
74 mode = CC3XX_AES_MODE_CTR; in cc3xx_internal_aes_setup()
80 mode = CC3XX_AES_MODE_GCM; in cc3xx_internal_aes_setup()
83 mode = CC3XX_AES_MODE_CCM; in cc3xx_internal_aes_setup()
91 state->mode = mode; in cc3xx_internal_aes_setup()
124 cc3xx_chacha_mode_t mode; in cc3xx_internal_chacha_setup() local
132 mode = CC3XX_CHACHA_MODE_CHACHA; in cc3xx_internal_chacha_setup()
143 mode = CC3XX_CHACHA_MODE_CHACHA; in cc3xx_internal_chacha_setup()
[all …]
/trusted-firmware-m-latest/platform/ext/accelerator/cc312/cc312-rom/
Dcc3xx_chacha.c103 if (chacha_state.mode == CC3XX_CHACHA_MODE_CHACHA_POLY1305) { in chacha_init_from_state()
105 P_CC3XX->chacha.chacha_control_reg |= (chacha_state.mode & 0b1) << 2; in chacha_init_from_state()
112 cc3xx_chacha_mode_t mode, in cc3xx_lowlevel_chacha20_init() argument
121 if (mode == CC3XX_CHACHA_MODE_CHACHA_POLY1305) { in cc3xx_lowlevel_chacha20_init()
125 assert(mode == CC3XX_CHACHA_MODE_CHACHA); in cc3xx_lowlevel_chacha20_init()
131 chacha_state.mode = mode; in cc3xx_lowlevel_chacha20_init()
161 if (chacha_state.mode == CC3XX_CHACHA_MODE_CHACHA_POLY1305) { in cc3xx_lowlevel_chacha20_init()
183 if (chacha_state.mode == CC3XX_CHACHA_MODE_CHACHA_POLY1305) { in cc3xx_lowlevel_chacha20_get_state()
198 if (chacha_state.mode == CC3XX_CHACHA_MODE_CHACHA_POLY1305) { in cc3xx_lowlevel_chacha20_set_state()
231 if (chacha_state.mode == CC3XX_CHACHA_MODE_CHACHA_POLY1305) { in cc3xx_lowlevel_chacha20_update_authed_data()
[all …]
/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/utils/src/cc3x_boot_cert/examples/enabler_cert/
Dsb_enabler_dbg_cert.cfg14 #rma-mode = Set to non-zero value to use this certificate for RMA mode entry. Mandatory…
16 … OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
17 … Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is set, the HW keys rese…
18 …OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
19 # Cannot be defined together with rma-mode.
23 # Mandatory if rma-mode is defined (for rma-mode, only two-level certificate …
25 # Must be empty if rma-mode is defined.
32 #rma-mode =
Dsb_enabler_dbg_cert_no_pwd.cfg14 #rma-mode = Set to non-zero value to use this certificate for RMA mode entry. Mandatory…
16 … OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
17 … Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is set, the HW keys rese…
18 …OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
19 # Cannot be defined together with rma-mode.
23 # Mandatory if rma-mode is defined (for rma-mode, only two-level certificate …
25 # Must be empty if rma-mode is defined.
32 #rma-mode =
Dx509_sb_enabler_dbg_cert.cfg14 #rma-mode = Set to non-zero value to use this certificate for RMA mode entry. Mandatory…
16 … OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
17 … Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is set, the HW keys rese…
18 …OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
19 # Cannot be defined together with rma-mode.
23 # Mandatory if rma-mode is defined (for rma-mode, only two-level certificate …
25 # Must be empty if rma-mode is defined.
32 #rma-mode =
Dsb_enabler_dbg_cert_rma_no_pwd.cfg14 #rma-mode = Set to non-zero value to use this certificate for RMA mode entry. Mandatory…
16 … OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
17 … Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is set, the HW keys rese…
18 …OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
19 # Cannot be defined together with rma-mode.
23 # Mandatory if rma-mode is defined (for rma-mode, only two-level certificate …
25 # Must be empty if rma-mode is defined.
32 rma-mode = 1
Dsb_enabler_dbg_cert_rma.cfg14 #rma-mode = Set to non-zero value to use this certificate for RMA mode entry. Mandatory…
16 … OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
17 … Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is set, the HW keys rese…
18 …OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
19 # Cannot be defined together with rma-mode.
23 # Mandatory if rma-mode is defined (for rma-mode, only two-level certificate …
31 rma-mode = 1
Dx509_sb_enabler_dbg_cert_rma.cfg14 #rma-mode = Set to non-zero value to use this certificate for RMA mode entry. Mandatory…
16 … OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
17 … Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is set, the HW keys rese…
18 …OEM. 128 bit mask in 4*32 bits hex format (e.g. 0x7000000f). Mandatory if rma-mode is not defined.
19 # Cannot be defined together with rma-mode.
23 # Mandatory if rma-mode is defined (for rma-mode, only two-level certificate …
31 rma-mode = 1
/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/codesafe/src/crypto_api/cc3x_sym/driver/
Daes_driver_ext_dma.c141 drvError_t AesExtDmaSetIv(aesMode_t mode, uint32_t *pIv) in AesExtDmaSetIv() argument
145 switch (mode) { in AesExtDmaSetIv()
171 drvError_t AesExtDmaStoreIv(aesMode_t mode, uint32_t *pIv) in AesExtDmaStoreIv() argument
175 switch (mode) { in AesExtDmaStoreIv()
192 drvError_t AesExtDmaSetKey(aesMode_t mode, uint32_t *keyBuf, keySizeId_t keySizeId) in AesExtDmaSetKey() argument
217 if (mode == CIPHER_CMAC) { in AesExtDmaSetKey()
225 drvError_t finalizeAesExtDma(aesMode_t mode, uint32_t *pIv) in finalizeAesExtDma() argument
229 if (mode == CIPHER_CMAC || mode== CIPHER_CBC_MAC) in finalizeAesExtDma()
231 drvRc = AesExtDmaStoreIv(mode, pIv); in finalizeAesExtDma()
Daes_driver_ext_dma.h17 drvError_t finalizeAesExtDma(aesMode_t mode, uint32_t *pIv);
21 drvError_t AesExtDmaSetIv(aesMode_t mode, uint32_t *pIv);
24 drvError_t AesExtDmaSetKey(aesMode_t mode, uint32_t *keyBuf, keySizeId_t keySizeId);
/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/codesafe/src/psa_driver_api/src/
Dcc3xx_internal_aes.c109 aesMode_t mode, in cc3xx_aes_crypt() argument
128 if (mode != CIPHER_CTR && length % AES_BLOCK_SIZE) { in cc3xx_aes_crypt()
133 ctx->mode = mode; in cc3xx_aes_crypt()
135 if (mode != CIPHER_ECB) { in cc3xx_aes_crypt()
152 if (mode != CIPHER_ECB) { in cc3xx_aes_crypt()
/trusted-firmware-m-latest/platform/ext/target/stm/common/hal/accelerator/
Daes_alt.c307 int mode, in mbedtls_aes_crypt_ecb() argument
316 AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || in mbedtls_aes_crypt_ecb()
317 mode == MBEDTLS_AES_DECRYPT ); in mbedtls_aes_crypt_ecb()
332 if (mode == MBEDTLS_AES_DECRYPT) { /* AES decryption */ in mbedtls_aes_crypt_ecb()
369 int mode, in mbedtls_aes_crypt_cbc() argument
379 AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || in mbedtls_aes_crypt_cbc()
380 mode == MBEDTLS_AES_DECRYPT ); in mbedtls_aes_crypt_cbc()
412 if (mode == MBEDTLS_AES_DECRYPT) { in mbedtls_aes_crypt_cbc()
498 int mode, in mbedtls_aes_crypt_xts() argument
512 AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || in mbedtls_aes_crypt_xts()
[all …]
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/
DARMCA7_ac6.sct38 -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
45 -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
51 -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
56 -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
60 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/
DARMCA9_ac6.sct38 -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
45 -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
51 -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
56 -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
60 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/
DARMCA5_ac6.sct38 -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
45 -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
51 -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
56 -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
60 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/
Dsbrt_int_func.c293 bsvCryptoMode_t mode, in SBRT_CryptoImageInit() argument
297 if ((mode!=BSV_CRYPTO_HASH) && in SBRT_CryptoImageInit()
298 (mode!=BSV_CRYPTO_AES_AND_HASH) && in SBRT_CryptoImageInit()
299 (mode!=BSV_CRYPTO_AES_TO_HASH_AND_DOUT)){ in SBRT_CryptoImageInit()
303 if(mode != BSV_CRYPTO_HASH){ in SBRT_CryptoImageInit()
313 if (mode != BSV_CRYPTO_HASH){ in SBRT_CryptoImageInit()
317 SB_HAL_WRITE_REGISTER(SB_REG_ADDR(hwBaseAddress, CRYPTO_CTL) ,mode); in SBRT_CryptoImageInit()
324 bsvCryptoMode_t mode, in SBRT_CryptoImageUpdate() argument
336 if (mode == BSV_CRYPTO_HASH){ in SBRT_CryptoImageUpdate()
353 bsvCryptoMode_t mode, in SBRT_CryptoImageFinish() argument
[all …]
/trusted-firmware-m-latest/interface/include/mbedtls/
Daes.h248 int mode,
296 int mode,
341 int mode,
390 int mode,
435 int mode,

123456789