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Searched refs:ctrl (Results 1 – 25 of 54) sorted by relevance

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/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/RTOS2/Source/
Dos_tick_ptim.c102 uint32_t ctrl; in OS_Tick_Enable() local
111 ctrl = PTIM_GetControl(); in OS_Tick_Enable()
113 ctrl |= 1U; in OS_Tick_Enable()
114 PTIM_SetControl (ctrl); in OS_Tick_Enable()
119 uint32_t ctrl; in OS_Tick_Disable() local
122 ctrl = PTIM_GetControl(); in OS_Tick_Disable()
124 ctrl &= ~1U; in OS_Tick_Disable()
125 PTIM_SetControl (ctrl); in OS_Tick_Disable()
Dos_tick_gtim.c124 uint32_t ctrl; in OS_Tick_Enable() local
133 ctrl = PL1_GetControl(); in OS_Tick_Enable()
135 ctrl |= 1U; in OS_Tick_Enable()
136 PL1_SetControl(ctrl); in OS_Tick_Enable()
141 uint32_t ctrl; in OS_Tick_Disable() local
144 ctrl = PL1_GetControl(); in OS_Tick_Disable()
146 ctrl &= ~1U; in OS_Tick_Disable()
147 PL1_SetControl(ctrl); in OS_Tick_Disable()
/trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/Native_Driver/
Dtimer_cmsdk_drv.c40 volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */ member
76 register_map->ctrl = 0; in timer_cmsdk_init()
91 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_enable_external_input()
98 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_disable_external_input()
105 return GET_BIT(register_map->ctrl, in timer_cmsdk_is_external_input_enabled()
113 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_internal()
120 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_external()
127 return GET_BIT(register_map->ctrl, in timer_cmsdk_is_clock_external()
135 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_enable()
142 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_disable()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an519/native_drivers/timer_cmsdk/
Dtimer_cmsdk.c40 volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */ member
76 register_map->ctrl = 0; in cmsdk_timer_init()
91 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_enable_external_input()
98 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_disable_external_input()
105 return GET_BIT(register_map->ctrl, in cmsdk_timer_is_external_input_enabled()
113 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_internal()
120 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_external()
127 return GET_BIT(register_map->ctrl, in cmsdk_timer_is_clock_external()
135 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_enable()
142 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_disable()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/drivers/timer/cmsdk/
Dtimer_cmsdk_drv.c40 volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */ member
78 register_map->ctrl = 0; in timer_cmsdk_init()
93 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_enable_external_input()
100 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_disable_external_input()
107 return GET_BIT(register_map->ctrl, in timer_cmsdk_is_external_input_enabled()
115 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_internal()
122 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_external()
129 return GET_BIT(register_map->ctrl, in timer_cmsdk_is_clock_external()
137 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_enable()
144 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_disable()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/musca_s1/Native_Driver/
Dtimer_cmsdk_drv.c31 volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */ member
67 register_map->ctrl = 0; in timer_cmsdk_init()
82 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_enable_external_input()
89 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_disable_external_input()
96 return GET_BIT(register_map->ctrl, in timer_cmsdk_is_external_input_enabled()
104 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_internal()
111 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_external()
118 return GET_BIT(register_map->ctrl, in timer_cmsdk_is_clock_external()
126 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_enable()
133 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_disable()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an521/native_drivers/timer_cmsdk/
Dtimer_cmsdk.c40 volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */ member
76 register_map->ctrl = 0; in cmsdk_timer_init()
91 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_enable_external_input()
98 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_disable_external_input()
105 return GET_BIT(register_map->ctrl, in cmsdk_timer_is_external_input_enabled()
113 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_internal()
120 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_external()
127 return GET_BIT(register_map->ctrl, in cmsdk_timer_is_clock_external()
135 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_enable()
142 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_disable()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an519/native_drivers/
Darm_uart_drv.c25 volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ member
70 p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN; in arm_uart_init()
174 p_uart->ctrl |= ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_enable()
185 p_uart->ctrl &= ~ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_disable()
210 p_uart->ctrl |= ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_enable()
221 p_uart->ctrl &= ~ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_disable()
269 p_uart->ctrl |= ARM_UART_TX_EN; in arm_uart_tx_enable()
280 p_uart->ctrl &= ~ARM_UART_TX_EN; in arm_uart_tx_disable()
293 p_uart->ctrl |= ARM_UART_RX_EN; in arm_uart_rx_enable()
304 p_uart->ctrl &= ~ARM_UART_RX_EN; in arm_uart_rx_disable()
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an521/native_drivers/
Darm_uart_drv.c25 volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ member
70 p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN; in arm_uart_init()
174 p_uart->ctrl |= ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_enable()
185 p_uart->ctrl &= ~ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_disable()
210 p_uart->ctrl |= ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_enable()
221 p_uart->ctrl &= ~ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_disable()
269 p_uart->ctrl |= ARM_UART_TX_EN; in arm_uart_tx_enable()
280 p_uart->ctrl &= ~ARM_UART_TX_EN; in arm_uart_tx_disable()
293 p_uart->ctrl |= ARM_UART_RX_EN; in arm_uart_rx_enable()
304 p_uart->ctrl &= ~ARM_UART_RX_EN; in arm_uart_rx_disable()
/trusted-firmware-m-latest/platform/ext/target/arm/drivers/usart/cmsdk/
Duart_cmsdk_drv.c56 p_uart->ctrl = UART_CMSDK_RX_EN | UART_CMSDK_TX_EN; in uart_cmsdk_init()
162 p_uart->ctrl |= UART_CMSDK_TX_INTR_EN; in uart_cmsdk_irq_tx_enable()
173 p_uart->ctrl &= ~UART_CMSDK_TX_INTR_EN; in uart_cmsdk_irq_tx_disable()
198 p_uart->ctrl |= UART_CMSDK_RX_INTR_EN; in uart_cmsdk_irq_rx_enable()
209 p_uart->ctrl &= ~UART_CMSDK_RX_INTR_EN; in uart_cmsdk_irq_rx_disable()
258 p_uart->ctrl |= UART_CMSDK_TX_EN; in uart_cmsdk_tx_enable()
269 p_uart->ctrl &= ~UART_CMSDK_TX_EN; in uart_cmsdk_tx_disable()
282 p_uart->ctrl |= UART_CMSDK_RX_EN; in uart_cmsdk_rx_enable()
293 p_uart->ctrl &= ~UART_CMSDK_RX_EN; in uart_cmsdk_rx_disable()
/trusted-firmware-m-latest/secure_fw/spm/include/
Dtfm_arch.h215 CONTROL_Type ctrl; in __set_CONTROL_nPRIV() local
217 ctrl.w = __get_CONTROL(); in __set_CONTROL_nPRIV()
218 ctrl.b.nPRIV = nPRIV; in __set_CONTROL_nPRIV()
219 __set_CONTROL(ctrl.w); in __set_CONTROL_nPRIV()
231 CONTROL_Type ctrl; in tfm_arch_is_priv() local
239 ctrl.w = __get_CONTROL(); in tfm_arch_is_priv()
240 if (!ctrl.b.nPRIV) { in tfm_arch_is_priv()
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/CoreValidation/Source/
DCV_CoreFunc.c244 static uint32_t ctrl; in TC_CoreFunc_Control() local
248 ctrl = orig; in TC_CoreFunc_Control()
253 ASSERT_TRUE((ctrl & CONTROL_SPSEL_Msk) == 0U); in TC_CoreFunc_Control()
256 ctrl |= CONTROL_SPSEL_Msk; in TC_CoreFunc_Control()
262 __set_CONTROL(ctrl); in TC_CoreFunc_Control()
270 ASSERT_TRUE(result == ctrl); in TC_CoreFunc_Control()
409 static uint32_t ctrl; in TC_CoreFunc_MSP() local
411 ctrl = __get_CONTROL(); in TC_CoreFunc_MSP()
415 __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP in TC_CoreFunc_MSP()
424 __set_CONTROL(ctrl); in TC_CoreFunc_MSP()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/drivers/mpc_sie/
Dmpc_sie_drv.c545 *ctrl_val = p_mpc->ctrl; in mpc_sie_get_ctrl()
560 p_mpc->ctrl = mpc_ctrl; in mpc_sie_set_ctrl()
581 if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) { in mpc_sie_get_sec_resp()
593 if(p_mpc->ctrl & MPC_SIE300_CTRL_SEC_RESP) { in mpc_sie_get_sec_resp()
620 p_mpc->ctrl |= MPC_SIE200_CTRL_SEC_RESP; in mpc_sie_set_sec_resp()
622 p_mpc->ctrl &= ~MPC_SIE200_CTRL_SEC_RESP; in mpc_sie_set_sec_resp()
634 p_mpc->ctrl |= MPC_SIE300_CTRL_SEC_RESP; in mpc_sie_set_sec_resp()
636 p_mpc->ctrl &= ~MPC_SIE300_CTRL_SEC_RESP; in mpc_sie_set_sec_resp()
695 p_mpc->ctrl |= (MPC_SIE_CTRL_AUTOINCREMENT in mpc_sie_lock_down()
715 *gating_present = (bool)(p_mpc->ctrl & MPC_SIE300_CTRL_GATE_PRESENT); in mpc_sie_is_gating_present()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an519/
Dtfm_hal_isolation.c255 CONTROL_Type ctrl; in tfm_hal_activate_boundary() local
259 ctrl.w = __get_CONTROL(); in tfm_hal_activate_boundary()
260 ctrl.b.nPRIV = privileged ? 0 : 1; in tfm_hal_activate_boundary()
261 __set_CONTROL(ctrl.w); in tfm_hal_activate_boundary()
293 CONTROL_Type ctrl; in tfm_hal_memory_check() local
294 ctrl.w = __TZ_get_CONTROL_NS(); in tfm_hal_memory_check()
295 if (ctrl.b.nPRIV == 1) { in tfm_hal_memory_check()
/trusted-firmware-m-latest/platform/ext/target/nuvoton/common/native_drivers/
Darm_uart_drv.c25 volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ member
70 p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN; in arm_uart_init()
174 p_uart->ctrl |= ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_enable()
185 p_uart->ctrl &= ~ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_disable()
210 p_uart->ctrl |= ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_enable()
221 p_uart->ctrl &= ~ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_disable()
Duart_cmsdk_drv.c25 volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ member
73 p_uart->ctrl = UART_CMSDK_RX_EN | UART_CMSDK_TX_EN; in uart_cmsdk_init()
179 p_uart->ctrl |= UART_CMSDK_TX_INTR_EN; in uart_cmsdk_irq_tx_enable()
190 p_uart->ctrl &= ~UART_CMSDK_TX_INTR_EN; in uart_cmsdk_irq_tx_disable()
215 p_uart->ctrl |= UART_CMSDK_RX_INTR_EN; in uart_cmsdk_irq_rx_enable()
226 p_uart->ctrl &= ~UART_CMSDK_RX_INTR_EN; in uart_cmsdk_irq_rx_disable()
/trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/
Dtfm_hal_isolation.c148 CONTROL_Type ctrl; in tfm_hal_activate_boundary() local
152 ctrl.w = __get_CONTROL(); in tfm_hal_activate_boundary()
153 ctrl.b.nPRIV = privileged ? 0 : 1; in tfm_hal_activate_boundary()
154 __set_CONTROL(ctrl.w); in tfm_hal_activate_boundary()
/trusted-firmware-m-latest/platform/ext/target/arm/musca_s1/
Dtfm_hal_isolation.c265 CONTROL_Type ctrl; in tfm_hal_activate_boundary() local
269 ctrl.w = __get_CONTROL(); in tfm_hal_activate_boundary()
270 ctrl.b.nPRIV = privileged ? 0 : 1; in tfm_hal_activate_boundary()
271 __set_CONTROL(ctrl.w); in tfm_hal_activate_boundary()
303 CONTROL_Type ctrl; in tfm_hal_memory_check() local
304 ctrl.w = __TZ_get_CONTROL_NS(); in tfm_hal_memory_check()
305 if (ctrl.b.nPRIV == 1) { in tfm_hal_memory_check()
/trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/CMSIS_Driver/
DDriver_MPC.c121 static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM0_MPC_SetCtrlConfig() argument
125 ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV, ctrl); in ISRAM0_MPC_SetCtrlConfig()
260 static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM1_MPC_SetCtrlConfig() argument
264 ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV, ctrl); in ISRAM1_MPC_SetCtrlConfig()
399 static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM2_MPC_SetCtrlConfig() argument
403 ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV, ctrl); in ISRAM2_MPC_SetCtrlConfig()
537 static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM3_MPC_SetCtrlConfig() argument
541 ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV, ctrl); in ISRAM3_MPC_SetCtrlConfig()
676 static int32_t CODE_SRAM_MPC_SetCtrlConfig(uint32_t ctrl) in CODE_SRAM_MPC_SetCtrlConfig() argument
680 ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM_DEV, ctrl); in CODE_SRAM_MPC_SetCtrlConfig()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/musca_s1/CMSIS_Driver/
DDriver_MPC.c121 static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM0_MPC_SetCtrlConfig() argument
125 ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV, ctrl); in ISRAM0_MPC_SetCtrlConfig()
259 static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM1_MPC_SetCtrlConfig() argument
263 ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV, ctrl); in ISRAM1_MPC_SetCtrlConfig()
397 static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM2_MPC_SetCtrlConfig() argument
401 ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV, ctrl); in ISRAM2_MPC_SetCtrlConfig()
534 static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM3_MPC_SetCtrlConfig() argument
538 ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV, ctrl); in ISRAM3_MPC_SetCtrlConfig()
672 static int32_t CODE_SRAM_MPC_SetCtrlConfig(uint32_t ctrl) in CODE_SRAM_MPC_SetCtrlConfig() argument
676 ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM_DEV, ctrl); in CODE_SRAM_MPC_SetCtrlConfig()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an519/cmsis_drivers/
DDriver_MPC.c121 static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM0_MPC_SetCtrlConfig() argument
125 ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV_S, ctrl); in ISRAM0_MPC_SetCtrlConfig()
257 static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM1_MPC_SetCtrlConfig() argument
261 ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV_S, ctrl); in ISRAM1_MPC_SetCtrlConfig()
393 static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM2_MPC_SetCtrlConfig() argument
397 ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV_S, ctrl); in ISRAM2_MPC_SetCtrlConfig()
529 static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM3_MPC_SetCtrlConfig() argument
533 ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV_S, ctrl); in ISRAM3_MPC_SetCtrlConfig()
665 static int32_t SRAM1_MPC_SetCtrlConfig(uint32_t ctrl) in SRAM1_MPC_SetCtrlConfig() argument
669 ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl); in SRAM1_MPC_SetCtrlConfig()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an521/cmsis_drivers/
DDriver_MPC.c121 static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM0_MPC_SetCtrlConfig() argument
125 ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV_S, ctrl); in ISRAM0_MPC_SetCtrlConfig()
257 static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM1_MPC_SetCtrlConfig() argument
261 ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV_S, ctrl); in ISRAM1_MPC_SetCtrlConfig()
393 static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM2_MPC_SetCtrlConfig() argument
397 ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV_S, ctrl); in ISRAM2_MPC_SetCtrlConfig()
529 static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl) in ISRAM3_MPC_SetCtrlConfig() argument
533 ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV_S, ctrl); in ISRAM3_MPC_SetCtrlConfig()
665 static int32_t SRAM1_MPC_SetCtrlConfig(uint32_t ctrl) in SRAM1_MPC_SetCtrlConfig() argument
669 ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl); in SRAM1_MPC_SetCtrlConfig()
[all …]
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/secure/
Dtfm_hal_isolation.c438 CONTROL_Type ctrl; in tfm_hal_activate_boundary() local
443 ctrl.w = __get_CONTROL(); in tfm_hal_activate_boundary()
444 ctrl.b.nPRIV = privileged ? 0 : 1; in tfm_hal_activate_boundary()
445 __set_CONTROL(ctrl.w); in tfm_hal_activate_boundary()
477 CONTROL_Type ctrl; in tfm_hal_memory_check() local
478 ctrl.w = __TZ_get_CONTROL_NS(); in tfm_hal_memory_check()
479 if (ctrl.b.nPRIV == 1) { in tfm_hal_memory_check()
/trusted-firmware-m-latest/platform/ext/common/
Dtfm_hal_isolation_v8m.c411 CONTROL_Type ctrl; in tfm_hal_activate_boundary() local
415 ctrl.w = __get_CONTROL(); in tfm_hal_activate_boundary()
416 ctrl.b.nPRIV = privileged ? 0 : 1; in tfm_hal_activate_boundary()
417 __set_CONTROL(ctrl.w); in tfm_hal_activate_boundary()
454 CONTROL_Type ctrl; in tfm_hal_memory_check() local
455 ctrl.w = __TZ_get_CONTROL_NS(); in tfm_hal_memory_check()
456 if (ctrl.b.nPRIV == 1) { in tfm_hal_memory_check()
/trusted-firmware-m-latest/platform/ext/target/rpi/rp2350/
Dtfm_hal_isolation_rp2350.c397 CONTROL_Type ctrl; in tfm_hal_activate_boundary() local
401 ctrl.w = __get_CONTROL(); in tfm_hal_activate_boundary()
402 ctrl.b.nPRIV = privileged ? 0 : 1; in tfm_hal_activate_boundary()
403 __set_CONTROL(ctrl.w); in tfm_hal_activate_boundary()
440 CONTROL_Type ctrl; in tfm_hal_memory_check() local
441 ctrl.w = __TZ_get_CONTROL_NS(); in tfm_hal_memory_check()
442 if (ctrl.b.nPRIV == 1) { in tfm_hal_memory_check()

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