Searched refs:SRAM1_BASE_NS (Results 1 – 16 of 16) sorted by relevance
| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/bl2/ |
| D | tfm_low_level_security.c | 493 SAU->RBAR = (SRAM1_BASE_NS & SAU_RBAR_BADDR_Msk); in sau_and_idau_cfg()
494 SAU->RLAR = ((SRAM1_BASE_NS + 0xff) & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; in sau_and_idau_cfg()
646 region_cfg.region_base = SRAM1_BASE_NS + (~MPU_RBAR_BASE_Msk) + 1; in mpu_init_cfg()
648 region_cfg.region_base = SRAM1_BASE_NS ; in mpu_init_cfg()
650 region_cfg.region_limit = SRAM1_BASE_NS + TOTAL_RAM_SIZE - 1; in mpu_init_cfg()
723 region_cfg.region_base = SRAM1_BASE_NS ; in mpu_appli_cfg()
726 region_cfg.region_base = SRAM1_BASE_NS ; in mpu_appli_cfg()
727 region_cfg.region_limit = SRAM1_BASE_NS + (~MPU_RBAR_BASE_Msk); in mpu_appli_cfg()
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| D | boot_hal_bl2.c | 343 nsfptr_t nsfptr = (nsfptr_t)(SRAM1_BASE_NS + 1); in Error_Handler()
344 __IO uint16_t *pt = (uint16_t *)SRAM1_BASE_NS; in Error_Handler()
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/bl2/ |
| D | boot_hal_bl2.c | 661 nsfptr_t nsfptr = (nsfptr_t)(SRAM1_BASE_NS + 1); in Error_Handler()
662 __IO uint16_t *pt = (uint16_t *)SRAM1_BASE_NS; in Error_Handler()
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| D | low_level_security.c | 446 (uint32_t)SRAM1_BASE_NS,
447 ((uint32_t)SRAM1_BASE_NS + _SRAM1_SIZE_MAX - 1U),
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/bl2/ |
| D | boot_hal_bl2.c | 684 nsfptr_t nsfptr = (nsfptr_t)(SRAM1_BASE_NS + 1); in Error_Handler()
685 __IO uint16_t *pt = (uint16_t *)SRAM1_BASE_NS; in Error_Handler()
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| D | low_level_security.c | 224 SRAM1_BASE_NS + (~MPU_RBAR_BASE_Msk) + 1,
226 SRAM1_BASE_NS,
228 SRAM1_BASE_NS + TOTAL_RAM_SIZE,
309 SRAM1_BASE_NS,
310 (SRAM1_BASE_NS + NS_NO_INIT_DATA_SIZE),
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/secure/ |
| D | target_cfg.c | 110 SRAM1_BASE_NS,
111 (SRAM1_BASE_NS + _SRAM1_SIZE_MAX - 1),
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| D | tfm_hal_isolation.c | 170 SRAM1_BASE_NS,
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/secure/ |
| D | tfm_hal_isolation.c | 163 SRAM1_BASE_NS,
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/hal/Src/ |
| D | stm32l5xx_hal_gtzc.c | 851 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()
946 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_GetConfigMemAttributes()
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/hal/Src/ |
| D | stm32h5xx_hal_gtzc.c | 1047 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()
1192 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_GetConfigMemAttributes()
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/hal/Src/ |
| D | stm32u5xx_hal_gtzc.c | 1010 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()
1161 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_GetConfigMemAttributes()
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/Device/Include/ |
| D | stm32l552xx.h | 1342 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1(up to 192 KB) base address */ macro
2485 #define SRAM1_BASE SRAM1_BASE_NS
2487 #define SRAM_BASE SRAM1_BASE_NS
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| D | stm32l562xx.h | 1416 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1(up to 192 KB) base address */ macro
2608 #define SRAM1_BASE SRAM1_BASE_NS
2610 #define SRAM_BASE SRAM1_BASE_NS
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/Device/Include/ |
| D | stm32u585xx.h | 1726 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address … macro
3006 #define SRAM1_BASE SRAM1_BASE_NS
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/Device/Include/ |
| D | stm32h573xx.h | 1809 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (256 KB) non-secure base address … macro
3143 #define SRAM1_BASE SRAM1_BASE_NS
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