Searched refs:Interrupt (Results 1 – 25 of 32) sorted by relevance
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73 DCD NvicMux0_IRQHandler ; CPU User Interrupt #075 DCD NvicMux2_IRQHandler ; CPU User Interrupt #277 DCD NvicMux4_IRQHandler ; CPU User Interrupt #478 DCD NvicMux5_IRQHandler ; CPU User Interrupt #579 DCD NvicMux6_IRQHandler ; CPU User Interrupt #680 DCD tfm_mailbox_irq_handler ; CPU User Interrupt #781 DCD Internal0_IRQHandler ; Internal SW Interrupt #082 DCD Internal1_IRQHandler ; Internal SW Interrupt #183 DCD Internal2_IRQHandler ; Internal SW Interrupt #284 DCD Internal3_IRQHandler ; Internal SW Interrupt #3[all …]
62 DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #063 DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #164 DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #265 DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #366 DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #467 DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #568 DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #669 DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #770 DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #871 DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9[all …]
79 DCD NvicMux0_IRQHandler ; CPU User Interrupt #081 DCD NvicMux2_IRQHandler ; CPU User Interrupt #283 DCD NvicMux4_IRQHandler ; CPU User Interrupt #484 DCD NvicMux5_IRQHandler ; CPU User Interrupt #585 DCD NvicMux6_IRQHandler ; CPU User Interrupt #686 DCD tfm_mailbox_irq_handler ; CPU User Interrupt #787 DCD Internal0_IRQHandler ; Internal SW Interrupt #088 DCD Internal1_IRQHandler ; Internal SW Interrupt #189 DCD Internal2_IRQHandler ; Internal SW Interrupt #290 DCD Internal3_IRQHandler ; Internal SW Interrupt #3[all …]
68 DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #069 DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #170 DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #271 DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #372 DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #473 DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #574 DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #675 DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #776 DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #877 DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9[all …]
2 Secure Interrupt Integration Guide17 Interrupt Handling Model22 - First-Level Interrupt Handling (FLIH)30 - Second-Level Interrupt Handling (SLIH)53 Enabling an Interrupt65 See also `Enabling the Interrupt Tests`_ on how to integrate them to platforms.67 Binding an Interrupt to a Secure Partition argument72 ``irqs`` is a list of Interrupt Request (IRQ) assigned to the Secure Partition.173 - ``FLIH`` - First-Level Interrupt Handling174 - ``SLIH`` - Second-Level Interrupt Handling[all …]
23 * Does not support use FPU in First-Level Interrupt Handling (FLIH) [6]_ at143 .. [6] :doc:`Secure Interrupt Integration Guide </integration_guide/tfm_secure_irq_integration_guid…
15 Secure Interrupt <tfm_secure_irq_integration_guide.rst>
9 … OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests")
12 … OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests")
7 … OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests")
10 … OFF CACHE BOOL "Whether to build NS regression First-Level Interrupt Handling tests")
10 … OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests")
36 | TEST_NS_SLIH_IRQ | Build non-secure regression Second-Level Interrupt Handling tests. |38 | TEST_NS_FLIH_IRQ | Build non-secure regression First-Level Interrupt Handling tests. |
13 - Interrupt support (both SLIH/FLIH) for the SFN backend.
12 - First-Level Interrupt Handling (FLIH) [1]_ proof of concept on AN521 and MUSCA-B1.
11 - Support Second-Level Interrupt Handling (SLIH) defined in FF-M 1.1 [1]_.
32 - Secure Partition Interrupt Handling, Pre-emption of SPE execution
58 - **Interrupt API**: Provides the interrupt functions.639 Interrupt APIs642 The SPM HAL interrupt APIs are intended for operations on Interrupt Controllers664 This API enables an interrupt from the Interrupt Controller of the platform.688 This API disables an interrupt from the Interrupt Controller of the platform.
59 /* Interrupt init functions */
519 example, the `First Level Interrupt Handler (FLIH)` of one partition.523 Interrupt handling is a common background state example. Check Interrupt
1810 if (sAllTamper->TampInput[i].Interrupt != RTC_ATAMP_INTERRUPT_DISABLE) in HAL_RTCEx_SetActiveTampers()1880 sAllTamper->TampInput[i].Interrupt = (uint32_t)(((TAMP->IER & (TAMP_IER_TAMP1IE << i))) >> i); in HAL_RTCEx_GetActiveTampers()
