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Searched refs:FLASH_BASE_NS (Results 1 – 18 of 18) sorted by relevance

/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/bl2/
Dtfm_low_level_security.c509 SAU->RBAR = ((uint32_t)FLASH_BASE_NS + FLASH_AREA_1_OFFSET) & SAU_RBAR_BADDR_Msk; in sau_and_idau_cfg()
510 SAU->RLAR = (((uint32_t)FLASH_BASE_NS + FLASH_AREA_1_OFFSET in sau_and_idau_cfg()
518 SAU->RBAR = ((uint32_t)FLASH_BASE_NS + FLASH_AREA_1_OFFSET) & SAU_RBAR_BADDR_Msk; in sau_and_idau_cfg()
519 SAU->RLAR = (((uint32_t)FLASH_BASE_NS + FLASH_AREA_3_OFFSET in sau_and_idau_cfg()
622 region_cfg.region_base = FLASH_BASE_NS + FLASH_AREA_1_OFFSET; in mpu_init_cfg()
623 region_cfg.region_limit = FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE - 1; in mpu_init_cfg()
633 region_cfg.region_base = FLASH_BASE_NS + FLASH_AREA_2_OFFSET; in mpu_init_cfg()
634 region_cfg.region_limit = FLASH_BASE_NS + FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE - 1; in mpu_init_cfg()
712 region_cfg.region_base = FLASH_BASE_NS + FLASH_AREA_1_OFFSET; in mpu_appli_cfg()
713 region_cfg.region_limit = FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE - 1; in mpu_appli_cfg()
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/bl2/
Dlow_level_security.c169 FLASH_BASE_NS,
170 FLASH_BASE_NS + FLASH_TOTAL_SIZE,
190 FLASH_BASE_NS + NS_IMAGE_PRIMARY_PARTITION_OFFSET,
191 FLASH_BASE_NS + NS_IMAGE_PRIMARY_PARTITION_OFFSET + FLASH_NS_PARTITION_SIZE,
206 FLASH_BASE_NS + S_IMAGE_SECONDARY_PARTITION_OFFSET,
207 FLASH_BASE_NS + NS_IMAGE_SECONDARY_PARTITION_OFFSET + FLASH_NS_PARTITION_SIZE,
288 FLASH_BASE_NS + NS_IMAGE_PRIMARY_PARTITION_OFFSET,
290 …FLASH_BASE_NS + NS_IMAGE_PRIMARY_PARTITION_OFFSET + FLASH_NS_PARTITION_SIZE - (~MPU_RLAR_LIMIT_Msk…
337 ((uint32_t)FLASH_BASE_NS + NS_IMAGE_PRIMARY_PARTITION_OFFSET),
339 ((uint32_t)FLASH_BASE_NS + NS_IMAGE_PRIMARY_PARTITION_OFFSET + FLASH_NS_PARTITION_SIZE),
[all …]
/trusted-firmware-m-latest/platform/ext/target/stm/common/hal/CMSIS_Driver/
Dlow_level_flash.c388 memcpy_flash(data, (void *)((uint32_t)addr + FLASH_BASE_NS), cnt); in Flash_ReadData()
391 memcpy_flash(data, (void *)((uint32_t)addr + FLASH_BASE_NS), cnt); in Flash_ReadData()
448 flash_base = (uint32_t)FLASH_BASE_NS; in Flash_ProgramData()
604 pt = (uint32_t *)((uint32_t)FLASH_BASE_NS + addr); in Flash_EraseSector()
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/secure/
Dtfm_hal_isolation.c179 FLASH_BASE_NS,
180 FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE - 32,
Dtarget_cfg.c52 #define NON_SECURE_LIMIT (uint32_t)(FLASH_BASE_NS + FLASH_TOTAL_SIZE - 1)
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/secure/
Dtfm_hal_isolation.c186 FLASH_BASE_NS,
187 FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE - 32,
Dtarget_cfg.c62 #define NON_SECURE_LIMIT (uint32_t)(FLASH_BASE_NS + FLASH_AREA_END_OFFSET - 1)
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/secure/
Dtarget_cfg.c47 (uint32_t)(FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_NS_PARTITION_SIZE - 1),
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/hal/Inc/
Dstm32h5xx_hal_flash.h730 … (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE))))
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/bl2/
Dlow_level_security.c220 FLASH_BASE_NS + FLASH_AREA_BEGIN_OFFSET,
221 FLASH_BASE_NS + FLASH_AREA_END_OFFSET - 1,
311 ((uint32_t)FLASH_BASE_NS + NS_IMAGE_PRIMARY_PARTITION_OFFSET),
312 ((uint32_t)FLASH_BASE_NS + FLASH_AREA_END_OFFSET - 1),
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/hal/Inc/
Dstm32l5xx_hal_flash.h987 … (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE))))
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/hal/Inc/
Dstm32u5xx_hal_flash.h983 … (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE))))
/trusted-firmware-m-latest/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/
DLPC55S69_cm33_core1.h7793 #define FLASH_BASE_NS (0x40034000u) macro
7797 #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS)
7803 #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS }
DLPC55S69_cm33_core0.h7793 #define FLASH_BASE_NS (0x40034000u) macro
7797 #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS)
7803 #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS }
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/Device/Include/
Dstm32l552xx.h1341 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH(up to 512 KB) base address */ macro
2484 #define FLASH_BASE FLASH_BASE_NS
Dstm32l562xx.h1415 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH(up to 512 KB) base address */ macro
2607 #define FLASH_BASE FLASH_BASE_NS
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/Device/Include/
Dstm32u585xx.h1725 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address … macro
3005 #define FLASH_BASE FLASH_BASE_NS
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/Device/Include/
Dstm32h573xx.h1808 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address … macro
3138 #define FLASH_BASE FLASH_BASE_NS