Searched refs:CSSELR (Results 1 – 8 of 8) sorted by relevance
148 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()192 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()254 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()289 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()324 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
557 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member3186 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()3224 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()3262 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()3297 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()3332 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
493 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
545 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
581 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
555 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
576 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
