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Searched refs:CPU0_PWRCTRL_BASE_S (Results 1 – 9 of 9) sorted by relevance

/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/partition/
Dplatform_base_address.h93 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/an547/partition/
Dplatform_base_address.h112 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-latest/platform/ext/target/armchina/mps3/alcor/an557/partition/
Dplatform_base_address.h104 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone310/common/partition/
Dplatform_base_address.h133 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/an552/partition/
Dplatform_base_address.h117 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/fvp/partition/
Dplatform_base_address.h127 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/partition/
Dplatform_base_address.h125 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/include/
Dpower_control.h52 (struct cpu0_pwrctrl_t*) CPU0_PWRCTRL_BASE_S;
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone310/common/device/include/
Dpower_control.h52 (struct cpu0_pwrctrl_t*) CPU0_PWRCTRL_BASE_S;