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Searched refs:CLOCK_SetClkDiv (Results 1 – 7 of 7) sorted by relevance

/trusted-firmware-m-latest/platform/ext/target/nxp/lpcxpresso55s69/project_template/bl2/
Dclock_config.c94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
142 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
293 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
365 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL1_150M()
/trusted-firmware-m-latest/platform/ext/target/nxp/lpcxpresso55s69/project_template/s/
Dclock_config.c94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
142 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
293 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
365 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL1_150M()
/trusted-firmware-m-latest/platform/ext/target/nxp/lpcxpresso55s69/project_template/ns/
Dclock_config.c94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
142 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
293 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
365 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL1_150M()
/trusted-firmware-m-latest/platform/ext/target/nxp/common/
Dplat_test.c48 CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 0u, false); in tfm_plat_test_secure_timer_start()
49 CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1u, true); in tfm_plat_test_secure_timer_start()
/trusted-firmware-m-latest/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/
Dfsl_clock.c200 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) in CLOCK_SetClkDiv() function
1909 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
1945 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
1973 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2008 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
Dfsl_clock.h1051 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
Dfsl_power.c386 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ in POWER_EnterLowPower()