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Searched refs:BL1_1_DATA_START (Results 1 – 16 of 16) sorted by relevance

/trusted-firmware-m-latest/platform/ext/target/arm/corstone1000/partition/
Dregion_defs.h105 #define BL1_1_DATA_START (SRAM_BASE) macro
107 #define BL1_1_DATA_LIMIT (BL1_1_DATA_START + BL1_1_DATA_SIZE - 1)
109 #define BL1_2_CODE_START (BL1_1_DATA_START + BL1_1_DATA_SIZE)
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/partition/
Dregion_defs.h148 #define BL1_1_DATA_START (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE) macro
150 #define BL1_1_DATA_LIMIT (BL1_1_DATA_START + BL1_1_DATA_SIZE - 1)
155 #define BL1_2_DATA_START (BL1_1_DATA_START + BL1_1_DATA_SIZE)
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/partition/
Dregion_defs.h215 #define BL1_1_DATA_START (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE) macro
217 #define BL1_1_DATA_LIMIT (BL1_1_DATA_START + BL1_1_DATA_SIZE - 1)
219 #define BL1_2_DATA_START (BL1_1_DATA_START + BL1_1_DATA_SIZE)
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/device/source/armclang/
Drse_bl1_1.sct28 BL1_1_ER_DATA_START BL1_1_DATA_START EMPTY 0x0 {
51 ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL1_1_DATA_START + BL1_1_DATA_SIZE)
Drse_bl1_2.sct56 BL1_1_ER_DATA_START BL1_1_DATA_START EMPTY 0x0 {
59 BL1_1_ER_DATA_LIMIT BL1_1_DATA_START + BL1_1_DATA_SIZE EMPTY 0x0 {
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/source/armclang/
Dcorstone315_bl1_1.sct28 BL1_1_ER_DATA_START BL1_1_DATA_START EMPTY 0x0 {
60 ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL1_1_DATA_START + BL1_1_DATA_SIZE)
Dcorstone315_bl1_2.sct65 BL1_1_ER_DATA_START BL1_1_DATA_START EMPTY 0x0 {
68 BL1_1_ER_DATA_LIMIT BL1_1_DATA_START + BL1_1_DATA_SIZE EMPTY 0x0 {
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/device/source/gcc/
Drse_bl1_1.ld29 RAM (rwx) : ORIGIN = BL1_1_DATA_START, LENGTH = BL1_1_DATA_SIZE
137 . = BL1_1_DATA_START;
Drse_bl1_2.ld186 Image$$BL1_1_ER_DATA_START$$Base = BL1_1_DATA_START;
187 Image$$BL1_1_ER_DATA_LIMIT$$Base = BL1_1_DATA_START + BL1_1_DATA_SIZE;
/trusted-firmware-m-latest/platform/ext/target/arm/corstone1000/Device/Source/gcc/
Dcorstone1000_bl1_2.ld186 Image$$BL1_1_ER_DATA_START$$Base = BL1_1_DATA_START;
187 Image$$BL1_1_ER_DATA_LIMIT$$Base = BL1_1_DATA_START + BL1_2_DATA_SIZE;
Dcorstone1000_bl1_1.ld28 RAM (rwx) : ORIGIN = BL1_1_DATA_START, LENGTH = BL1_1_DATA_SIZE
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/source/gcc/
Dcorstone315_bl1_1.ld28 RAM (rwx) : ORIGIN = BL1_1_DATA_START, LENGTH = BL1_1_DATA_SIZE
135 . = BL1_1_DATA_START;
Dcorstone315_bl1_2.ld203 Image$$BL1_1_ER_DATA_START$$Base = BL1_1_DATA_START;
204 Image$$BL1_1_ER_DATA_LIMIT$$Base = BL1_1_DATA_START + BL1_1_DATA_SIZE;
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/bl1/
Dboot_hal_bl1_2.c229 : : "I" (BL1_1_DATA_START >> 16), "I" (BL1_1_DATA_START & 0xFFFF) : "r2" in setup_got_register()
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/source/iar/
Dcorstone315_bl1_2.icf64 place at address BL1_1_DATA_START {block BL1_1_ER_DATA};
Dcorstone315_bl1_1.icf60 place at address BL1_1_DATA_START {block BL1_1_ER_DATA};