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/trusted-firmware-m-3.7.0/platform/ext/accelerator/cc312/cc312-rom/
Dcc3xx_pka.h206 uint32_t cc3xx_lowlevel_pka_get_bit_size(cc3xx_pka_reg_id_t r0);
214 void cc3xx_lowlevel_pka_set_to_power_of_two(cc3xx_pka_reg_id_t r0, uint32_t power);
228 cc3xx_err_t cc3xx_lowlevel_pka_set_to_random(cc3xx_pka_reg_id_t r0, size_t bit_len);
240 cc3xx_err_t cc3xx_lowlevel_pka_set_to_random_within_modulus(cc3xx_pka_reg_id_t r0);
252 void cc3xx_lowlevel_pka_add(cc3xx_pka_reg_id_t r0, cc3xx_pka_reg_id_t r1, cc3xx_pka_reg_id_t res);
265 void cc3xx_lowlevel_pka_add_si(cc3xx_pka_reg_id_t r0, int32_t imm, cc3xx_pka_reg_id_t res);
278 void cc3xx_lowlevel_pka_sub(cc3xx_pka_reg_id_t r0, cc3xx_pka_reg_id_t r1, cc3xx_pka_reg_id_t res);
291 void cc3xx_lowlevel_pka_sub_si(cc3xx_pka_reg_id_t r0, int32_t imm, cc3xx_pka_reg_id_t res);
302 void cc3xx_lowlevel_pka_neg(cc3xx_pka_reg_id_t r0, cc3xx_pka_reg_id_t res);
318 void cc3xx_lowlevel_pka_mod_add(cc3xx_pka_reg_id_t r0, cc3xx_pka_reg_id_t r1, cc3xx_pka_reg_id_t re…
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Dcc3xx_pka.c540 bool r0_is_immediate, uint32_t r0, in opcode_construct() argument
602 opcode |= (r0 & 0b11111) << 18; in opcode_construct()
604 assert(r0 >= 0); in opcode_construct()
605 assert(r0 <= pka_reg_am_max); in opcode_construct()
606 assert(virt_reg_in_use[r0]); in opcode_construct()
608 ensure_virt_reg_is_mapped(r0); in opcode_construct()
609 opcode |= (virt_reg_phys_reg[r0] & 0b11111) << 18; in opcode_construct()
613 assert(virt_reg_is_mapped[r0]); in opcode_construct()
618 if (!r0_is_immediate && r0 != r1) { in opcode_construct()
619 assert(virt_reg_phys_reg[r1] != virt_reg_phys_reg[r0]); in opcode_construct()
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Dcc3xx_drbg_ctr.c19 cc3xx_pka_reg_id_t r0; in long_inc_int() local
26 r0 = cc3xx_lowlevel_pka_allocate_reg(); in long_inc_int()
29 cc3xx_lowlevel_pka_write_reg(r0, (const uint32_t *)acc, CC3XX_DRBG_CTR_BLOCKLEN); in long_inc_int()
32 cc3xx_lowlevel_pka_add_si(r0, is_increment ? 1 : -1, r0); in long_inc_int()
35 cc3xx_lowlevel_pka_read_reg(r0, acc, CC3XX_DRBG_CTR_BLOCKLEN); in long_inc_int()
Dcc3xx_drbg_hash.c30 cc3xx_pka_reg_id_t r0, r1; in long_acc() local
37 r0 = cc3xx_lowlevel_pka_allocate_reg(); in long_acc()
40 cc3xx_lowlevel_pka_write_reg(r0, (const uint32_t *)acc, CC3XX_DRBG_HASH_SEEDLEN); in long_acc()
49 cc3xx_lowlevel_pka_add(r0, r1, r0); in long_acc()
52 cc3xx_lowlevel_pka_read_reg(r0, (uint32_t *)acc, CC3XX_DRBG_HASH_SEEDLEN); in long_acc()
/trusted-firmware-m-3.7.0/platform/ext/target/cypress/psoc64/Device/Source/gcc/
Dstartup_psoc64_s.S110 mrs r0, PRIMASK
121 msr PRIMASK, r0
163 ldr r0, [r1, r3]
164 str r0, [r2, r3]
187 ldr r0, [r1,r3]
188 str r0, [r2,r3]
218 movs r0, 0
222 str r0, [r1, r2]
239 movs r0, 0
244 str r0, [r1, r2]
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Dstartup_psoc64_ns.S261 mrs r0, PRIMASK
273 msr PRIMASK, r0
315 ldr r0, [r1, r3]
316 str r0, [r2, r3]
339 ldr r0, [r1,r3]
340 str r0, [r2,r3]
370 movs r0, 0
374 str r0, [r1, r2]
391 movs r0, 0
396 str r0, [r1, r2]
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/trusted-firmware-m-3.7.0/secure_fw/spm/include/
Daapcs_local.h39 uint32_t r0; member
50 (v).u32_regs.r0 = (uint32_t)(a0); \
55 (v).u32_regs.r0 = (uint32_t)(a0)
Dtfm_arch.h91 uint32_t r0; member
163 (x)->r0 = (uint32_t)(param0); \
174 ((x)->r0 = (uint32_t)(r0_val))
/trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/
Dstartup_ARMCA5.s97 MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
98 ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
99 MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
/trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/
Dstartup_ARMCA7.s97 MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
98 ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
99 MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
/trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/
Dstartup_ARMCA9.s97 MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
98 ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
99 MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
/trusted-firmware-m-3.7.0/platform/ext/target/cypress/psoc64/Device/Source/armclang/
Dstartup_psoc64_s.s110 LDR r0, =__ramVectors
114 STR r3, [r0]
115 ADDS r0, r0, #4
122 LDR r0, =__ramVectors
131 STR r0, [r1]
Dstartup_psoc64_ns.s292 movs r0, #4
294 tst r0, r1
296 mrs r0, PSP
299 mrs r0, MSP
/trusted-firmware-m-3.7.0/platform/ext/target/cypress/psoc64/Device/Source/iar/
Dstartup_psoc64_s.s113 LDR r0, =__ramVectors
117 STR r3, [r0]
118 ADDS r0, r0, #4
125 LDR r0, =__ramVectors
130 STR r0, [r1]
Dstartup_psoc64_ns.s288 movs r0, #4
290 tst r0, r1
292 mrs r0, PSP
295 mrs r0, MSP
/trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/Core/Template/Device_A/Source/
Dstartup_Device.c100 MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register in Reset_Handler()
101 ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) in Reset_Handler()
102 MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register in Reset_Handler()
/trusted-firmware-m-3.7.0/lib/ext/cryptocell-312-runtime/codesafe/src/crypto_api/pki/rsa/
Drsa_genkey.c1348 uint32_t r0 = PKA_REG_N; /*mod*/ in RsaCalculateNandD() local
1371 PkaClearBlockOfRegs(r0/*firstReg*/, pkaRegsCount, LEN_ID_MAX_BITS); in RsaCalculateNandD()
1387 …PKA_MUL_LOW(LEN_ID_N_BITS, r0, rP/*OpA*/, rQ/*OpB*/); // use LEN_ID_N_BITS, since its size is 2*… in RsaCalculateNandD()
1390 PkaCopyDataFromPkaReg(pCcPubKey->n, 2*primeSizeInWords, r0/*srcReg*/); in RsaCalculateNandD()
1422 PKA_COPY(LEN_ID_N_BITS, r0/*dst*/, rP); in RsaCalculateNandD()
1425 PKA_COPY(LEN_ID_N_BITS, r0/*dst*/, rQ); in RsaCalculateNandD()
1439 PkaCopyDataIntoPkaReg(r0/*dstReg*/, LEN_ID_MAX_BITS, pCcPubKey->e/*src_ptr*/, in RsaCalculateNandD()
1444 PKA_DIV(LEN_ID_N_BITS, rQ/*Res not used*/, rP/*OpA=LCM*/, r0/*OpB=E*/); /*rP = LCM mod E*/ in RsaCalculateNandD()
1457 PKA_DIV(LEN_ID_N_PKA_REG_BITS, rD/*Res*/, rT/*OpA*/, r0/*OpB*/); /*rT = rT / e*/ in RsaCalculateNandD()
1628 int8_t r0, rP, rdP, rQ, rdQ, rQinv, rE; in RsaCalculateCrtParams() local
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/trusted-firmware-m-3.7.0/docs/security/security_advisories/
Dsvc_caller_sp_fetching_vulnerability.rst43 moveq r0, r2 ; if (EXC_RETURN.SPSEL == 0) r0 = msp;
44 movne r0, psp ; if (EXC_RETURN.SPSEL == 1) r0 = psp;
46 bl tfm_core_svc_handler ; r0 = sp(context), r1 = EXC_RETURN, r2 = msp
/trusted-firmware-m-3.7.0/secure_fw/spm/core/arch/
Dtfm_arch.c40 ((struct full_context_t *)p_ctx_ctrl->sp)->stat_ctx.r0 = ret_code; in tfm_arch_set_context_ret_code()
/trusted-firmware-m-3.7.0/secure_fw/spm/core/
Dtfm_svcalls.c125 if (sp_info.u32_regs.r0 != 0) { in init_spm_func_context()
126 sp = sp_info.u32_regs.r0; in init_spm_func_context()
Dinterrupt.c126 p_ctx_flih_ret->state_ctx.r0 = (uint32_t)result; in tfm_flih_return_to_isr()