| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/ |
| D | main.c | 75 IRQHandler_t const handler = IRQ_GetHandler(irqn); in IRQ_Handler() local
76 if (handler != NULL) { in IRQ_Handler()
78 handler(); in IRQ_Handler()
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/ |
| D | main.c | 85 IRQHandler_t const handler = IRQ_GetHandler(irqn); in IRQ_Handler() local
86 if (handler != NULL) { in IRQ_Handler()
88 handler(); in IRQ_Handler()
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| /trusted-firmware-m-3.7.0/docs/design_docs/dual-cpu/ |
| D | communication_prototype_between_nspe_and_spe_in_dual_core_systems.rst | 65 3. Inter-Processor Communication interrupt handler and mailbox handling in TF-M
69 eventually handled in target Secure Partition or corresponding handler.
155 1. Platform specific Inter-Processor Communication interrupt handler is
156 triggered after the mailbox event is asserted by NSPE. The interrupt handler
162 handler in TF-M SPM.
169 - `Inter-Processor Communication interrupt handler`_ discusses the
170 Inter-Processor Communication interrupt handler
177 Inter-Processor Communication interrupt handler
181 interrupt handler to deal with the Inter-Processor Communication interrupt
183 The platform specific interrupt handler shall complete the interrupt
[all …]
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| D | mailbox_design_on_dual_core_system.rst | 199 asserted in SPE. The interrupt handler activates SPE mailbox to process the
252 In SPE, the Inter-Processor Communication interrupt handler should deal with the
255 Communication interrupt handler.
257 NSPE can implement an interrupt handler or a polling of notification status to
341 NS mailbox interrupt handler.
371 Communication interrupts. The interrupt handler invokes
450 Platform specific Inter-Processor Communication interrupt handler in SPE should
890 specific Inter-Processor Communication interrupt handler.
1002 IRQ handler.
1011 critical section of NSPE mailbox queue in an IRQ handler.
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/RTOS2/Source/ |
| D | os_tick_ptim.c | 40 int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { in OS_Tick_Setup() argument
89 IRQ_SetHandler(PrivTimer_IRQn, handler); in OS_Tick_Setup()
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| D | os_tick_gtim.c | 49 int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { in OS_Tick_Setup() argument
106 IRQ_SetHandler(GTIM_IRQ_NUM, handler); in OS_Tick_Setup()
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| D | os_systick.c | 40 __WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { in OS_Tick_Setup() argument
42 (void)handler; in OS_Tick_Setup()
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/RTOS2/Include/ |
| D | os_tick.h | 45 int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler);
|
| /trusted-firmware-m-3.7.0/docs/security/security_advisories/ |
| D | svc_caller_sp_fetching_vulnerability.rst | 5 | Title | Invoking Secure functions from handler mode may cause TF-M |
33 handles requests from SPE and NSPE in a unified SVC handler. The TF-M SVC
34 handler code relies on the 'SPSEL' bit in 'EXC_RETURN' to get the caller stack
54 handling based on EXC_RETURN.SPSEL, hence the SVC handler accesses the wrong
56 To prevent this vulnerability, TF-M secure SVC handler should fetch the right
57 stack pointer register by checking both the PE mode and SPSEL bit. The handler
68 handler gets the SVC number by referencing the memory at the 2 bytes subtracted
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| D | debug_log_vulnerability.rst | 30 Since the SVC handler has the highest privilege level and full memory
62 is added to the logging function of the SVC handler. If the check fails
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| D | index.rst | 23 | |TFMV-2| | Invoking Secure functions from handler mode may cause TF-M IPC |
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| D | stack_seal_vulnerability.rst | 81 secure interrupt handling. But if the de-privileged handler makes a
102 `ARMv8-M ARM`_ which is to seal the base of both handler mode stack (MSP_S)
104 of MSP_S before handing control over to de-privileged interrupt handler.
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| /trusted-firmware-m-3.7.0/platform/ext/target/nxp/common/Native_Driver/drivers/ |
| D | fsl_flexcomm.h | 56 void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
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| D | fsl_flexcomm.c | 149 void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) in FLEXCOMM_SetIRQHandler() argument
159 s_flexcommIrqHandler[instance] = handler; in FLEXCOMM_SetIRQHandler()
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| D | fsl_usart.c | 767 usart_to_flexcomm_t handler; in USART_TransferCreateHandle() local
768 handler.usart_master_handler = USART_TransferHandleIRQ; in USART_TransferCreateHandle()
787 FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); in USART_TransferCreateHandle()
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| /trusted-firmware-m-3.7.0/docs/design_docs/software/ |
| D | tfm_cooperative_scheduling_rules.rst | 50 - A NSPE exception handler returns from NSPE to pre-empted SPE context
51 - A SPE exception handler returns from SPE to pre-empted NSPE context
63 1. **The NSPE exception handler is allowed to trigger a NSPE context switch**
87 2. **The SPE interrupt handler is allowed to trigger a SPE context switch**
126 **handler must return to preempted NSPE context.**
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/Core/Source/ |
| D | irq_ctrl_gic.c | 61 __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { in IRQ_SetHandler() argument
65 IRQTable[irqn] = handler; in IRQ_SetHandler()
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/Core/Include/a-profile/ |
| D | irq_ctrl.h | 99 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
|
| /trusted-firmware-m-3.7.0/platform/ext/target/cypress/psoc64/Device/Source/armclang/ |
| D | startup_psoc64_s.s | 30 ; Address of the NMI handler in ROM
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| /trusted-firmware-m-3.7.0/platform/ext/target/cypress/psoc64/Device/Source/iar/ |
| D | startup_psoc64_s.s | 30 ; Address of the NMI handler in ROM
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| /trusted-firmware-m-3.7.0/docs/design_docs/services/ |
| D | secure_partition_manager.rst | 396 The API handler:
517 interrupt handler can preempt an ongoing interrupt execution.
545 - The exception handler priority needs to be decided.
546 - Boost the secure handler mode priority to prevent NSPE from preempting SPE
547 handler mode execution(`AIRCR.PRIS`).
626 - The SVC handler calls SPM internal routines, and eventually back to the
627 handler before an exit.
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ |
| D | gcc_linker_script.ld | 59 * Reset_Handler : Entry of reset handler
|
| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ |
| D | gcc_linker_script.ld | 59 * Reset_Handler : Entry of reset handler
|
| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ |
| D | gcc_linker_script.ld | 59 * Reset_Handler : Entry of reset handler
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ |
| D | gcc_linker_script.ld | 59 * Reset_Handler : Entry of reset handler
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