1 /* 2 * Copyright (c) 2016-2018 Arm Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file uart_pl011_drv.h 19 * \brief Driver for ARM UART PL011. 20 */ 21 22 #ifndef __UART_PL011_DRV_H__ 23 #define __UART_PL011_DRV_H__ 24 25 #include <stdint.h> 26 #include <stdbool.h> 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /** 33 * \brief ARM UART PL011 state types 34 */ 35 enum uart_pl011_state_t { 36 UART_PL011_UNINITIALIZED = 0x0u, 37 UART_PL011_INITIALIZED = 0x1u, 38 }; 39 40 #define UART_PL011_UARTRSR_FE_ERR_OFF 0x0u 41 /*!< Receive Status Register Frame Error bit field offset */ 42 #define UART_PL011_UARTRSR_PE_ERR_OFF 0x1u 43 /*!< Receive Status Register Parity Error bit field offset */ 44 #define UART_PL011_UARTRSR_BE_ERR_OFF 0x2u 45 /*!< Receive Status Register Break Error bit field offset */ 46 #define UART_PL011_UARTRSR_OE_ERR_OFF 0x3u 47 /*!< Receive Status Register Overrun Error bit field offset */ 48 49 #define UART_PL011_RX_ERR_MASK ( \ 50 0x1u<<UART_PL011_UARTRSR_FE_ERR_OFF \ 51 | 0x1u<<UART_PL011_UARTRSR_PE_ERR_OFF \ 52 | 0x1u<<UART_PL011_UARTRSR_BE_ERR_OFF \ 53 | 0x1u<<UART_PL011_UARTRSR_OE_ERR_OFF) 54 /*!< Receive Status Register Error Mask */ 55 56 #define UART_PL011_UARTFR_CTS_OFF 0x0u 57 /*!< Flag Register Clear to send bit field offset */ 58 #define UART_PL011_UARTFR_DSR_OFF 0x1u 59 /*!< Flag Register Data set ready bit field offset */ 60 #define UART_PL011_UARTFR_DCD_OFF 0x2u 61 /*!< Flag Register Data carrier detect bit field offset */ 62 #define UART_PL011_UARTFR_BUSYBIT_OFF 0x3u 63 /*!< Flag Register Busy bit field offset */ 64 #define UART_PL011_UARTFR_RX_FIFO_EMPTY_OFF 0x4u 65 /*!< Flag Register Receive fifo empty bit field offset */ 66 #define UART_PL011_UARTFR_TX_FIFO_FULL_OFF 0x5u 67 /*!< Flag Register Transmit fifo full bit field offset */ 68 #define UART_PL011_UARTFR_RX_FIFO_FULL_OFF 0x6u 69 /*!< Flag Register Receive fifo full bit field offset */ 70 #define UART_PL011_UARTFR_TX_FIFO_EMPTY_OFF 0x7u 71 /*!< Flag Register Transmit fifo empty bit field offset */ 72 #define UART_PL011_UARTFR_RI_OFF 0x8u 73 /*!< Flag Register Ring indicator bit field offset */ 74 75 #define UART_PL011_UARTLCR_H_BRK_OFF 0x0u 76 /*!< Line Control Register Break bit field offset */ 77 #define UART_PL011_UARTLCR_H_PEN_OFF 0x1u 78 /*!< Line Control Register Parity enable bit field offset */ 79 #define UART_PL011_UARTLCR_H_EPS_OFF 0x2u 80 /*!< Line Control Register Even parity select bit field offset */ 81 #define UART_PL011_UARTLCR_H_STP2_OFF 0x3u 82 /*!< Line Control Register 2 stop bit select bit field offset */ 83 #define UART_PL011_UARTLCR_H_FEN_OFF 0x4u 84 /*!< Line Control Register Fifo enable bit field offset */ 85 #define UART_PL011_UARTLCR_H_WLEN_OFF 0x5u 86 /*!< Line Control Register Word length bit field offset */ 87 #define UART_PL011_UARTLCR_H_SPS_OFF 0x7u 88 /*!< Line Control Register Stick parity select bit field offset */ 89 90 /** 91 * \brief Allowed word length options UART PL011 92 */ 93 enum uart_pl011_wlen_t { 94 UART_PL011_WLEN_5 = (0x0u<<UART_PL011_UARTLCR_H_WLEN_OFF), 95 UART_PL011_WLEN_6 = (0x1u<<UART_PL011_UARTLCR_H_WLEN_OFF), 96 UART_PL011_WLEN_7 = (0x2u<<UART_PL011_UARTLCR_H_WLEN_OFF), 97 UART_PL011_WLEN_8 = (0x3u<<UART_PL011_UARTLCR_H_WLEN_OFF), 98 }; 99 100 /** 101 * \brief Allowed parity options UART PL011 102 */ 103 enum uart_pl011_parity_t { 104 UART_PL011_PARITY_DISABLED = (0x0u<<UART_PL011_UARTLCR_H_PEN_OFF), 105 UART_PL011_PARITY_ODD = (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF 106 | 0x0u<<UART_PL011_UARTLCR_H_EPS_OFF 107 | 0x0u<<UART_PL011_UARTLCR_H_SPS_OFF), 108 UART_PL011_PARITY_EVEN = (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF 109 | 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF 110 | 0x0u<<UART_PL011_UARTLCR_H_SPS_OFF), 111 UART_PL011_PARITY_STICKY_ONE= (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF 112 | 0x0u<<UART_PL011_UARTLCR_H_EPS_OFF 113 | 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF), 114 UART_PL011_PARITY_STICKY_ZERO= (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF 115 | 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF 116 | 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF), 117 }; 118 119 /** 120 * \brief Allowed stop bits options UART PL011 121 */ 122 enum uart_pl011_stopbit_t { 123 UART_PL011_STOPBIT_1 = (0x0u<<UART_PL011_UARTLCR_H_STP2_OFF), 124 UART_PL011_STOPBIT_2 = (0x1u<<UART_PL011_UARTLCR_H_STP2_OFF), 125 }; 126 127 #define UART_PL011_UARTCR_UARTEN_OFF 0x0u 128 /*!< Control Register Uart enable bit field offset */ 129 #define UART_PL011_UARTCR_SIREN_OFF 0x1u 130 /*!< Control Register Sir enable bit field offset */ 131 #define UART_PL011_UARTCR_SIRLP_OFF 0x2u 132 /*!< Control Register Sir low power bit field offset */ 133 #define UART_PL011_UARTCR_LBE_OFF 0x7u 134 /*!< Control Register Loop back enable bit field offset */ 135 #define UART_PL011_UARTCR_TXE_OFF 0x8u 136 /*!< Control Register Transmit enable bit field offset */ 137 #define UART_PL011_UARTCR_RXE_OFF 0x9u 138 /*!< Control Register Receive enable bit field offset */ 139 #define UART_PL011_UARTCR_DTR_OFF 0xAu 140 /*!< Control Register Data transmit ready bit field offset */ 141 #define UART_PL011_UARTCR_RTS_OFF 0xBu 142 /*!< Control Register Request to send bit field offset */ 143 #define UART_PL011_UARTCR_OUT1_OFF 0xCu 144 /*!< Control Register Out1 bit field offset */ 145 #define UART_PL011_UARTCR_OUT2_OFF 0xDu 146 /*!< Control Register Out2 bit field offset */ 147 #define UART_PL011_UARTCR_RTSE_OFF 0xEu 148 /*!< Control Register RTS hardware flow control enable bit field offset */ 149 #define UART_PL011_UARTCR_CTSE_OFF 0xFu 150 /*!< Control Register CTS hardware flow control enable bit field offset */ 151 152 #define UART_PL011_UARTIFLS_TX_OFF 0x0u 153 /*!< Interrupt FIFO Level Select Register Transmit bit field offset */ 154 #define UART_PL011_UARTIFLS_RX_OFF 0x3u 155 /*!< Interrupt FIFO Level Select Register Receive bit field offset */ 156 157 /** 158 * \brief UART Receive fifo levels 159 */ 160 enum uart_pl011_rx_fifo_lvl_t { 161 UART_PL011_RX_FIFO_LVL_1_8 = (0x0u<<UART_PL011_UARTIFLS_RX_OFF), 162 UART_PL011_RX_FIFO_LVL_1_4 = (0x1u<<UART_PL011_UARTIFLS_RX_OFF), 163 UART_PL011_RX_FIFO_LVL_1_2 = (0x2u<<UART_PL011_UARTIFLS_RX_OFF), 164 UART_PL011_RX_FIFO_LVL_3_4 = (0x3u<<UART_PL011_UARTIFLS_RX_OFF), 165 UART_PL011_RX_FIFO_LVL_7_8 = (0x4u<<UART_PL011_UARTIFLS_RX_OFF), 166 }; 167 168 /** 169 * \brief UART Transmit fifo levels 170 */ 171 enum uart_pl011_tx_fifo_lvl_t { 172 UART_PL011_TX_FIFO_LVL_1_8 = (0x0u<<UART_PL011_UARTIFLS_TX_OFF), 173 UART_PL011_TX_FIFO_LVL_1_4 = (0x1u<<UART_PL011_UARTIFLS_TX_OFF), 174 UART_PL011_TX_FIFO_LVL_1_2 = (0x2u<<UART_PL011_UARTIFLS_TX_OFF), 175 UART_PL011_TX_FIFO_LVL_3_4 = (0x3u<<UART_PL011_UARTIFLS_TX_OFF), 176 UART_PL011_TX_FIFO_LVL_7_8 = (0x4u<<UART_PL011_UARTIFLS_TX_OFF), 177 }; 178 179 #define UART_PL011_UARTDMACR_RXEN_OFF 0x0u 180 /*!< DMA Control Register Receive DMA enable bit field offset */ 181 #define UART_PL011_UARTDMACR_TXEN_OFF 0x1u 182 /*!< DMA Control Register Transmit DMA enable bit field offset */ 183 #define UART_PL011_UARTDMACR_ON_ERR_OFF 0x2u 184 /*!< DMA Control Register DMA on error bit field offset */ 185 186 /** 187 * \brief Transmit DMA Enable 188 */ 189 enum uart_pl011_tx_dma_t { 190 UART_PL011_TX_DMA_DISABLE = (0x0u<<UART_PL011_UARTDMACR_TXEN_OFF), 191 UART_PL011_TX_DMA_ENABLE = (0x1u<<UART_PL011_UARTDMACR_TXEN_OFF), 192 }; 193 194 /** 195 * \brief Receive DMA Enable 196 */ 197 enum uart_pl011_rx_dma_t { 198 UART_PL011_RX_DMA_DISABLE = (0x0u<<UART_PL011_UARTDMACR_RXEN_OFF), 199 UART_PL011_RX_DMA_ENABLE = (0x1u<<UART_PL011_UARTDMACR_RXEN_OFF), 200 UART_PL011_RX_DMA_ON_ERR_EN= (0x1u<<UART_PL011_UARTDMACR_RXEN_OFF 201 | 0x1u<<UART_PL011_UARTDMACR_ON_ERR_OFF), 202 }; 203 204 #define UART_PL011_INTR_RI_OFF 0x0u 205 /*!< Ring indicator interrupt bit field offset */ 206 #define UART_PL011_INTR_CTS_OFF 0x1u 207 /*!< Clear to send interrupt bit field offset */ 208 #define UART_PL011_INTR_DCD_OFF 0x2u 209 /*!< Data carrier detect interrupt bit field offset */ 210 #define UART_PL011_INTR_DSR_OFF 0x3u 211 /*!< Data set ready interrupt bit field offset */ 212 #define UART_PL011_INTR_RX_OFF 0x4u 213 /*!< Receive interrupt bit field offset */ 214 #define UART_PL011_INTR_TX_OFF 0x5u 215 /*!< Transmit interrupt bit field offset */ 216 #define UART_PL011_INTR_RT_OFF 0x6u 217 /*!< Receive timeout interrupt bit field offset */ 218 #define UART_PL011_INTR_FE_OFF 0x7u 219 /*!< Frame error interrupt bit field offset */ 220 #define UART_PL011_INTR_PE_OFF 0x8u 221 /*!< Parity error interrupt bit field offset */ 222 #define UART_PL011_INTR_BE_OFF 0x9u 223 /*!< Break error interrupt bit field offset */ 224 #define UART_PL011_INTR_OE_OFF 0xAu 225 /*!< Overrun error interrupt bit field offset */ 226 227 /** 228 * \brief ARM UART PL011 Interrupt data structure 229 */ 230 enum uart_pl011_intr_t { 231 UART_PL011_RI_INTR_MASK = (0x1u<<UART_PL011_INTR_RI_OFF), 232 UART_PL011_CTS_INTR_MASK = (0x1u<<UART_PL011_INTR_CTS_OFF), 233 UART_PL011_DCD_INTR_MASK = (0x1u<<UART_PL011_INTR_DCD_OFF), 234 UART_PL011_DSR_INTR_MASK = (0x1u<<UART_PL011_INTR_DSR_OFF), 235 UART_PL011_RX_INTR_MASK = (0x1u<<UART_PL011_INTR_RX_OFF), 236 UART_PL011_TX_INTR_MASK = (0x1u<<UART_PL011_INTR_TX_OFF), 237 UART_PL011_RT_INTR_MASK = (0x1u<<UART_PL011_INTR_RT_OFF), 238 UART_PL011_FE_INTR_MASK = (0x1u<<UART_PL011_INTR_FE_OFF), 239 UART_PL011_PE_INTR_MASK = (0x1u<<UART_PL011_INTR_PE_OFF), 240 UART_PL011_BE_INTR_MASK = (0x1u<<UART_PL011_INTR_BE_OFF), 241 UART_PL011_OE_INTR_MASK = (0x1u<<UART_PL011_INTR_OE_OFF), 242 }; 243 244 /** 245 * \brief ARM UART PL011 error enumeration types 246 */ 247 enum uart_pl011_error_t { 248 UART_PL011_ERR_NONE = (0x0u), 249 UART_PL011_ERR_RX_FRAME = (0x1u<<UART_PL011_UARTRSR_FE_ERR_OFF), 250 UART_PL011_ERR_RX_PARITY = (0x1u<<UART_PL011_UARTRSR_PE_ERR_OFF), 251 UART_PL011_ERR_RX_BREAK = (0x1u<<UART_PL011_UARTRSR_BE_ERR_OFF), 252 UART_PL011_ERR_RX_OVERFLOW = (0x1u<<UART_PL011_UARTRSR_OE_ERR_OFF), 253 UART_PL011_ERR_INVALID_ARG = (UART_PL011_RX_ERR_MASK + 1), 254 UART_PL011_ERR_NOT_READY, 255 UART_PL011_ERR_INVALID_BAUD, 256 UART_PL011_ERR_NOT_INIT, 257 }; 258 259 /** 260 * \brief ARM UART PL011 device configuration structure 261 */ 262 struct uart_pl011_dev_cfg_t { 263 const uint32_t base; /*!< UART PL011 base address */ 264 const uint32_t def_baudrate; /*!< Default baudrate */ 265 const enum uart_pl011_wlen_t def_wlen; /*!< Default word length */ 266 const enum uart_pl011_parity_t def_parity; /*!< Default parity */ 267 const enum uart_pl011_stopbit_t def_stopbit; /*!< Default stop bits */ 268 }; 269 270 /** 271 * \brief ARM UART PL011 device data structure 272 */ 273 struct uart_pl011_dev_data_t { 274 enum uart_pl011_state_t state; /*!< UART State */ 275 uint32_t uart_clk; /*!< UART clock */ 276 uint32_t baudrate; /*!< Baudrate */ 277 }; 278 279 /** 280 * \brief ARM UART PL011 device structure 281 */ 282 struct uart_pl011_dev_t { 283 const struct uart_pl011_dev_cfg_t* const cfg; 284 /*!< UART PL011 configuration */ 285 struct uart_pl011_dev_data_t* const data; 286 /*!< UART PL011 data */ 287 }; 288 289 /** 290 * \brief Initializes UART PL011. 291 * 292 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 293 * \param[in] uart_clk UART clock used by the device. 294 * 295 * It uses the default baudrate to configure UART. 296 * 297 * \return Returns error code as specified in \ref uart_pl011_error_t 298 * 299 * \note This API should be called before calling any of the below UART APIs. 300 * \note This function doesn't check if dev is NULL. 301 */ 302 enum uart_pl011_error_t uart_pl011_init(struct uart_pl011_dev_t* dev, 303 uint32_t uart_clk); 304 305 /** 306 * \brief Uninitializes UART PL011. 307 * 308 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 309 * 310 * 311 * \note This function doesn't check if dev is NULL. 312 */ 313 void uart_pl011_uninit(struct uart_pl011_dev_t* dev); 314 315 /** 316 * \brief Returns the UART PL011 operational state. 317 * 318 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 319 * 320 * \return Returns the UART operational state 321 * 322 * \note This function doesn't check if dev is NULL. 323 */ 324 enum uart_pl011_state_t uart_pl011_get_state(struct uart_pl011_dev_t* dev); 325 326 /** 327 * \brief Sets the UART baudrate. 328 * 329 * \param[in] dev UART device struct \ref uart_pl011_dev_t 330 * \param[in] baudrate New baudrate. 331 * 332 * \return Returns error code as specified in \ref uart_pl011_error_t 333 * 334 * \note This function doesn't check if dev is NULL. 335 */ 336 enum uart_pl011_error_t uart_pl011_set_baudrate( 337 struct uart_pl011_dev_t* dev, uint32_t baudrate); 338 339 /** 340 * \brief Gets the UART baudrate. 341 * 342 * \param[in] dev UART device struct \ref uart_pl011_dev_t 343 * 344 * \return Returns the UART baudrate. 345 * 346 * \note The UART should be in valid state before calling this API 347 * \ref uart_pl011_get_state should return UART_PL011_INITIALIZED 348 * \note This function doesn't check if dev is NULL. 349 */ 350 uint32_t uart_pl011_get_baudrate(struct uart_pl011_dev_t* dev); 351 352 /** 353 * \brief Enables UART interrupts 354 * 355 * \param[in] dev UART device struct \ref uart_pl011_dev_t 356 * \param[in] mask Bit mask for enabling/disabling interrupts 357 * \ref uart_pl011_intr_t 358 * 359 * \note User is responsible to configure the interrupt vector and 360 * the interrupt controller. 361 * \note This function doesn't check if dev is NULL. 362 */ 363 void uart_pl011_enable_intr(struct uart_pl011_dev_t* dev, 364 enum uart_pl011_intr_t mask); 365 366 /** 367 * \brief Disables UART interrupts 368 * 369 * \param[in] dev UART device struct \ref uart_pl011_dev_t 370 * \param[in] mask Bit mask for enabling/disabling interrupts 371 * \ref uart_pl011_intr_t 372 * 373 * \note This function doesn't check if dev is NULL. 374 */ 375 void uart_pl011_disable_intr(struct uart_pl011_dev_t* dev, 376 enum uart_pl011_intr_t mask); 377 378 /** 379 * \brief Clears UART Interrupt 380 * 381 * \param[in] dev UART device struct \ref uart_pl011_dev_t 382 * \param[in] mask Bit mask for clearing interrupts \ref uart_pl011_intr_t 383 * 384 * \note This function doesn't check if dev is NULL. 385 */ 386 void uart_pl011_clear_intr(struct uart_pl011_dev_t* dev, 387 enum uart_pl011_intr_t mask); 388 389 /** 390 * \brief Returns the UART Masked interrupt status 391 * 392 * \param[in] dev UART device struct \ref uart_pl011_dev_t 393 * 394 * \return Masked interrupt status \ref uart_pl011_intr_t 395 * 396 * \note This function doesn't check if dev is NULL. 397 */ 398 enum uart_pl011_intr_t uart_pl011_get_masked_intr_status( 399 struct uart_pl011_dev_t* dev); 400 401 /** 402 * \brief Returns the UART Raw interrupt status 403 * 404 * \param[in] dev UART device struct \ref uart_pl011_dev_t 405 * 406 * \return Raw interrupt status \ref uart_pl011_intr_t 407 * 408 * \note This function doesn't check if dev is NULL. 409 */ 410 enum uart_pl011_intr_t uart_pl011_get_raw_intr_status( 411 struct uart_pl011_dev_t* dev); 412 413 /** 414 * \brief Sets receive fifo levels 415 * 416 * \param[in] dev UART device struct \ref uart_pl011_dev_t 417 * \param[in] rx_lvl Receive fifo levels \ref uart_pl011_rx_fifo_lvl_t 418 * 419 * \note This function doesn't check if dev is NULL. 420 */ 421 void uart_pl011_set_rx_fifo_lvl(struct uart_pl011_dev_t* dev, 422 enum uart_pl011_rx_fifo_lvl_t rx_lvl); 423 424 /** 425 * \brief Sets transmit fifo levels 426 * 427 * \param[in] dev UART device struct \ref uart_pl011_dev_t 428 * \param[in] tx_lvl Transmit fifo levels \ref uart_pl011_tx_fifo_lvl_t 429 * 430 * \note This function doesn't check if dev is NULL. 431 */ 432 void uart_pl011_set_tx_fifo_lvl(struct uart_pl011_dev_t* dev, 433 enum uart_pl011_tx_fifo_lvl_t tx_lvl); 434 435 /** 436 * \brief Enables/Disables transmit UART DMA 437 * 438 * \param[in] dev UART device struct \ref uart_pl011_dev_t 439 * \param[in] enable To enable/disable the UART transmit DMA 440 * \ref uart_pl011_tx_dma_t 441 * 442 * \note This function doesn't check if dev is NULL. 443 */ 444 void uart_pl011_set_tx_dma(struct uart_pl011_dev_t* dev, 445 enum uart_pl011_tx_dma_t enable); 446 447 /** 448 * \brief Enables/Disables receive UART DMA 449 * 450 * \param[in] dev UART device struct \ref uart_pl011_dev_t 451 * \param[in] enable To enable/disable the UART receive DMA 452 * \ref uart_pl011_rx_dma_t 453 * 454 * \note This function doesn't check if dev is NULL. 455 */ 456 void uart_pl011_set_rx_dma(struct uart_pl011_dev_t* dev, 457 enum uart_pl011_rx_dma_t enable); 458 459 /** 460 * \brief Check if the UART dev is readable 461 * 462 * \param[in] dev UART device struct \ref uart_pl011_dev_t 463 * 464 * \return Returns bool, true if UART is readable, false otherwise 465 * 466 * \note This function doesn't check if dev is NULL. 467 */ 468 bool uart_pl011_is_readable(struct uart_pl011_dev_t* dev); 469 470 /** 471 * \brief Reads one byte from UART dev. 472 * 473 * \param[in] dev UART device struct \ref uart_pl011_dev_t 474 * \param[out] byte Pointer to byte that is populated with the data to be read 475 * 476 * \return Error status (if any) as specified in 477 * \ref uart_pl011_error_t 478 * 479 * \note This API should only be called when the device is readable 480 * \ref uart_pl011_is_readable 481 * \note For better performance, this function doesn't check if dev and byte 482 * pointer are NULL, and if the driver is initialized. 483 */ 484 enum uart_pl011_error_t uart_pl011_read(struct uart_pl011_dev_t* dev, 485 uint8_t* byte); 486 487 /** 488 * \brief Check if the UART dev is writable 489 * 490 * \param[in] dev UART device struct \ref uart_pl011_dev_t 491 * 492 * \return Returns bool, true if UART is writable, false otherwise 493 * 494 * \note This function doesn't check if dev is NULL. 495 */ 496 bool uart_pl011_is_writable(struct uart_pl011_dev_t* dev); 497 498 /** 499 * \brief Writes a byte to UART dev. 500 * 501 * \param[in] dev UART device struct \ref uart_pl011_dev_t 502 * \param[in] byte One byte to write. 503 * 504 * \note This API should only be called when the device is writable 505 * \ref uart_pl011_is_writable 506 * \note For better performance, this function doesn't check if dev is NULL and 507 * if the driver is initialized to have better performance. 508 */ 509 void uart_pl011_write(struct uart_pl011_dev_t* dev, uint8_t byte); 510 511 /** 512 * \brief Sets the UART format. 513 * 514 * \param[in] dev UART device struct \ref uart_pl011_dev_t 515 * \param[in] word_len UART word length \ref uart_pl011_wlen_t 516 * \param[in] parity UART parity \ref uart_pl011_parity_t 517 * \param[in] stop_bits UART stop bits \ref uart_pl011_stopbit_t 518 * 519 * \return Returns error code as specified in \ref uart_pl011_error_t 520 * 521 * \note This function doesn't check if dev is NULL. 522 */ 523 enum uart_pl011_error_t uart_pl011_set_format(struct uart_pl011_dev_t* dev, 524 enum uart_pl011_wlen_t word_len, 525 enum uart_pl011_parity_t parity, 526 enum uart_pl011_stopbit_t stop_bits); 527 528 /** 529 * \brief Enables the UART fifo. 530 * 531 * \param[in] dev UART device struct \ref uart_pl011_dev_t 532 * 533 * 534 * \note This function doesn't check if dev is NULL. 535 */ 536 void uart_pl011_enable_fifo(struct uart_pl011_dev_t* dev); 537 538 /** 539 * \brief Disables the UART fifo. 540 * 541 * \param[in] dev UART device struct \ref uart_pl011_dev_t 542 * 543 * 544 * \note This function doesn't check if dev is NULL. 545 */ 546 void uart_pl011_disable_fifo(struct uart_pl011_dev_t* dev); 547 548 /** 549 * \brief Enables break transmission from UART dev. 550 * 551 * \param[in] dev UART device struct \ref uart_pl011_dev_t 552 * 553 * \note For better performance, this function doesn't check if dev is NULL and 554 * if the driver is initialized to have better performance. 555 */ 556 void uart_pl011_enable_break(struct uart_pl011_dev_t* dev); 557 558 /** 559 * \brief Disables break transmission from UART dev. 560 * 561 * \param[in] dev UART device struct \ref uart_pl011_dev_t 562 * 563 * \note For better performance, this function doesn't check if dev is NULL and 564 * if the driver is initialized to have better performance. 565 */ 566 void uart_pl011_disable_break(struct uart_pl011_dev_t* dev); 567 568 /** 569 * \brief Enables CTS flow control in UART PL011 570 * 571 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 572 * 573 * \note This function doesn't check if dev is NULL. 574 */ 575 void uart_pl011_enable_cts_flowcontrol(struct uart_pl011_dev_t* dev); 576 577 /** 578 * \brief Disables CTS flow control in UART PL011. 579 * 580 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 581 * 582 * \note This function doesn't check if dev is NULL. 583 */ 584 void uart_pl011_disable_cts_flowcontrol(struct uart_pl011_dev_t* dev); 585 586 /** 587 * \brief Enables RTS flow control in UART PL011 588 * 589 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 590 * 591 * \note This function doesn't check if dev is NULL. 592 */ 593 void uart_pl011_enable_rts_flowcontrol(struct uart_pl011_dev_t* dev); 594 595 /** 596 * \brief Disables RTS flow control in UART PL011. 597 * 598 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 599 * 600 * \note This function doesn't check if dev is NULL. 601 */ 602 void uart_pl011_disable_rts_flowcontrol(struct uart_pl011_dev_t* dev); 603 604 /** 605 * \brief Enables Data carrier detect in UART PL011 606 * 607 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 608 * 609 * \note For DTE nUARTOut1 can be used as Data carrier detect (DCD). 610 * \note This function doesn't check if dev is NULL. 611 */ 612 void uart_pl011_enable_dcd(struct uart_pl011_dev_t* dev); 613 614 /** 615 * \brief Disables Data carrier detect in UART PL011. 616 * 617 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 618 * 619 * \note For DTE nUARTOut1 can be used as Data carrier detect (DCD). 620 * \note This function doesn't check if dev is NULL. 621 */ 622 void uart_pl011_disable_dcd(struct uart_pl011_dev_t* dev); 623 624 /** 625 * \brief Enables RTS signal for UART dev. 626 * 627 * \param[in] dev UART device struct \ref uart_pl011_dev_t 628 * 629 * \note For better performance, this function doesn't check if dev is NULL and 630 * if the driver is initialized to have better performance. 631 */ 632 void uart_pl011_set_rts(struct uart_pl011_dev_t* dev); 633 634 /** 635 * \brief Disables RTS signal for UART dev. 636 * 637 * \param[in] dev UART device struct \ref uart_pl011_dev_t 638 * 639 * \note For better performance, this function doesn't check if dev is NULL and 640 * if the driver is initialized to have better performance. 641 */ 642 void uart_pl011_clear_rts(struct uart_pl011_dev_t* dev); 643 644 /** 645 * \brief Enables DTR signal for UART dev. 646 * 647 * \param[in] dev UART device struct \ref uart_pl011_dev_t 648 * 649 * \note For better performance, this function doesn't check if dev is NULL and 650 * if the driver is initialized to have better performance. 651 */ 652 void uart_pl011_set_dtr(struct uart_pl011_dev_t* dev); 653 654 /** 655 * \brief Disables DTR signal for UART dev. 656 * 657 * \param[in] dev UART device struct \ref uart_pl011_dev_t 658 * 659 * \note For better performance, this function doesn't check if dev is NULL and 660 * if the driver is initialized to have better performance. 661 */ 662 void uart_pl011_clear_dtr(struct uart_pl011_dev_t* dev); 663 664 /** 665 * \brief Enables reception in UART PL011. 666 * 667 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 668 * 669 * 670 * \note This function doesn't check if dev is NULL. 671 */ 672 void uart_pl011_enable_receive(struct uart_pl011_dev_t* dev); 673 674 /** 675 * \brief Disables reception in UART PL011. 676 * 677 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 678 * 679 * 680 * \note This function doesn't check if dev is NULL. 681 */ 682 void uart_pl011_disable_receive(struct uart_pl011_dev_t* dev); 683 684 /** 685 * \brief Enables transmission in UART PL011. 686 * 687 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 688 * 689 * 690 * \note This function doesn't check if dev is NULL. 691 */ 692 void uart_pl011_enable_transmit(struct uart_pl011_dev_t* dev); 693 694 /** 695 * \brief Disables transmission in UART PL011. 696 * 697 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 698 * 699 * 700 * \note This function doesn't check if dev is NULL. 701 */ 702 void uart_pl011_disable_transmit(struct uart_pl011_dev_t* dev); 703 704 /** 705 * \brief Enables loopback in UART dev. 706 * 707 * \param[in] dev UART device struct \ref uart_pl011_dev_t 708 * 709 * \note For better performance, this function doesn't check if dev is NULL and 710 * if the driver is initialized to have better performance. 711 */ 712 void uart_pl011_set_loopback(struct uart_pl011_dev_t* dev); 713 714 /** 715 * \brief Disables loopback in UART dev. 716 * 717 * \param[in] dev UART device struct \ref uart_pl011_dev_t 718 * 719 * \note For better performance, this function doesn't check if dev is NULL and 720 * if the driver is initialized to have better performance. 721 */ 722 void uart_pl011_clear_loopback(struct uart_pl011_dev_t* dev); 723 724 /** 725 * \brief Enables IrDA Sir low power mode in UART dev. 726 * 727 * \param[in] dev UART device struct \ref uart_pl011_dev_t 728 * 729 * \note For better performance, this function doesn't check if dev is NULL and 730 * if the driver is initialized to have better performance. 731 */ 732 void uart_pl011_enable_sirlp(struct uart_pl011_dev_t* dev); 733 734 /** 735 * \brief Disables IrDA Sir in UART dev. 736 * 737 * \param[in] dev UART device struct \ref uart_pl011_dev_t 738 * 739 * \note For better performance, this function doesn't check if dev is NULL and 740 * if the driver is initialized to have better performance. 741 */ 742 void uart_pl011_disable_sirlp(struct uart_pl011_dev_t* dev); 743 744 /** 745 * \brief Enables IrDA Sir in UART dev. 746 * 747 * \param[in] dev UART device struct \ref uart_pl011_dev_t 748 * 749 * \note For better performance, this function doesn't check if dev is NULL and 750 * if the driver is initialized to have better performance. 751 */ 752 void uart_pl011_enable_sir(struct uart_pl011_dev_t* dev); 753 754 /** 755 * \brief Disables IrDA Sir in UART dev. 756 * 757 * \param[in] dev UART device struct \ref uart_pl011_dev_t 758 * 759 * \note For better performance, this function doesn't check if dev is NULL and 760 * if the driver is initialized to have better performance. 761 */ 762 void uart_pl011_disable_sir(struct uart_pl011_dev_t* dev); 763 764 /** 765 * \brief Enables in UART PL011. 766 * 767 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 768 * 769 * 770 * \note This function doesn't check if dev is NULL. 771 */ 772 void uart_pl011_enable(struct uart_pl011_dev_t* dev); 773 774 /** 775 * \brief Disables in UART PL011. 776 * 777 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 778 * 779 * 780 * \note This function doesn't check if dev is NULL. 781 */ 782 void uart_pl011_disable(struct uart_pl011_dev_t* dev); 783 784 /** 785 * \brief Gets the Clear to send status in UART PL011. 786 * 787 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 788 * 789 * \return Returns bool, true when the modem status input is 0, false otherwise 790 * 791 * \note This bit is the complement of the UART clear to send (nUARTCTS) modem 792 * status input. 793 * \note This function doesn't check if dev is NULL. 794 */ 795 bool uart_pl011_get_cts_status(struct uart_pl011_dev_t* dev); 796 797 /** 798 * \brief Gets the Data set ready status in UART PL011. 799 * 800 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 801 * 802 * \return Returns bool, true when the modem status input is 0, false otherwise 803 * 804 * \note This bit is the complement of the UART UART data set ready (nUARTDSR) 805 * modem status input. 806 * \note This function doesn't check if dev is NULL. 807 */ 808 bool uart_pl011_get_dsr_status(struct uart_pl011_dev_t* dev); 809 810 /** 811 * \brief Gets the Data carrier detect status in UART PL011. 812 * 813 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 814 * 815 * \return Returns bool, true when the modem status input is 0, false otherwise 816 * 817 * \note This bit is the complement of the UART data carrier detect (nUARTDCD) 818 * modem status input. 819 * \note This function doesn't check if dev is NULL. 820 */ 821 bool uart_pl011_get_dcd_status(struct uart_pl011_dev_t* dev); 822 823 /** 824 * \brief Gets the Ring indicator status in UART PL011. 825 * 826 * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t 827 * 828 * \return Returns bool, true when the modem status input is 0, false otherwise 829 * 830 * \note This bit is the complement of the UART ring indicator (nUARTRI) modem 831 * status input. 832 * \note This function doesn't check if dev is NULL. 833 */ 834 bool uart_pl011_get_ri_status(struct uart_pl011_dev_t* dev); 835 836 /** 837 * \brief Sets the Low power Divisor in UART dev. 838 * 839 * \param[in] dev UART device struct \ref uart_pl011_dev_t 840 * \param[in] value Low power divisor value to be set 841 * 842 * \return Returns error code as specified in \ref uart_pl011_error_t 843 * 844 * \note For better performance, this function doesn't check if dev is NULL 845 */ 846 enum uart_pl011_error_t uart_pl011_set_sirlp_divisor( 847 struct uart_pl011_dev_t* dev, uint32_t value); 848 849 #ifdef __cplusplus 850 } 851 #endif 852 #endif /* __UART_PL011_DRV_H__ */ 853
