1 /**************************************************************************//**
2 * @file tamper.h
3 * @version V3.00
4 * @brief M2354 series TAMPER driver header file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __TAMPER_H__
10 #define __TAMPER_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup TAMPER_Driver Tamper Driver
23 @{
24 */
25
26 /** @addtogroup TAMPER_EXPORTED_CONSTANTS Tamper Exported Constants
27 @{
28 */
29
30 #define TAMPER_TAMPER0_SELECT (0x1UL << 0) /*!< Select Tamper 0 */
31 #define TAMPER_TAMPER1_SELECT (0x1UL << 1) /*!< Select Tamper 1 */
32 #define TAMPER_TAMPER2_SELECT (0x1UL << 2) /*!< Select Tamper 2 */
33 #define TAMPER_TAMPER3_SELECT (0x1UL << 3) /*!< Select Tamper 3 */
34 #define TAMPER_TAMPER4_SELECT (0x1UL << 4) /*!< Select Tamper 4 */
35 #define TAMPER_TAMPER5_SELECT (0x1UL << 5) /*!< Select Tamper 5 */
36 #define TAMPER_MAX_TAMPER_PIN_NUM 6UL /*!< Tamper Pin number */
37
38 #define TAMPER_TAMPER_HIGH_LEVEL_DETECT 1UL /*!< Tamper pin detect voltage level is high */
39 #define TAMPER_TAMPER_LOW_LEVEL_DETECT 0UL /*!< Tamper pin detect voltage level is low */
40
41 #define TAMPER_TAMPER_DEBOUNCE_ENABLE 1UL /*!< Enable tamper pin de-bounce function */
42 #define TAMPER_TAMPER_DEBOUNCE_DISABLE 0UL /*!< Disable tamper pin de-bounce function */
43
44 #define TAMPER_PAIR0_SELECT (0x1UL << 0) /*!< Select Pair 0 */
45 #define TAMPER_PAIR1_SELECT (0x1UL << 1) /*!< Select Pair 1 */
46 #define TAMPER_PAIR2_SELECT (0x1UL << 2) /*!< Select Pair 2 */
47 #define TAMPER_MAX_PAIR_NUM 3UL /*!< Pair number */
48
49 #define TAMPER_2POW6_CLK (0x0UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 RTC clock cycles */
50 #define TAMPER_2POW7_CLK (0x1UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 2 RTC clock cycles */
51 #define TAMPER_2POW8_CLK (0x2UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 4 RTC clock cycles */
52 #define TAMPER_2POW9_CLK (0x3UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 6 RTC clock cycles */
53 #define TAMPER_2POW10_CLK (0x4UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 8 RTC clock cycles */
54 #define TAMPER_2POW11_CLK (0x5UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 10 RTC clock cycles */
55 #define TAMPER_2POW12_CLK (0x6UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 12 RTC clock cycles */
56 #define TAMPER_2POW13_CLK (0x7UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 14 RTC clock cycles */
57
58 #define TAMPER_ACTS_2POW10_CLK (0x0UL << 5) /*!< 1024 LIRC32K clock cycles */
59 #define TAMPER_ACTS_2POW11_CLK (0x1UL << 5) /*!< 1024 x 2 LIRC32K clock cycles */
60 #define TAMPER_ACTS_2POW12_CLK (0x2UL << 5) /*!< 1024 x 4 LIRC32K clock cycles */
61 #define TAMPER_ACTS_2POW13_CLK (0x3UL << 5) /*!< 1024 x 6 LIRC32K clock cycles */
62 #define TAMPER_ACTS_2POW14_CLK (0x4UL << 5) /*!< 1024 x 8 LIRC32K clock cycles */
63 #define TAMPER_ACTS_2POW15_CLK (0x5UL << 5) /*!< 1024 x 16 LIRC32K clock cycles */
64 #define TAMPER_ACTS_2POW16_CLK (0x6UL << 5) /*!< 1024 x 32 LIRC32K clock cycles */
65 #define TAMPER_ACTS_2POW17_CLK (0x7UL << 5) /*!< 1024 x 64 LIRC32K clock cycles */
66
67 #define TAMPER_REF_RANDOM_PATTERN 0x0UL /*!< The new reference pattern is generated by random number generator when the reference pattern run out */
68 #define TAMPER_REF_SEED 0x1UL /*!< The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out */
69
70 #define TAMPER_VG_192M_SAMPLE 0x0UL /*!< Select voltage glitch 192M sampleing rate */
71 #define TAMPER_VG_96M_SAMPLE 0x1UL /*!< Select voltage glitch 96M sampleing rate */
72 #define TAMPER_VG_48M_SAMPLE 0x2UL /*!< Select voltage glitch 48M sampleing rate */
73
74 #define TAMPER_LBSTRIM_TLVDSEL_1_25V 0x0UL /*!< Select the trim value of the under-shoot detection level as 1.25V */
75 #define TAMPER_LBSTRIM_TLVDSEL_1_20V 0x1UL /*!< Select the trim value of the under-shoot detection level as 1.2V */
76 #define TAMPER_LBSTRIM_TLVDSEL_1_15V 0x2UL /*!< Select the trim value of the under-shoot detection level as 1.15V */
77 #define TAMPER_LBSTRIM_TLVDSEL_1_10V 0x3UL /*!< Select the trim value of the under-shoot detection level as 1.1V */
78 #define TAMPER_LBSTRIM_TLVDSEL_1_05V 0x4UL /*!< Select the trim value of the under-shoot detection level as 1.05V */
79 #define TAMPER_LBSTRIM_TLVDSEL_1_00V 0x5UL /*!< Select the trim value of the under-shoot detection level as 1.0V */
80 #define TAMPER_LBSTRIM_TLVDSEL_0_95V 0x6UL /*!< Select the trim value of the under-shoot detection level as 0.95V */
81 #define TAMPER_LBSTRIM_TLVDSEL_0_90V 0x7UL /*!< Select the trim value of the under-shoot detection level as 0.9V */
82
83 #define TAMPER_LBSTRIM_TOVDSEL_1_35V 0x0UL /*!< Select the trim value of the over-shoot detection level as 1.35V */
84 #define TAMPER_LBSTRIM_TOVDSEL_1_40V 0x1UL /*!< Select the trim value of the over-shoot detection level as 1.4V */
85
86 /**@}*/ /* end of group TAMPER_EXPORTED_CONSTANTS */
87
88
89 /** @addtogroup TAMPER_EXPORTED_FUNCTIONS Tamper Exported Functions
90 @{
91 */
92
93 /**
94 * @brief Reset Tamper Coreblock
95 *
96 * @details To set TAMPER INIT control register to reset the tamper coreblock.
97 *
98 */
99 #define TAMPER_CORE_RESET() ((uint32_t)(TAMPER->INIT = 0x55AA))
100
101 /**
102 * @brief Release Tamper Coreblock
103 *
104 * @details To set TAMPER INIT control register to release the tamper coreblock.
105 *
106 */
107 #define TAMPER_CORE_RELEASE() ((uint32_t)(TAMPER->INIT = 0x5500))
108
109 /**
110 * @brief Get the Voltage Regulator Power Ready Status
111 *
112 * @retval 0 The power status of voltage regulator is not ready.
113 * @retval 1 The power status of voltage regulator is ready.
114 *
115 * @details This macro will return the power status of voltage regulator.
116 *
117 */
118 #define TAMPER_TLDO_IS_READY() (TAMPER->INIT & TAMPER_INIT_TLDORDY_Msk ? 1:0)
119
120 /**
121 * @brief Enable LXT Clock Detection
122 *
123 * @details To set TAMPER FUNEN control register to enable LXT clock detection.
124 *
125 */
126 #define TAMPER_ENABLE_LXTDET() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x44))
127
128 /**
129 * @brief Disable LXT Clock Detection
130 *
131 * @details To set TAMPER FUNEN control register to disable LXT clock detection.
132 *
133 */
134 #define TAMPER_DISABLE_LXTDET() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x40))
135
136 /**
137 * @brief Tamper I/O TAMPER Block Detection Selection
138 *
139 * @param[in] u32TamperSelect Tamper pin select. Possible options are
140 * - \ref TAMPER_TAMPER0_SELECT
141 * - \ref TAMPER_TAMPER1_SELECT
142 * - \ref TAMPER_TAMPER2_SELECT
143 * - \ref TAMPER_TAMPER3_SELECT
144 * - \ref TAMPER_TAMPER4_SELECT
145 * - \ref TAMPER_TAMPER5_SELECT
146 *
147 * @details To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through TAMPER block.
148 *
149 */
TAMPER_IOSEL_TAMPER(uint32_t u32TamperSelect)150 __STATIC_INLINE void TAMPER_IOSEL_TAMPER(uint32_t u32TamperSelect)
151 {
152 uint32_t i;
153
154 for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++)
155 {
156 if(u32TamperSelect & (0x1UL << i))
157 {
158 TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x94 + i * 0x10UL);
159 }
160 }
161 }
162
163 /**
164 * @brief Tamper I/O RTC Block Detection Selection
165 *
166 * @param[in] u32TamperSelect Tamper pin select. Possible options are
167 * - \ref TAMPER_TAMPER0_SELECT
168 * - \ref TAMPER_TAMPER1_SELECT
169 * - \ref TAMPER_TAMPER2_SELECT
170 * - \ref TAMPER_TAMPER3_SELECT
171 * - \ref TAMPER_TAMPER4_SELECT
172 * - \ref TAMPER_TAMPER5_SELECT
173 *
174 * @details To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through RTC block.
175 *
176 */
TAMPER_IOSEL_RTC(uint32_t u32TamperSelect)177 __STATIC_INLINE void TAMPER_IOSEL_RTC(uint32_t u32TamperSelect)
178 {
179 uint32_t i;
180
181 for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++)
182 {
183 if(u32TamperSelect & (0x1UL << i))
184 {
185 TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x90 + i * 0x10UL);
186 }
187 }
188 }
189
190 /**
191 * @brief Enable HIRC48M
192 *
193 * @details To set TAMPER FUNEN control register to enable HIRC48M.
194 *
195 */
196 #define TAMPER_ENABLE_HIRC48M() ((uint32_t)(TAMPER->FUNEN &= (~TAMPER_FUNEN_HIRC48MEN_Msk)))
197
198 /**
199 * @brief Disable HIRC48M
200 *
201 * @details To set TAMPER FUNEN control register to disable HIRC48M.
202 *
203 */
204 #define TAMPER_DISABLE_HIRC48M() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & (~TAMPER_FUNEN_HIRC48MEN_Msk)) | (0x5A << TAMPER_FUNEN_HIRC48MEN_Pos)))
205
206 /**
207 * @brief Voltage Glitch Sampling Rate Selection
208 *
209 * @param[in] u32VGSampleRate Voltage glitch sampling rate select. Possible options are
210 * - \ref TAMPER_VG_192M_SAMPLE
211 * - \ref TAMPER_VG_96M_SAMPLE
212 * - \ref TAMPER_VG_48M_SAMPLE
213 *
214 * @details To set TAMPER FUNEN control register to enable voltage glitch channel 0~3 to select voltage glitch sampling rate.
215 *
216 */
TAMPER_VG_SAMPLE_SEL(uint32_t u32VGSampleRate)217 __STATIC_INLINE void TAMPER_VG_SAMPLE_SEL(uint32_t u32VGSampleRate)
218 {
219 TAMPER->FUNEN &= ~0xF000000UL;
220
221 if(u32VGSampleRate == TAMPER_VG_192M_SAMPLE)
222 {
223 TAMPER->FUNEN |= TAMPER_FUNEN_VGCHEN0_Msk | TAMPER_FUNEN_VGCHEN1_Msk | TAMPER_FUNEN_VGCHEN2_Msk | TAMPER_FUNEN_VGCHEN3_Msk;
224 }
225 else if(u32VGSampleRate == TAMPER_VG_96M_SAMPLE)
226 {
227 TAMPER->FUNEN |= TAMPER_FUNEN_VGCHEN0_Msk | TAMPER_FUNEN_VGCHEN1_Msk;
228 }
229 else if(u32VGSampleRate == TAMPER_VG_48M_SAMPLE)
230 {
231 TAMPER->FUNEN |= TAMPER_FUNEN_VGCHEN0_Msk;
232 }
233 }
234
235 /**
236 * @brief Voltage Glitch Reference Trim Value Initialization
237 *
238 * @details To set TAMPER VG or VG2 control register to initialize a reference trim value that provides voltage glitch detection
239 * error tolerance within 15%.
240 *
241 */
TAMPER_VG_TRIM_INIT()242 __STATIC_INLINE void TAMPER_VG_TRIM_INIT()
243 {
244 if(SYS->PLSTS & SYS_PLSTS_PLSTATUS_PL0)
245 {
246 TAMPER->VG = (TAMPER->VG & ~0xFFFFUL) | 0x8CC8UL;
247 }
248 else if(SYS->PLSTS & SYS_PLSTS_PLSTATUS_PL1)
249 {
250 TAMPER->VG = (TAMPER->VG & ~0xFFFF0000UL) | 0x7CC90000UL;
251 }
252 else if(SYS->PLSTS & SYS_PLSTS_PLSTATUS_PL2)
253 {
254 TAMPER->VG2 = (TAMPER->VG2 & ~0xFFFFUL) | 0x5CCBUL;
255 }
256 else if(SYS->PLSTS & SYS_PLSTS_PLSTATUS_PL3)
257 {
258 TAMPER->VG2 = (TAMPER->VG2 & ~0xFFFF0000UL) | 0x2CCD0000UL;
259 }
260 }
261
262 /**
263 * @brief Under-shoot Detection Level Trim Value Initialization
264 *
265 * @param[in] u32TLVDTrim Under-shoot detect level trim value select. Possible options are
266 * - \ref TAMPER_LBSTRIM_TLVDSEL_1_25V
267 * - \ref TAMPER_LBSTRIM_TLVDSEL_1_20V
268 * - \ref TAMPER_LBSTRIM_TLVDSEL_1_15V
269 * - \ref TAMPER_LBSTRIM_TLVDSEL_1_10V
270 * - \ref TAMPER_LBSTRIM_TLVDSEL_1_05V
271 * - \ref TAMPER_LBSTRIM_TLVDSEL_1_00V
272 * - \ref TAMPER_LBSTRIM_TLVDSEL_0_95V
273 * - \ref TAMPER_LBSTRIM_TLVDSEL_0_90V
274 *
275 * @details To set TAMPER LBSTRIM control register to select under-shoot detection level trim value.
276 *
277 */
278 #define TAMPER_TLVD_TRIM_INIT(u32TLVDTrim) ((uint32_t)(TAMPER->LBSTRIM = (TAMPER->LBSTRIM & (~TAMPER_LBSTRIM_TLVDSEL_Msk)) | (u32TLVDTrim << TAMPER_LBSTRIM_TLVDSEL_Pos)))
279
280 /**
281 * @brief Over-shoot Detection Level Trim Value Initialization
282 *
283 * @param[in] u32TOVDTrim Over-shoot detect level trim value select. Possible options are
284 * - \ref TAMPER_LBSTRIM_TOVDSEL_1_35V
285 * - \ref TAMPER_LBSTRIM_TOVDSEL_1_40V
286 *
287 * @details To set TAMPER LBSTRIM control register to select over-shoot detection level trim value.
288 *
289 */
290 #define TAMPER_TOVD_TRIM_INIT(u32TOVDTrim) ((uint32_t)(TAMPER->LBSTRIM = (TAMPER->LBSTRIM & (~TAMPER_LBSTRIM_TOVDSEL_Msk)) | (u32TOVDTrim << TAMPER_LBSTRIM_TOVDSEL_Pos)))
291
292 /**
293 * @brief Enable to Trigger Key Store
294 *
295 * @details Set KSTRIGEN bit of TAMPER TRIEN control register to trigger Key Store when Tamper event is detected.
296 *
297 */
298 #define TAMPER_ENABLE_KS_TRIG() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_KSTRIGEN_Msk))
299
300 /**
301 * @brief Disable to Trigger Key Store
302 *
303 * @details Clear KSTRIGEN bit of TAMPER TRIEN control register to not trigger Key Store when Tamper event is detected.
304 *
305 */
306 #define TAMPER_DISABLE_KS_TRIG() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_KSTRIGEN_Msk)))
307
308 /**
309 * @brief Enable Wake-up Function
310 *
311 * @details Set WAKEUPEN bit of TAMPER TRIEN control register to wake-up the system when Tamper event is detected.
312 *
313 */
314 #define TAMPER_ENABLE_WAKEUP() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_WAKEUPEN_Msk))
315
316 /**
317 * @brief Disable Wake-up Function
318 *
319 * @details Clear WAKEUPEN bit of TAMPER TRIEN control register to not wake-up the system when Tamper event is detected.
320 *
321 */
322 #define TAMPER_DISABLE_WAKEUP() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_WAKEUPEN_Msk)))
323
324 /**
325 * @brief Enable to Clear Crypto Function
326 *
327 * @details Set CRYPTOEN bit of TAMPER TRIEN control register to reset Crypto when Tamper event is detected.
328 *
329 */
330 #define TAMPER_ENABLE_CRYPTO() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CRYPTOEN_Msk))
331
332 /**
333 * @brief Disable to Clear Crypto Function
334 *
335 * @details Clear CRYPTOEN bit of TAMPER TRIEN control register to not reset Crypto when Tamper event is detected.
336 *
337 */
338 #define TAMPER_DISABLE_CRYPTO() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CRYPTOEN_Msk)))
339
340 /**
341 * @brief Enable to Trigger Chip Reset
342 *
343 * @details Set CHIPRSTEN bit of TAMPER TRIEN control register to reset the system when Tamper event is detected.
344 *
345 */
346 #define TAMPER_ENABLE_CHIPRST() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CHIPRSTEN_Msk))
347
348 /**
349 * @brief Disable to Trigger Chip Reset
350 *
351 * @details Clear CHIPRSTEN bit of TAMPER TRIEN control register to not reset the system when Tamper event is detected.
352 *
353 */
354 #define TAMPER_DISABLE_CHIPRST() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CHIPRSTEN_Msk)))
355
356 /**
357 * @brief Enable to Clear RTC Spare Register
358 *
359 * @details Set RTCSPCLREN bit of TAMPER TRIEN control register to reset RTC spare register when Tamper event is detected.
360 *
361 */
362 #define TAMPER_ENABLE_RTCSPCLR() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_RTCSPCLREN_Msk))
363
364 /**
365 * @brief Disable to Clear RTC Spare Register
366 *
367 * @details Clear RTCSPCLREN bit of TAMPER TRIEN control register to not reset RTC spare register when Tamper event is detected.
368 *
369 */
370 #define TAMPER_DISABLE_RTCSPCLR() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_RTCSPCLREN_Msk)))
371
372 /**
373 * @brief Get Tamper Interrupt Flag
374 *
375 * @retval 0 Tamper event Interrupt did not occur
376 * @retval 1 Tamper event Interrupt occurred
377 *
378 * @details This macro indicates Tamper event intertupt occurred or not.
379 *
380 */
381 #define TAMPER_GET_INT_FLAG() ((TAMPER->INTSTS & (0xAA77AFFF))? 1:0)
382
383 /**
384 * @brief Clear Tamper Interrupt Status
385 *
386 * @param[in] u32TamperFlag Tamper event interrupt flag. It consists of:
387 * - \ref TAMPER_INTSTS_TAMP0IF_Msk
388 * - \ref TAMPER_INTSTS_TAMP1IF_Msk
389 * - \ref TAMPER_INTSTS_TAMP2IF_Msk
390 * - \ref TAMPER_INTSTS_TAMP3IF_Msk
391 * - \ref TAMPER_INTSTS_TAMP4IF_Msk
392 * - \ref TAMPER_INTSTS_TAMP5IF_Msk
393 * - \ref TAMPER_INTSTS_CLKFAILIF_Msk
394 * - \ref TAMPER_INTSTS_CLKSTOPIF_Msk
395 * - \ref TAMPER_INTSTS_OVPOUTIF_Msk
396 * - \ref TAMPER_INTSTS_VGPEVIF_Msk
397 * - \ref TAMPER_INTSTS_VGNEVIF_Msk
398 * - \ref TAMPER_INTSTS_ACTSEIF_Msk
399 * - \ref TAMPER_INTSTS_ACTST5IF_Msk
400 * - \ref TAMPER_INTSTS_ACTST25IF_Msk
401 * - \ref TAMPER_INTSTS_VBATLOSSIF_Msk
402 * - \ref TAMPER_INTSTS_SECWDTIF_Msk
403 * - \ref TAMPER_INTSTS_BODIF_Msk
404 * - \ref TAMPER_INTSTS_ACTST1IF_Msk
405 * - \ref TAMPER_INTSTS_ACTST3IF_Msk
406 * - \ref TAMPER_INTSTS_ACTST21IF_Msk
407 * - \ref TAMPER_INTSTS_ACTST23IF_Msk
408 *
409 * @details This macro is used to clear Tamper event flag.
410 *
411 */
412 #define TAMPER_CLR_INT_STATUS(u32TamperFlag) (TAMPER->INTSTS = (u32TamperFlag))
413
414 /**
415 * @brief Get Tamper Interrupt Status
416 *
417 * @retval TAMPER_INTSTS_TAMP0IF_Msk
418 * @retval TAMPER_INTSTS_TAMP1IF_Msk
419 * @retval TAMPER_INTSTS_TAMP2IF_Msk
420 * @retval TAMPER_INTSTS_TAMP3IF_Msk
421 * @retval TAMPER_INTSTS_TAMP4IF_Msk
422 * @retval TAMPER_INTSTS_TAMP5IF_Msk
423 * @retval TAMPER_INTSTS_CLKFAILIF_Msk
424 * @retval TAMPER_INTSTS_CLKSTOPIF_Msk
425 * @retval TAMPER_INTSTS_OVPOUTIF_Msk
426 * @retval TAMPER_INTSTS_VGPEVIF_Msk
427 * @retval TAMPER_INTSTS_VGNEVIF_Msk
428 * @retval TAMPER_INTSTS_ACTSEFIF_Msk
429 * @retval TAMPER_INTSTS_ACTST5IF_Msk
430 * @retval TAMPER_INTSTS_ACTST25IF_Msk
431 * @retval TAMPER_INTSTS_RTCLVRIF_Msk
432 * @retval TAMPER_INTSTS_RIOTRIGIF_Msk
433 * @retval TAMPER_INTSTS_RCLKTRIGIF_Msk
434 * @retval TAMPER_INTSTS_VBATLOSSIF_Msk
435 * @retval TAMPER_INTSTS_SECWDTIF_Msk
436 * @retval TAMPER_INTSTS_BODIF_Msk
437 * @retval TAMPER_INTSTS_ACTST1IF_Msk
438 * @retval TAMPER_INTSTS_ACTST3IF_Msk
439 * @retval TAMPER_INTSTS_ACTST21IF_Msk
440 * @retval TAMPER_INTSTS_ACTST23IF_Msk
441 *
442 * @details This macro indicates Tamper event status.
443 *
444 */
445 #define TAMPER_GET_INT_STATUS() ((TAMPER->INTSTS & (0xAA77AFFF)))
446
447 void TAMPER_EnableInt(uint32_t u32IntFlagMask);
448 void TAMPER_DisableInt(uint32_t u32IntFlagMask);
449 void TAMPER_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
450 void TAMPER_StaticTamperDisable(uint32_t u32TamperSelect);
451 void TAMPER_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
452 void TAMPER_DynamicTamperDisable(uint32_t u32PairSel);
453 void TAMPER_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
454 void TAMPER_ActiveShieldDynamicTamperEnable(uint32_t u32PairSel1, uint32_t u32Pair1Source1, uint32_t u32PairSel2, uint32_t u32Pair1Source2);
455 void TAMPER_ActiveShieldDynamicTamperDisable(uint32_t u32PairSel1, uint32_t u32PairSe2);
456 void TAMPER_ActiveShieldDynamicTamperConfig(uint32_t u32ChangeRate1, uint32_t u32SeedReload1, uint32_t u32RefPattern1, uint32_t u32Seed,
457 uint32_t u32ChangeRate2, uint32_t u32SeedReload2, uint32_t u32RefPattern2, uint32_t u32Seed2);
458
459
460 /**@}*/ /* end of group TAMPER_EXPORTED_FUNCTIONS */
461
462 /**@}*/ /* end of group TAMPER_Driver */
463
464 /**@}*/ /* end of group Standard_Driver */
465
466 #ifdef __cplusplus
467 }
468 #endif
469
470 #endif /* __TAMPER_H__ */
471
472
