1 /* 2 * Copyright (c) 2017-2020 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __MUSCA_B1_DEVICE_CFG_H__ 18 #define __MUSCA_B1_DEVICE_CFG_H__ 19 20 /** 21 * \file device_cfg.h 22 * \brief Configuration file native driver re-targeting 23 * 24 * \details This file can be used to add native driver specific macro 25 * definitions to select which peripherals are available in the build. 26 * 27 * This is a default device configuration file with all peripherals enabled. 28 */ 29 30 /* ARM SCC */ 31 #define MUSCA_B1_SCC_S 32 33 /* CMSDK GPIO */ 34 #define GPIO0_CMSDK_S 35 36 /* ARM Memory Protection Controller (MPC) SIE 200 */ 37 #define MPC_ISRAM0_S 38 #define MPC_ISRAM1_S 39 #define MPC_ISRAM2_S 40 #define MPC_ISRAM3_S 41 #define MPC_CODE_SRAM_S 42 #define MPC_QSPI_S 43 #define MPC_EFLASH0_S 44 #define MPC_EFLASH1_S 45 46 /* ARM Peripheral Protection Controllers (PPC) */ 47 #define AHB_PPC0_S 48 #define AHB_PPCEXP0_S 49 #define AHB_PPCEXP1_S 50 #define AHB_PPCEXP2_S 51 #define AHB_PPCEXP3_S 52 53 #define APB_PPC0_S 54 #define APB_PPC1_S 55 #define APB_PPCEXP0_S 56 #define APB_PPCEXP1_S 57 #define APB_PPCEXP2_S 58 #define APB_PPCEXP3_S 59 60 /*ARM UART Controller PL011*/ 61 #define UART0_PL011_S 62 #define UART0_PL011_NS 63 #define UART1_PL011_S 64 #define UART1_PL011_NS 65 66 /* CMSDK Timers */ 67 #define CMSDK_TIMER0_S 68 #define CMSDK_TIMER0_NS 69 #define CMSDK_TIMER1_S 70 #define CMSDK_TIMER1_NS 71 72 /* GFC-100 EFlash controller */ 73 #define GFC100_EFLASH0_S 74 75 /* Cadence QSPI Flash Controller */ 76 #define QSPI_IP6514E_S 77 #define QSPI_IP6514E_NS 78 79 /* MT25QL Flash memory library */ 80 #define MT25QL_S 81 #define MT25QL_NS 82 83 #ifdef USE_SECURE_ENCLAVE_MAILBOX 84 /* SE MHU */ 85 #define SE_MHU_SENDER_S 86 #define SE_MHU_SENDER_DEV SE_MHU_SENDER_DEV_S 87 #define SE_MHU_RECEIVER_S 88 #define SE_MHU_RECEIVER_DEV SE_MHU_RECEIVER_DEV_S 89 #endif 90 91 #define DEFAULT_UART_CONTROL 0 92 /* Default UART baud rate */ 93 #define DEFAULT_UART_BAUDRATE 115200 94 95 #endif /* __MUSCA_B1_DEVICE_CFG_H__ */ 96
