1 /**************************************************************************//** 2 * @file sc_reg.h 3 * @version V1.00 4 * @brief SC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SC_REG_H__ 10 #define __SC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Smart Card Host Interface Controller -------------------------*/ 19 /** 20 @addtogroup SC Smart Card Host Interface Controller(SC) 21 Memory Mapped Structure for SC Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var SC_T::DAT 31 * Offset: 0x00 SC Receive/Transmit Holding Buffer Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[7:0] |DAT |Receive/Transmit Holding Buffer 36 * | | |Write Operation: 37 * | | |By writing data to DAT, the SC will send out an 8-bit data. 38 * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. 39 * | | |Read Operation: 40 * | | |By reading DAT, the SC will return an 8-bit received data. 41 * @var SC_T::CTL 42 * Offset: 0x04 SC Control Register 43 * --------------------------------------------------------------------------------------------------- 44 * |Bits |Field |Descriptions 45 * | :----: | :----: | :---- | 46 * |[0] |SCEN |SC Controller Enable Bit 47 * | | |Set this bit to 1 to enable SC operation. 48 * | | |0 = SC will force all transition to IDLE state. 49 * | | |1 = SC controller is enabled and all function can work correctly. 50 * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. 51 * |[1] |RXOFF |RX Transition Disable Control Bit 52 * | | |This bit is used for disable Rx transition function. 53 * | | |0 = The receiver Enabled. 54 * | | |1 = The receiver Disabled. 55 * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 56 * |[2] |TXOFF |TX Transition Disable Control Bit 57 * | | |This bit is used for disable Tx transition function. 58 * | | |0 = The transceiver Enabled. 59 * | | |1 = The transceiver Disabled. 60 * |[3] |AUTOCEN |Auto Convention Enable Bit 61 * | | |This bit is used for enable auto convention function. 62 * | | |0 = Auto-convention Disabled. 63 * | | |1 = Auto-convention Enabled. 64 * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F 65 * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F 66 * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. 67 * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. 68 * |[5:4] |CONSEL |Convention Selection 69 * | | |00 = Direct convention. 70 * | | |01 = Reserved. 71 * | | |10 = Reserved. 72 * | | |11 = Inverse convention. 73 * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 74 * |[7:6] |RXTRGLV |Rx Buffer Trigger Level 75 * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set 76 * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. 77 * | | |00 = Rx Buffer Trigger Level with 01 bytes. 78 * | | |01 = Rx Buffer Trigger Level with 02 bytes. 79 * | | |10 = Rx Buffer Trigger Level with 03 bytes. 80 * | | |11 = Reserved. 81 * |[12:8] |BGT |Block Guard Time (BGT) 82 * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions 83 * | | |This field indicates the counter for the bit length of block guard time 84 * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. 85 * | | |Note: The real block guard time is BGT + 1. 86 * |[14:13] |TMRSEL |Timer Channel Selection 87 * | | |00 = All internal timer function Disabled. 88 * | | |. 89 * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled 90 * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. 91 * | | |Other configurations are reserve 92 * |[15] |NSB |Stop Bit Length 93 * | | |This field indicates the length of stop bit. 94 * | | |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode). 95 * | | |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode). 96 * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. 97 * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. 98 * |[18:16] |RXRTY |RX Error Retry Count Number 99 * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred 100 * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. 101 * | | |Note2: This field cannot be changed when RXRTYEN enabled 102 * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. 103 * |[19] |RXRTYEN |RX Error Retry Enable Bit 104 * | | |This bit enables receiver retry function when parity error has occurred. 105 * | | |0 = RX error retry function Disabled. 106 * | | |1 = RX error retry function Enabled. 107 * | | |Note: User must fill in the RXRTY value before enabling this bit. 108 * |[22:20] |TXRTY |TX Error Retry Count Number 109 * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. 110 * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. 111 * | | |Note2: This field cannot be changed when TXRTYEN enabled 112 * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. 113 * |[23] |TXRTYEN |TX Error Retry Enable Bit 114 * | | |This bit enables transmitter retry function when parity error has occurred. 115 * | | |0 = TX error retry function Disabled. 116 * | | |1 = TX error retry function Enabled. 117 * |[25:24] |CDDBSEL |Card Detect De-bounce Selection 118 * | | |This field indicates the card detect de-bounce selection. 119 * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks. 120 * | | |Other configurations are reserved. 121 * |[26] |CDLV |Card Detect Level Selection 122 * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. 123 * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. 124 * | | |Note: User must select card detect level before Smart Card controller enabled. 125 * |[30] |SYNC |SYNC Flag Indicator (Read Only) 126 * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 127 * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. 128 * | | |1 = Last value is synchronizing. 129 * @var SC_T::ALTCTL 130 * Offset: 0x08 SC Alternate Control Register 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[0] |TXRST |TX Software Reset 135 * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. 136 * | | |0 = No effect. 137 * | | |1 = Reset the TX internal state machine and pointers. 138 * | | |Note: This bit will be auto cleared after reset is complete. 139 * |[1] |RXRST |Rx Software Reset 140 * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. 141 * | | |0 = No effect. 142 * | | |1 = Reset the Rx internal state machine and pointers. 143 * | | |Note: This bit will be auto cleared after reset is complete. 144 * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit 145 * | | |This bit enables SC controller to initiate the card by deactivation sequence. 146 * | | |0 = No effect. 147 * | | |1 = Deactivation sequence generator Enabled. 148 * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. 149 * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) 150 * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. 151 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 152 * |[3] |ACTEN |Activation Sequence Generator Enable Bit 153 * | | |This bit enables SC controller to initiate the card by activation sequence. 154 * | | |0 = No effect. 155 * | | |1 = Activation sequence generator Enabled. 156 * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. 157 * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) 158 * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. 159 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 160 * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data 161 * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. 162 * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit 163 * | | |This bit enables SC controller to initiate the card by warm reset sequence. 164 * | | |0 = No effect. 165 * | | |1 = Warm reset sequence generator Enabled. 166 * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. 167 * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) 168 * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. 169 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 170 * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data 171 * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. 172 * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit 173 * | | |This bit enables Timer 0 to start counting 174 * | | |User can fill 0 to stop it and set 1 to reload and count 175 * | | |The counter unit is ETU base. 176 * | | |0 = Stops counting. 177 * | | |1 = Start counting. 178 * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. 179 * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. 180 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed 181 * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit 182 * | | |This bit enables Timer 1 to start counting 183 * | | |User can fill 0 to stop it and set 1 to reload and count 184 * | | |The counter unit is ETU base. 185 * | | |0 = Stops counting. 186 * | | |1 = Start counting. 187 * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only 188 * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. 189 * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. 190 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 191 * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit 192 * | | |This bit enables Timer 2 to start counting 193 * | | |User can fill 0 to stop it and set 1 to reload and count 194 * | | |The counter unit is ETU base. 195 * | | |0 = Stops counting. 196 * | | |1 = Start counting. 197 * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only 198 * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. 199 * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. 200 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 201 * |[9:8] |INITSEL |Initial Timing Selection 202 * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. 203 * | | |The unit of initial timing is SC module clock. 204 * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence. 205 * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence. 206 * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence. 207 * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. 208 * |[11] |ADACEN |Auto Deactivation When Card Removal 209 * | | |This bit is used for enable hardware auto deactivation when smart card is removed. 210 * | | |0 = Auto deactivation Disabled. 211 * | | |1 = Auto deactivation Enabled. 212 * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set 213 * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. 214 * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit 215 * | | |This bit enables the receiver block guard time function. 216 * | | |0 = Receiver block guard time function Disabled. 217 * | | |1 = Receiver block guard time function Enabled. 218 * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) 219 * | | |This bit indicates the timer counter status of timer0. 220 * | | |0 = Timer0 is not active. 221 * | | |1 = Timer0 is active. 222 * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). 223 * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) 224 * | | |This bit indicates the timer counter status of timer1. 225 * | | |0 = Timer1 is not active. 226 * | | |1 = Timer1 is active. 227 * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). 228 * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) 229 * | | |This bit indicates the timer counter status of timer2. 230 * | | |0 = Timer2 is not active. 231 * | | |1 = Timer2 is active. 232 * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). 233 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 234 * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. 235 * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. 236 * | | |1 = Last value is synchronizing. 237 * @var SC_T::EGT 238 * Offset: 0x0C SC Extra Guard Time Register 239 * --------------------------------------------------------------------------------------------------- 240 * |Bits |Field |Descriptions 241 * | :----: | :----: | :---- | 242 * |[7:0] |EGT |Extra Guard Time 243 * | | |This field indicates the extra guard time value. 244 * | | |Note: The extra guard time unit is ETU base. 245 * @var SC_T::RXTOUT 246 * Offset: 0x10 SC Receive Buffer Time-out Counter Register 247 * --------------------------------------------------------------------------------------------------- 248 * |Bits |Field |Descriptions 249 * | :----: | :----: | :---- | 250 * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter 251 * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data 252 * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled. 253 * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. 254 * | | |Note2: Filling in all 0 to this field indicates to disable this function. 255 * @var SC_T::ETUCTL 256 * Offset: 0x14 SC Element Time Unit Control Register 257 * --------------------------------------------------------------------------------------------------- 258 * |Bits |Field |Descriptions 259 * | :----: | :----: | :---- | 260 * |[11:0] |ETURDIV |ETU Rate Divider 261 * | | |The field is used for ETU clock rate divider. 262 * | | |The real ETU is ETURDIV + 1. 263 * | | |Note: User can configure this field, but this field must be greater than 0x04. 264 * @var SC_T::INTEN 265 * Offset: 0x18 SC Interrupt Enable Control Register 266 * --------------------------------------------------------------------------------------------------- 267 * |Bits |Field |Descriptions 268 * | :----: | :----: | :---- | 269 * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit 270 * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. 271 * | | |0 = Receive data reach trigger level interrupt Disabled. 272 * | | |1 = Receive data reach trigger level interrupt Enabled. 273 * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit 274 * | | |This field is used to enable transmit buffer empty interrupt. 275 * | | |0 = Transmit buffer empty interrupt Disabled. 276 * | | |1 = Transmit buffer empty interrupt Enabled. 277 * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit 278 * | | |This field is used to enable transfer error interrupt 279 * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). 280 * | | |0 = Transfer error interrupt Disabled. 281 * | | |1 = Transfer error interrupt Enabled. 282 * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit 283 * | | |This field is used to enable Timer0 interrupt function. 284 * | | |0 = Timer0 interrupt Disabled. 285 * | | |1 = Timer0 interrupt Enabled. 286 * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit 287 * | | |This field is used to enable the Timer1 interrupt function. 288 * | | |0 = Timer1 interrupt Disabled. 289 * | | |1 = Timer1 interrupt Enabled. 290 * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit 291 * | | |This field is used to enable Timer2 interrupt function. 292 * | | |0 = Timer2 interrupt Disabled. 293 * | | |1 = Timer2 interrupt Enabled. 294 * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit 295 * | | |This field is used to enable block guard time interrupt in receive direction. 296 * | | |0 = Block guard time interrupt Disabled. 297 * | | |1 = Block guard time interrupt Enabled. 298 * | | |Note: This bit is valid only for receive receive direction block guard time. 299 * |[7] |CDIEN |Card Detect Interrupt Enable Bit 300 * | | |This field is used to enable card detect interrupt 301 * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). 302 * | | |0 = Card detect interrupt Disabled. 303 * | | |1 = Card detect interrupt Enabled. 304 * |[8] |INITIEN |Initial End Interrupt Enable Bit 305 * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. 306 * | | |0 = Initial end interrupt Disabled. 307 * | | |1 = Initial end interrupt Enabled. 308 * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit 309 * | | |This field is used to enable receiver buffer time-out interrupt. 310 * | | |0 = Receiver buffer time-out interrupt Disabled. 311 * | | |1 = Receiver buffer time-out interrupt Enabled. 312 * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit 313 * | | |This field is used to enable auto-convention error interrupt. 314 * | | |0 = Auto-convention error interrupt Disabled. 315 * | | |1 = Auto-convention error interrupt Enabled. 316 * @var SC_T::INTSTS 317 * Offset: 0x1C SC Interrupt Status Register 318 * --------------------------------------------------------------------------------------------------- 319 * |Bits |Field |Descriptions 320 * | :----: | :----: | :---- | 321 * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) 322 * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. 323 * | | |0 = Number of receive buffer is less than RXTRGLV setting. 324 * | | |1 = Number of receive buffer data equals the RXTRGLV setting. 325 * | | |Note: This bit is read only 326 * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. 327 * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) 328 * | | |This field is used for transmit buffer empty interrupt status flag. 329 * | | |0 = Transmit buffer is not empty. 330 * | | |1 = Transmit buffer is empty. 331 * | | |Note: This bit is read only 332 * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. 333 * |[2] |TERRIF |Transfer Error Interrupt Status Flag 334 * | | |This field is used for transfer error interrupt status flag 335 * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]). 336 * | | |0 = Transfer error interrupt did not occur. 337 * | | |1 = Transfer error interrupt occurred. 338 * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. 339 * | | |Note2: This bit can be cleared by writing 1 to it. 340 * |[3] |TMR0IF |Timer0 Interrupt Status Flag 341 * | | |This field is used for Timer0 interrupt status flag. 342 * | | |0 = Timer0 interrupt did not occur. 343 * | | |1 = Timer0 interrupt occurred. 344 * | | |Note: This bit can be cleared by writing 1 to it. 345 * |[4] |TMR1IF |Timer1 Interrupt Status Flag 346 * | | |This field is used for Timer1 interrupt status flag. 347 * | | |0 = Timer1 interrupt did not occur. 348 * | | |1 = Timer1 interrupt occurred. 349 * | | |Note: This bit can be cleared by writing 1 to it. 350 * |[5] |TMR2IF |Timer2 Interrupt Status Flag 351 * | | |This field is used for Timer2 interrupt status flag. 352 * | | |0 = Timer2 interrupt did not occur. 353 * | | |1 = Timer2 interrupt occurred. 354 * | | |Note: This bit can be cleared by writing 1 to it. 355 * |[6] |BGTIF |Block Guard Time Interrupt Status Flag 356 * | | |This field is used for indicate block guard time interrupt status flag in receive direction. 357 * | | |0 = Block guard time interrupt did not occur. 358 * | | |1 = Block guard time interrupt occurred. 359 * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. 360 * | | |Note2: This bit can be cleared by writing 1 to it. 361 * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) 362 * | | |This field is used for card detect interrupt status flag 363 * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). 364 * | | |0 = Card detect event did not occur. 365 * | | |1 = Card detect event occurred. 366 * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. 367 * |[8] |INITIF |Initial End Interrupt Status Flag 368 * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. 369 * | | |0 = Initial sequence is not complete. 370 * | | |1 = Initial sequence is completed. 371 * | | |Note: This bit can be cleared by writing 1 to it. 372 * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) 373 * | | |This field is used for indicate receive buffer time-out interrupt status flag. 374 * | | |0 = Receive buffer time-out interrupt did not occur. 375 * | | |1 = Receive buffer time-out interrupt occurred. 376 * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. 377 * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag 378 * | | |This field indicates auto convention sequence error. 379 * | | |0 = Received TS at ATR state is 0x3B or 0x3F. 380 * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. 381 * | | |Note: This bit can be cleared by writing 1 to it. 382 * @var SC_T::STATUS 383 * Offset: 0x20 SC Transfer Status Register 384 * --------------------------------------------------------------------------------------------------- 385 * |Bits |Field |Descriptions 386 * | :----: | :----: | :---- | 387 * |[0] |RXOV |Receive Overflow Error Status Flag 388 * | | |This bit is set when Rx buffer overflow. 389 * | | |0 = Rx buffer is not overflow. 390 * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). 391 * | | |Note: This bit can be cleared by writing 1 to it. 392 * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) 393 * | | |This bit indicates Rx buffer empty or not. 394 * | | |0 = Rx buffer is not empty. 395 * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. 396 * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) 397 * | | |This bit indicates Rx buffer full or not. 398 * | | |0 = Rx buffer count is less than 4. 399 * | | |1 = Rx buffer count equals to 4. 400 * |[4] |PEF |Receiver Parity Error Status Flag 401 * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. 402 * | | |0 = Receiver parity error flag did not occur. 403 * | | |1 = Receiver parity error flag occurred. 404 * | | |Note1: This bit can be cleared by writing 1 to it. 405 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 406 * |[5] |FEF |Receiver Frame Error Status Flag 407 * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). 408 * | | |0 = Receiver frame error flag did not occur. 409 * | | |1 = Receiver frame error flag occurred. 410 * | | |Note1: This bit can be cleared by writing 1 to it. 411 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 412 * |[6] |BEF |Receiver Break Error Status Flag 413 * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits). 414 * | | |0 = Receiver break error flag did not occur. 415 * | | |1 = Receiver break error flag occurred. 416 * | | |Note1: This bit can be cleared by writing 1 to it. 417 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 418 * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag 419 * | | |This bit is set when Tx buffer overflow. 420 * | | |0 = Tx buffer is not overflow. 421 * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). 422 * | | |Note: This bit can be cleared by writing 1 to it. 423 * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) 424 * | | |This bit indicates TX buffer empty or not. 425 * | | |0 = Tx buffer is not empty. 426 * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register. 427 * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). 428 * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) 429 * | | |This bit indicates Tx buffer full or not. 430 * | | |0 = Tx buffer count is less than 4. 431 * | | |1 = Tx buffer count equals to 4. 432 * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin 433 * | | |This bit is set whenever card has been removal. 434 * | | |0 = No effect. 435 * | | |1 = Card removed. 436 * | | |Note1: This bit can be cleared by writing 1 to it. 437 * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. 438 * |[12] |CINSERT |Card Insert Status of SCn_CD Pin 439 * | | |This bit is set whenever card has been inserted. 440 * | | |0 = No effect. 441 * | | |1 = Card insert. 442 * | | |Note1: This bit can be cleared by writing 1 to it. 443 * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. 444 * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) 445 * | | |This bit is the pin status of SCn_CD. 446 * | | |0 = The SCn_CD pin state at low. 447 * | | |1 = The SCn_CD pin state at high. 448 * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) 449 * | | |This field indicates the Rx buffer pointer status 450 * | | |When SC controller receives one byte from external device, RXPOINT increases one 451 * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. 452 * |[21] |RXRERR |Receiver Retry Error 453 * | | |This bit is used for receiver error retry and set by hardware. 454 * | | |0 = No Rx retry transfer. 455 * | | |1 = Rx has any error and retries transfer. 456 * | | |Note1: This bit can be cleared by writing 1 to it. 457 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. 458 * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 459 * |[22] |RXOVERR |Receiver over Retry Error 460 * | | |This bit is used for receiver retry counts over than retry number limitation. 461 * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. 462 * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. 463 * | | |Note1: This bit can be cleared by writing 1 to it. 464 * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 465 * |[23] |RXACT |Receiver in Active Status Flag (Read Only) 466 * | | |This bit indicates Rx transfer status. 467 * | | |0 = This bit is cleared automatically when Rx transfer is finished. 468 * | | |1 = This bit is set by hardware when Rx transfer is in active. 469 * | | |Note: This bit is read only. 470 * | | |Note2: 471 * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) 472 * | | |This field indicates the Tx buffer pointer status 473 * | | |When CPU writes data into SCn_DAT, TXPOINT increases one 474 * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. 475 * |[29] |TXRERR |Transmitter Retry Error 476 * | | |This bit is used for indicate transmitter error retry and set by hardware.. 477 * | | |0 = No Tx retry transfer. 478 * | | |1 = Tx has any error and retries transfer. 479 * | | |Note1: This bit can be cleared by writing 1 to it. 480 * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. 481 * |[30] |TXOVERR |Transmitter over Retry Error 482 * | | |This bit is used for transmitter retry counts over than retry number limitation. 483 * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. 484 * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. 485 * | | |Note: This bit can be cleared by writing 1 to it. 486 * |[31] |TXACT |Transmit in Active Status Flag (Read Only) 487 * | | |This bit indicates Tx transmit status. 488 * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed. 489 * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted. 490 * | | |Note: This bit is read only. 491 * @var SC_T::PINCTL 492 * Offset: 0x24 SC Pin Control State Register 493 * --------------------------------------------------------------------------------------------------- 494 * |Bits |Field |Descriptions 495 * | :----: | :----: | :---- | 496 * |[0] |PWREN |SCn_PWR Pin Signal 497 * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. 498 * | | |Write this field to drive SCn_PWR pin 499 * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. 500 * | | |Read this field to get SCn_PWR signal status. 501 * | | |0 = SCn_PWR signal status is low. 502 * | | |1 = SCn_PWR signal status is high. 503 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically 504 * | | |Thus, do not fill in this field when operating in these modes. 505 * |[1] |RSTEN |SCn_RST Pin Signal 506 * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. 507 * | | |Write this field to drive SCn_RST pin. 508 * | | |0 = Drive SCn_RST pin to low. 509 * | | |1 = Drive SCn_RST pin to high. 510 * | | |Read this field to get SCn_RST signal status. 511 * | | |0 = SCn_RST signal status is low. 512 * | | |1 = SCn_RST signal status is high. 513 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically 514 * | | |Thus, do not fill in this field when operating in these modes. 515 * |[5] |CSTOPLV |SCn_CLK Pin Stop Level 516 * | | |This field indicates the SCn_CLK pin status when SC clock in clock stop mode. 517 * | | |0 = SCn_CLK pin keeps at low when SC clock stopped. 518 * | | |1 = SCn_CLK pin keeps at high when SC clock stopped. 519 * |[6] |CLKKEEP |SC Clock Enable Bit 520 * | | |0 = SC clock generation Disabled. 521 * | | |1 = SC clock always keeps free running. 522 * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically 523 * | | |Thus, do not fill in this field when operating in these modes. 524 * |[9] |SCDATA |SCn_DATA Pin Signal 525 * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. 526 * | | |0 = Drive SCn_DATA pin to low. 527 * | | |1 = Drive SCn_DATA pin to high. 528 * | | |Read this field to get SCn_DATA signal status. 529 * | | |0 = SCn_DATA signal status is low. 530 * | | |1 = SCn_DATA signal status is high. 531 * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically 532 * | | |Thus, do not fill in this field when SC is in these modes. 533 * |[11] |PWRINV |SCn_PWR Pin Inverse 534 * | | |This bit is used for inverse the SCn_PWR pin. 535 * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). 536 * | | |0 = SCn_PWR pin inverse Disabled 537 * | | |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0. 538 * | | |1 = SCn_PWR pin inverse Enabled 539 * | | |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1. 540 * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). 541 * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) 542 * | | |This bit is the pin status of SCn_DATA. 543 * | | |0 = The SCn_DATA pin status is low. 544 * | | |1 = The SCn_DATA pin status is high. 545 * | | |Note: 546 * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) 547 * | | |This bit is the pin status of SCn_PWR. 548 * | | |0 = SCn_PWR pin to low. 549 * | | |1 = SCn_PWR pin to high. 550 * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) 551 * | | |This bit is the pin status of SCn_RST. 552 * | | |0 = SCn_RST pin is low. 553 * | | |1 = SCn_RST pin is high. 554 * |[30] |SYNC |SYNC Flag Indicator (Read Only) 555 * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. 556 * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. 557 * | | |1 = Last value is synchronizing. 558 * @var SC_T::TMRCTL0 559 * Offset: 0x28 SC Internal Timer0 Control Register 560 * --------------------------------------------------------------------------------------------------- 561 * |Bits |Field |Descriptions 562 * | :----: | :----: | :---- | 563 * |[23:0] |CNT |Timer0 Counter Value 564 * | | |This field indicates the internal Timer0 counter values. 565 * | | |Note: Unit of Timer0 counter is ETU base. 566 * |[27:24] |OPMODE |Timer0 Operation Mode Selection 567 * | | |This field indicates the internal 24-bit Timer0 operation selection. 568 * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0. 569 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 570 * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. 571 * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. 572 * | | |1 = Last value is synchronizing. 573 * @var SC_T::TMRCTL1 574 * Offset: 0x2C SC Internal Timer1 Control Register 575 * --------------------------------------------------------------------------------------------------- 576 * |Bits |Field |Descriptions 577 * | :----: | :----: | :---- | 578 * |[7:0] |CNT |Timer 1 Counter Value 579 * | | |This field indicates the internal Timer1 counter values. 580 * | | |Note: Unit of Timer1 counter is ETU base. 581 * |[27:24] |OPMODE |Timer 1 Operation Mode Selection 582 * | | |This field indicates the internal 8-bit Timer1 operation selection. 583 * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1. 584 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 585 * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. 586 * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. 587 * | | |1 = Last value is synchronizing. 588 * @var SC_T::TMRCTL2 589 * Offset: 0x30 SC Internal Timer2 Control Register 590 * --------------------------------------------------------------------------------------------------- 591 * |Bits |Field |Descriptions 592 * | :----: | :----: | :---- | 593 * |[7:0] |CNT |Timer 2 Counter Value 594 * | | |This field indicates the internal Timer2 counter values. 595 * | | |Note: Unit of Timer2 counter is ETU base. 596 * |[27:24] |OPMODE |Timer 2 Operation Mode Selection 597 * | | |This field indicates the internal 8-bit Timer2 operation selection 598 * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2. 599 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 600 * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. 601 * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. 602 * | | |1 = Last value is synchronizing. 603 * @var SC_T::UARTCTL 604 * Offset: 0x34 SC UART Mode Control Register 605 * --------------------------------------------------------------------------------------------------- 606 * |Bits |Field |Descriptions 607 * | :----: | :----: | :---- | 608 * |[0] |UARTEN |UART Mode Enable Bit 609 * | | |Sets this bit to enable UART mode function. 610 * | | |0 = Smart Card mode. 611 * | | |1 = UART mode. 612 * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. 613 * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. 614 * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. 615 * |[5:4] |WLS |Word Length Selection 616 * | | |This field is used for select UART data length. 617 * | | |00 = Word length is 8 bits. 618 * | | |01 = Word length is 7 bits. 619 * | | |10 = Word length is 6 bits. 620 * | | |11 = Word length is 5 bits. 621 * | | |Note: In smart card mode, this WLS must be u201800'. 622 * |[6] |PBOFF |Parity Bit Disable Control 623 * | | |Sets this bit is used for disable parity check function. 624 * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. 625 * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. 626 * | | |Note: In smart card mode, this field must be u20180' (default setting is with parity bit). 627 * |[7] |OPE |Odd Parity Enable Bit 628 * | | |This is used for odd/even parity selection. 629 * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. 630 * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. 631 * | | |Note: This bit has effect only when PBOFF bit is u20180'. 632 * @var SC_T::ACTCTL 633 * Offset: 0x4C SC Activation Control Register 634 * --------------------------------------------------------------------------------------------------- 635 * |Bits |Field |Descriptions 636 * | :----: | :----: | :---- | 637 * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation 638 * | | |This field provide the configurable cycles to extend the activation time T1 period. 639 * | | |The cycle scaling factor is 2048. 640 * | | |Extend cycles = (filled value * 2048) cycles. 641 * | | |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence. 642 * | | |For example, 643 * | | |SCLK = 4MHz, each cycle = 0.25us,. 644 * | | |Filled 20 to this field 645 * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. 646 * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 647 */ 648 __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ 649 __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ 650 __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ 651 __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ 652 __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ 653 __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ 654 __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ 655 __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ 656 __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ 657 __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ 658 __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ 659 __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ 660 __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ 661 __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ 662 __I uint32_t RESERVE0[5]; 663 __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ 664 665 } SC_T; 666 667 /** 668 @addtogroup SC_CONST SC Bit Field Definition 669 Constant Definitions for SC Controller 670 @{ 671 */ 672 673 #define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ 674 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ 675 676 #define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ 677 #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ 678 679 #define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ 680 #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ 681 682 #define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ 683 #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ 684 685 #define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ 686 #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ 687 688 #define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ 689 #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ 690 691 #define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ 692 #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ 693 694 #define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ 695 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ 696 697 #define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ 698 #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ 699 700 #define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ 701 #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ 702 703 #define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ 704 #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ 705 706 #define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ 707 #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ 708 709 #define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ 710 #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ 711 712 #define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ 713 #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ 714 715 #define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ 716 #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ 717 718 #define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ 719 #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ 720 721 #define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ 722 #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ 723 724 #define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ 725 #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ 726 727 #define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ 728 #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ 729 730 #define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ 731 #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ 732 733 #define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ 734 #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ 735 736 #define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ 737 #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ 738 739 #define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ 740 #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ 741 742 #define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ 743 #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ 744 745 #define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ 746 #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ 747 748 #define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ 749 #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ 750 751 #define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ 752 #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ 753 754 #define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ 755 #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ 756 757 #define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ 758 #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ 759 760 #define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ 761 #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ 762 763 #define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ 764 #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ 765 766 #define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ 767 #define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ 768 769 #define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ 770 #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ 771 772 #define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ 773 #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ 774 775 #define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ 776 #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ 777 778 #define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ 779 #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ 780 781 #define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ 782 #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ 783 784 #define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ 785 #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ 786 787 #define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ 788 #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ 789 790 #define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ 791 #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ 792 793 #define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ 794 #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ 795 796 #define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ 797 #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ 798 799 #define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ 800 #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ 801 802 #define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ 803 #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ 804 805 #define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ 806 #define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ 807 808 #define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ 809 #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ 810 811 #define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ 812 #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ 813 814 #define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ 815 #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ 816 817 #define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ 818 #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ 819 820 #define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ 821 #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ 822 823 #define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ 824 #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ 825 826 #define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ 827 #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ 828 829 #define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ 830 #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ 831 832 #define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ 833 #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ 834 835 #define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ 836 #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ 837 838 #define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ 839 #define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ 840 841 #define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ 842 #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ 843 844 #define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ 845 #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ 846 847 #define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ 848 #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ 849 850 #define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ 851 #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ 852 853 #define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ 854 #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ 855 856 #define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ 857 #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ 858 859 #define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ 860 #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ 861 862 #define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ 863 #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ 864 865 #define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ 866 #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ 867 868 #define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ 869 #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ 870 871 #define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ 872 #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ 873 874 #define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ 875 #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ 876 877 #define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ 878 #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ 879 880 #define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ 881 #define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ 882 883 #define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ 884 #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ 885 886 #define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ 887 #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ 888 889 #define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ 890 #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ 891 892 #define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ 893 #define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ 894 895 #define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ 896 #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ 897 898 #define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ 899 #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ 900 901 #define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ 902 #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ 903 904 #define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ 905 #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ 906 907 #define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ 908 #define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ 909 910 #define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */ 911 #define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Mask */ 912 913 #define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ 914 #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ 915 916 #define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ 917 #define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ 918 919 #define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ 920 #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ 921 922 #define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ 923 #define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ 924 925 #define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ 926 #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ 927 928 #define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ 929 #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ 930 931 #define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ 932 #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ 933 934 #define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ 935 #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ 936 937 #define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ 938 #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ 939 940 #define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ 941 #define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ 942 943 #define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ 944 #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ 945 946 #define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ 947 #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ 948 949 #define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ 950 #define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ 951 952 #define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ 953 #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ 954 955 #define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ 956 #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ 957 958 #define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ 959 #define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ 960 961 #define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ 962 #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ 963 964 #define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ 965 #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ 966 967 #define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ 968 #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ 969 970 #define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ 971 #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ 972 973 #define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ 974 #define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ 975 976 /**@}*/ /* SC_CONST */ 977 /**@}*/ /* end of SC register group */ 978 /**@}*/ /* end of REGISTER group */ 979 980 #endif /* __SC_REG_H__ */ 981
