1 /* 2 * Copyright (c) 2019 Arm Limited. All rights reserved. 3 * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. 4 * Copyright (c) 2021 Laird Connectivity. All rights reserved. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef __RTE_DEVICE_H 20 #define __RTE_DEVICE_H 21 22 #include <nrf-pinctrl.h> 23 24 #define RTE_USART0 1 25 26 #define RTE_USART0_PINS \ 27 { \ 28 NRF_PSEL(UART_TX, 0, 20), \ 29 NRF_PSEL(UART_RX, 0, 22), \ 30 NRF_PSEL(UART_RTS, 0, 19), \ 31 NRF_PSEL(UART_CTS, 0, 21), \ 32 } 33 34 35 #define RTE_USART1 1 36 37 #define RTE_USART1_PINS \ 38 { \ 39 NRF_PSEL(UART_TX, 1, 8), \ 40 NRF_PSEL(UART_RX, 1, 10), \ 41 NRF_PSEL(UART_RTS, 1, 7), \ 42 NRF_PSEL(UART_CTS, 1, 9), \ 43 } 44 45 // <e> TWIM (Two-wire interface master) [Driver_TWIM2] 46 // <i> Configuration settings for Driver_TWIM2 in component ::Drivers:TWIM 47 #define RTE_TWIM2 1 48 // <h> Pin Selection (0xFFFFFFFF means Disconnected) 49 // <o> SCL 50 #define RTE_TWIM2_SCL_PIN 35 51 // <o> SDA 52 #define RTE_TWIM2_SDA_PIN 34 53 // </h> Pin Configuration 54 // </e> TWIM (Two-wire interface master) [Driver_TWIM2] 55 56 // <e> QSPI (Quad serial peripheral interface) [Driver_QSPI0] 57 // <i> Configuration settings for Driver_QSPI0 in component ::Drivers:QSPI 58 #define RTE_QSPI0 1 59 // <h> Pin Selection (0xFFFFFFFF means Disconnected) 60 // <o> IO0 61 #define RTE_QSPI0_IO0_PIN 13 62 // <o> IO1 63 #define RTE_QSPI0_IO1_PIN 14 64 // <o> IO2 65 #define RTE_QSPI0_IO2_PIN 15 66 // <o> IO3 67 #define RTE_QSPI0_IO3_PIN 16 68 // <o> SCL 69 #define RTE_QSPI0_SCL_PIN 17 70 // <o> CSN 71 #define RTE_QSPI0_CSN_PIN 18 72 // </h> Pin Configuration 73 // </e> QSPI (Quad serial peripheral interface) [Driver_QSPI0] 74 75 // <e> FLASH (Flash Memory) [Driver_FLASH0] 76 // <i> Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH 77 #define RTE_FLASH0 1 78 // </e> FLASH (Flash Memory) [Driver_FLASH0] 79 80 #endif /* __RTE_DEVICE_H */ 81
