| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/CoreValidation/Source/ |
| D | CV_MPU_ARMv8.c | 20 MPU->RLAR = 0U; in ClearMpu()
39 { .RBAR = 0U, .RLAR = 0U }, in TC_MPU_SetClear()
40 { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) } in TC_MPU_SetClear()
46 ASSERT_TRUE(MPU->RLAR == region.RLAR) in TC_MPU_SetClear()
50 ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR); in TC_MPU_SetClear()
59 ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U); in TC_MPU_SetClear()
75 { .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) }, in TC_MPU_Load()
76 { .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) }, in TC_MPU_Load()
77 { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) }, in TC_MPU_Load()
78 { .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) }, in TC_MPU_Load()
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/target/armchina/mps3/alcor/an557/cmsis_drivers/ |
| D | Driver_Flash.c | 77 mpu_state->mpu_table[i].RLAR = mpu->RLAR; in mpu_save()
79 mpu->RLAR = 0; in mpu_save()
107 mpu->RLAR = ARM_MPU_RLAR_PXN((memory_base + qspi_flash_size) - 1, 1, mpu_attr_num); in mpu_save()
109 mpu->RLAR = ARM_MPU_RLAR((memory_base + qspi_flash_size) - 1, mpu_attr_num); in mpu_save()
132 mpu->RLAR = mpu_state->mpu_table[i].RLAR; in mpu_restore()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps3/corstone310/an555/cmsis_drivers/ |
| D | Driver_Flash.c | 77 mpu_state->mpu_table[i].RLAR = mpu->RLAR; in mpu_save()
79 mpu->RLAR = 0; in mpu_save()
107 mpu->RLAR = ARM_MPU_RLAR_PXN((memory_base + qspi_flash_size) - 1, 1, mpu_attr_num); in mpu_save()
109 mpu->RLAR = ARM_MPU_RLAR((memory_base + qspi_flash_size) - 1, mpu_attr_num); in mpu_save()
132 mpu->RLAR = mpu_state->mpu_table[i].RLAR; in mpu_restore()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps3/corstone300/an547/cmsis_drivers/ |
| D | Driver_Flash.c | 77 mpu_state->mpu_table[i].RLAR = mpu->RLAR; in mpu_save()
79 mpu->RLAR = 0; in mpu_save()
107 mpu->RLAR = ARM_MPU_RLAR_PXN((memory_base + qspi_flash_size) - 1, 1, mpu_attr_num); in mpu_save()
109 mpu->RLAR = ARM_MPU_RLAR((memory_base + qspi_flash_size) - 1, mpu_attr_num); in mpu_save()
132 mpu->RLAR = mpu_state->mpu_table[i].RLAR; in mpu_restore()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps3/corstone300/an552/cmsis_drivers/ |
| D | Driver_Flash.c | 77 mpu_state->mpu_table[i].RLAR = mpu->RLAR; in mpu_save()
79 mpu->RLAR = 0; in mpu_save()
107 mpu->RLAR = ARM_MPU_RLAR_PXN((memory_base + qspi_flash_size) - 1, 1, mpu_attr_num); in mpu_save()
109 mpu->RLAR = ARM_MPU_RLAR((memory_base + qspi_flash_size) - 1, mpu_attr_num); in mpu_save()
132 mpu->RLAR = mpu_state->mpu_table[i].RLAR; in mpu_restore()
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/hal/Native_Driver/ |
| D | mpu_armv8m_drv.c | 147 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
192 if ((mpu->RBAR == base_cfg) && (mpu->RLAR == limit_cfg)) in mpu_armv8m_region_enable_check()
218 mpu->RLAR = 0; in mpu_armv8m_region_disable()
237 if ((mpu->RBAR == 0) && (mpu->RLAR == 0)) in mpu_armv8m_region_disable_check()
287 mpu->RLAR = limit_cfg; in mpu_armv8m_region_config_only()
333 if ((mpu->RBAR == base_cfg) && (mpu->RLAR == limit_cfg)) in mpu_armv8m_region_config_only_check()
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/secure/ |
| D | target_cfg.c | 135 SAU->RLAR = (memory_regions.non_secure_partition_limit in sau_and_idau_cfg()
141 SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; in sau_and_idau_cfg()
146 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
153 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
158 SAU->RLAR = ((PACKAGE_BASE + 0xfff) & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/common/ |
| D | tfm_hal_isolation_v8m.c | 251 localcfg.RLAR = mpu_region_attributes[i].RLAR; in tfm_hal_set_up_static_boundaries()
252 ARM_MPU_SetRegion(i, localcfg.RBAR, localcfg.RLAR); in tfm_hal_set_up_static_boundaries()
377 local_mpu_region.RLAR = ARM_MPU_RLAR_PXN(plat_data_ptr->periph_limit, in tfm_hal_bind_boundary()
381 local_mpu_region.RLAR = ARM_MPU_RLAR(plat_data_ptr->periph_limit, in tfm_hal_bind_boundary()
388 local_mpu_region.RLAR); in tfm_hal_bind_boundary()
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| /trusted-firmware-m-3.7.0/platform/ext/target/armchina/mps3/alcor/common/ |
| D | target_cfg.c | 434 SAU->RLAR = ((ITCM_BASE_NS + ITCM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
441 SAU->RLAR = ((CODE_MEM_BASE_NS + CODE_MEM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
448 SAU->RLAR = ((DTCM0_BASE_NS + (DTCM_BLK_SIZE * DTCM_BLK_NUM) - 1) in sau_and_idau_cfg()
453 SAU->RLAR = ((ISRAM1_BASE_NS + ISRAM1_SIZE - 1) in sau_and_idau_cfg()
459 SAU->RLAR = (memory_regions.non_secure_partition_limit in sau_and_idau_cfg()
464 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
469 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
474 SAU->RLAR = ((DDR4_BLK0_BASE_NS + ((uint32_t)DDR4_BLK_NUM * DDR4_BLK_SIZE) - 1) in sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps4/corstone315/ |
| D | target_cfg.c | 455 SAU->RLAR = ((ITCM_BASE_NS + ITCM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
462 SAU->RLAR = ((SRAM_BASE_NS + SRAM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
469 SAU->RLAR = ((DTCM0_BASE_NS + (DTCM_BLK_SIZE * DTCM_BLK_NUM) - 1) in sau_and_idau_cfg()
474 SAU->RLAR = ((ISRAM1_BASE_NS + ISRAM1_SIZE - 1) in sau_and_idau_cfg()
480 SAU->RLAR = (memory_regions.non_secure_partition_limit in sau_and_idau_cfg()
485 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
490 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
495 SAU->RLAR = ((DDR4_BLK0_BASE_NS + ((uint32_t)DDR4_BLK_NUM * DDR4_BLK_SIZE) - 1) in sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps3/corstone300/common/ |
| D | target_cfg.c | 439 SAU->RLAR = ((ITCM_BASE_NS + ITCM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
446 SAU->RLAR = ((SRAM_BASE_NS + SRAM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
453 SAU->RLAR = ((DTCM0_BASE_NS + (DTCM_BLK_SIZE * DTCM_BLK_NUM) - 1) in sau_and_idau_cfg()
458 SAU->RLAR = ((ISRAM1_BASE_NS + ISRAM1_SIZE - 1) in sau_and_idau_cfg()
464 SAU->RLAR = (memory_regions.non_secure_partition_limit in sau_and_idau_cfg()
469 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
474 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
479 SAU->RLAR = ((DDR4_BLK0_BASE_NS + ((uint32_t)DDR4_BLK_NUM * DDR4_BLK_SIZE) - 1) in sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps3/corstone310/common/ |
| D | target_cfg.c | 447 SAU->RLAR = ((ITCM_BASE_NS + ITCM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
454 SAU->RLAR = ((SRAM_BASE_NS + SRAM_SIZE - 1) & SAU_RBAR_BADDR_Msk) in sau_and_idau_cfg()
461 SAU->RLAR = ((DTCM0_BASE_NS + (DTCM_BLK_SIZE * DTCM_BLK_NUM) - 1) in sau_and_idau_cfg()
466 SAU->RLAR = ((ISRAM1_BASE_NS + ISRAM1_SIZE - 1) in sau_and_idau_cfg()
472 SAU->RLAR = (memory_regions.non_secure_partition_limit in sau_and_idau_cfg()
477 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
482 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
487 SAU->RLAR = ((DDR4_BLK0_BASE_NS + ((uint32_t)DDR4_BLK_NUM * DDR4_BLK_SIZE) - 1) in sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps2/an519/native_drivers/ |
| D | mpu_armv8m_drv.c | 108 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
139 mpu->RLAR = 0; in mpu_armv8m_region_disable()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/musca_b1/Native_Driver/ |
| D | mpu_armv8m_drv.c | 108 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
139 mpu->RLAR = 0; in mpu_armv8m_region_disable()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/musca_s1/Native_Driver/ |
| D | mpu_armv8m_drv.c | 108 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
139 mpu->RLAR = 0; in mpu_armv8m_region_disable()
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| /trusted-firmware-m-3.7.0/platform/ext/target/nuvoton/common/native_drivers/ |
| D | mpu_armv8m_drv.c | 104 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
135 mpu->RLAR = 0; in mpu_armv8m_region_disable()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/drivers/mpu/armv8m/ |
| D | mpu_armv8m_drv.c | 111 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
139 mpu->RLAR = 0; in mpu_armv8m_region_disable()
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| /trusted-firmware-m-3.7.0/platform/ext/target/nordic_nrf/common/core/native_drivers/ |
| D | mpu_armv8m_drv.c | 111 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
142 mpu->RLAR = 0; in mpu_armv8m_region_disable()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps2/an521/native_drivers/ |
| D | mpu_armv8m_drv.c | 107 mpu->RLAR = limit_cfg; in mpu_armv8m_region_enable()
135 mpu->RLAR = 0; in mpu_armv8m_region_disable()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/rse/common/ |
| D | target_cfg.c | 339 SAU->RLAR = (memory_regions.non_secure_partition_limit in sau_and_idau_cfg()
344 SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; in sau_and_idau_cfg()
350 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
357 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
363 SAU->RLAR = (HOST_ACCESS_LIMIT_NS & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps2/an521/ |
| D | target_cfg.c | 321 uint32_t RLAR; member
399 SAU->RLAR = (sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) | in sau_and_idau_cfg()
430 if (SAU->RLAR != ((sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) | in fih_verify_sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/arm/mps3/an524/ |
| D | target_cfg.c | 266 SAU->RLAR = (memory_regions.non_secure_partition_limit in sau_and_idau_cfg()
271 SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; in sau_and_idau_cfg()
276 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
282 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) in sau_and_idau_cfg()
290 SAU->RLAR = (memory_regions.secondary_partition_limit in sau_and_idau_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/boards/ |
| D | target_cfg.h | 73 uint32_t RLAR; member
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/boards/ |
| D | target_cfg.h | 75 uint32_t RLAR; member
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| /trusted-firmware-m-3.7.0/platform/ext/cmsis/CMSIS/Core/Include/m-profile/ |
| D | armv8m_mpu.h | 184 uint32_t RLAR; /*!< Region Limit Address Register value */ member
297 mpu->RLAR = 0U; in ARM_MPU_ClrRegionEx()
328 mpu->RLAR = rlar; in ARM_MPU_SetRegionEx()
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