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Searched refs:RCC_CFGR2_HPRE_Pos (Results 1 – 10 of 10) sorted by relevance

/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/secure/
Dsystem_stm32u5xx.c318 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/secure/
Dsystem_stm32h5xx.c266 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/Device/Source/Templates/
Dsystem_stm32u5xx.c324 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/Device/Source/Templates/
Dsystem_stm32h5xx.c258 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/hal/Src/
Dstm32u5xx_hal.c153 … = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; in HAL_Init()
Dstm32u5xx_hal_rcc.c1491 … = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; in HAL_RCC_ClockConfig()
1707 … = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; in HAL_RCC_GetHCLKFreq()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/hal/Src/
Dstm32h5xx_hal.c145 … = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; in HAL_Init()
Dstm32h5xx_hal_rcc.c1227 … = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; in HAL_RCC_ClockConfig()
1471 >> RCC_CFGR2_HPRE_Pos] & 0x1FU); in HAL_RCC_GetHCLKFreq()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/Device/Include/
Dstm32u585xx.h15363 #define RCC_CFGR2_HPRE_Pos (0U) macro
15364 #define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F…
15366 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001…
15367 #define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002…
15368 #define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004…
15369 #define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008…
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/Device/Include/
Dstm32h573xx.h15786 #define RCC_CFGR2_HPRE_Pos (0U) macro
15787 #define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F…
15789 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001…
15790 #define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002…
15791 #define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004…
15792 #define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008…