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Searched refs:RCC (Results 1 – 25 of 33) sorted by relevance

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/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/hal/Inc/
Dstm32u5xx_hal_rcc.h676 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
678 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
685 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
692 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
697 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
699 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
704 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
706 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32u5xx_hal_rcc_ex.h874 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM3), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
879 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM2), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
884 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM1), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
889 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM0), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\
911 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)); \
913 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(uint32_t)(__TIMICSOURCE__));\
919 #define __HAL_RCC_TIMIC_CLK_DISABLE() MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000))
928 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
929 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
939 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2…
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/hal/Inc/
Dstm32l5xx_hal_rcc.h656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
658 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
664 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
666 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
672 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
674 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
679 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
681 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
687 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
689 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32l5xx_hal_rcc_ex.h727 MODIFY_REG(RCC->PLLSAI1CFGR, \
754 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_…
768 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PL…
783 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI…
798 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI…
813 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI…
821 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
823 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
839 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1…
841 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSA…
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/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/hal/Inc/
Dstm32h5xx_hal_rcc.h744 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
746 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
752 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \
754 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \
761 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
763 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
771 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
773 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
780 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
782 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32h5xx_hal_rcc_ex.h1390 #define __HAL_RCC_TIMIC_ENABLE() SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/…
1391 #define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock avail…
1403 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2…
1414 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC))
1449 WRITE_REG(RCC->PLL2CFGR,((__PLL2SOURCE__) << RCC_PLL2CFGR_PLL2SRC_Pos) | \
1451 WRITE_REG(RCC->PLL2DIVR , ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | \
1472 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, ((__PLL2N__) - 1U) << RCC_PLL2DIVR_N2_Pos)
1487 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_DIVM2, (__PLL2M__) << RCC_PLL2CFGR_DIVM2_Pos)
1502 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, ((__PLL2P__) - 1U) << RCC_PLL2DIVR_P2_Pos)
1517 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, ((__PLL2Q__) - 1U) << RCC_PLL2DIVR_Q2_Pos)
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/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/Device/Source/Templates/
Dsystem_stm32h5xx.c199 switch (RCC->CFGR1 & RCC_CFGR1_SWS) in SystemCoreClockUpdate()
202 SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); in SystemCoreClockUpdate()
217 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
218 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
219 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
220 …fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRAC… in SystemCoreClockUpdate()
229 hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; in SystemCoreClockUpdate()
230 …pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_… in SystemCoreClockUpdate()
234 …pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_… in SystemCoreClockUpdate()
238 …pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_… in SystemCoreClockUpdate()
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/hal/Src/
Dstm32l5xx_hal_rcc.c247 SET_BIT(RCC->CR, RCC_CR_MSION); in HAL_RCC_DeInit()
254 while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) in HAL_RCC_DeInit()
259 if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) in HAL_RCC_DeInit()
267 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6); in HAL_RCC_DeInit()
270 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
286 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_SYSCLKSOURCE_STATUS_MSI) in HAL_RCC_DeInit()
291 if (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_SYSCLKSOURCE_STATUS_MSI) in HAL_RCC_DeInit()
299 …CLEAR_BIT(RCC->CR, RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS |… in HAL_RCC_DeInit()
308 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) in HAL_RCC_DeInit()
313 if (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) in HAL_RCC_DeInit()
[all …]
Dstm32l5xx_hal_rcc_ex.c291 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
296 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); in HAL_RCCEx_PeriphCLKConfig()
301 RCC->BDCR = tmpregister; in HAL_RCCEx_PeriphCLKConfig()
311 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) in HAL_RCCEx_PeriphCLKConfig()
316 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) in HAL_RCCEx_PeriphCLKConfig()
701 …PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1SRC) … in HAL_RCCEx_GetPeriphCLKConfig()
702 …PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_… in HAL_RCCEx_GetPeriphCLKConfig()
703 …PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_… in HAL_RCCEx_GetPeriphCLKConfig()
704 …PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC… in HAL_RCCEx_GetPeriphCLKConfig()
705 …PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC… in HAL_RCCEx_GetPeriphCLKConfig()
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/hal/Src/
Dstm32h5xx_hal_rcc.c262 SET_BIT(RCC->CR, RCC_CR_HSION); in HAL_RCC_DeInit()
265 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) in HAL_RCC_DeInit()
274 CLEAR_BIT(RCC->CR, RCC_CR_HSIDIV); in HAL_RCC_DeInit()
277 WRITE_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); in HAL_RCC_DeInit()
290 CLEAR_REG(RCC->CFGR1); in HAL_RCC_DeInit()
291 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
294 while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U) in HAL_RCC_DeInit()
303 …CLEAR_BIT(RCC->CR, RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSECSSON | RCC_CR_HSIKERON | RCC_CR_HSI… in HAL_RCC_DeInit()
307 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); in HAL_RCC_DeInit()
313 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); in HAL_RCC_DeInit()
[all …]
Dstm32h5xx_hal_rcc_ex.c1745 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
1750 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); in HAL_RCCEx_PeriphCLKConfig()
1755 RCC->BDCR = tmpregister; in HAL_RCCEx_PeriphCLKConfig()
1765 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) in HAL_RCCEx_PeriphCLKConfig()
2596 …pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFG… in HAL_RCCEx_GetPeriphCLKConfig()
2597 …pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M… in HAL_RCCEx_GetPeriphCLKConfig()
2598 …pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N… in HAL_RCCEx_GetPeriphCLKConfig()
2599 …pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P… in HAL_RCCEx_GetPeriphCLKConfig()
2600 …pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q… in HAL_RCCEx_GetPeriphCLKConfig()
2601 …pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R… in HAL_RCCEx_GetPeriphCLKConfig()
[all …]
Dstm32h5xx_hal_cortex.c421 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, (0x00000000U)); in HAL_SYSTICK_CLKSourceConfig()
426 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, RCC_CCIPR4_SYSTICKSEL_0); in HAL_SYSTICK_CLKSourceConfig()
431 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, RCC_CCIPR4_SYSTICKSEL_1); in HAL_SYSTICK_CLKSourceConfig()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/Device/Source/Templates/
Dsystem_stm32u5xx.c256 if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) in SystemCoreClockUpdate()
259 msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; in SystemCoreClockUpdate()
264 msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; in SystemCoreClockUpdate()
271 switch (RCC->CFGR1 & RCC_CFGR1_SWS) in SystemCoreClockUpdate()
289 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
290 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
291 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
292 …fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRAC… in SystemCoreClockUpdate()
313 …pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x20… in SystemCoreClockUpdate()
314 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); in SystemCoreClockUpdate()
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/hal/Src/
Dstm32u5xx_hal_rcc.c210 (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
378 SET_BIT(RCC->CR, RCC_CR_MSISON); in HAL_RCC_DeInit()
381 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) in HAL_RCC_DeInit()
390 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, RCC_MSIRANGE_4); in HAL_RCC_DeInit()
393 WRITE_REG(RCC->ICSCR2, 0x00084210U); in HAL_RCC_DeInit()
396 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, RCC_MSIKRANGE_4); in HAL_RCC_DeInit()
399 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL, 0x0U); in HAL_RCC_DeInit()
404 CLEAR_REG(RCC->CFGR1); in HAL_RCC_DeInit()
405 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
408 while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U) in HAL_RCC_DeInit()
[all …]
Dstm32u5xx_hal_rcc_ex.c726 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
731 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); in HAL_RCCEx_PeriphCLKConfig()
736 RCC->BDCR = tmpregister; in HAL_RCCEx_PeriphCLKConfig()
746 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) in HAL_RCCEx_PeriphCLKConfig()
1000 …pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFG… in HAL_RCCEx_GetPeriphCLKConfig()
1001 …pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M… in HAL_RCCEx_GetPeriphCLKConfig()
1002 …pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N… in HAL_RCCEx_GetPeriphCLKConfig()
1003 …pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P… in HAL_RCCEx_GetPeriphCLKConfig()
1004 …pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q… in HAL_RCCEx_GetPeriphCLKConfig()
1005 …pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R… in HAL_RCCEx_GetPeriphCLKConfig()
[all …]
Dstm32u5xx_hal_cortex.c422 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U)); in HAL_SYSTICK_CLKSourceConfig()
427 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0); in HAL_SYSTICK_CLKSourceConfig()
432 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1); in HAL_SYSTICK_CLKSourceConfig()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/secure/
Dsystem_stm32h5xx.c207 switch (RCC->CFGR1 & RCC_CFGR1_SWS) in SystemCoreClockUpdate()
210 SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); in SystemCoreClockUpdate()
225 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
226 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
227 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
228 …fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRAC… in SystemCoreClockUpdate()
237 hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; in SystemCoreClockUpdate()
238 …pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_… in SystemCoreClockUpdate()
242 …pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_… in SystemCoreClockUpdate()
246 …pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_… in SystemCoreClockUpdate()
[all …]
Dtfm_hal_isolation.c300 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, 0x40 << RCC_HSICFGR_HSITRIM_Pos); in SetSysClock()
301 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, RCC_HSI_DIV1); in SetSysClock()
303 SET_BIT(RCC->CR, RCC_CR_HSION); in SetSysClock()
304 while((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY) in SetSysClock()
312 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, RCC_PLL1CFGR_PLL1SRC_0); in SetSysClock()
315 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); in SetSysClock()
316 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); in SetSysClock()
317 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in SetSysClock()
318 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); in SetSysClock()
319 …MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, RCC_PLL1CFGR_PLL1SRC_1 << RCC_PLL1CFGR_PLL1RGE_Pos… in SetSysClock()
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/secure/
Dsystem_stm32u5xx.c250 if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) in SystemCoreClockUpdate()
253 msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; in SystemCoreClockUpdate()
258 msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; in SystemCoreClockUpdate()
265 switch (RCC->CFGR1 & RCC_CFGR1_SWS) in SystemCoreClockUpdate()
283 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
284 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
285 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
286 …fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRAC… in SystemCoreClockUpdate()
307 …pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x20… in SystemCoreClockUpdate()
308 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); in SystemCoreClockUpdate()
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/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/Device/Source/Templates/
Dsystem_stm32l5xx.c263 if((RCC->CR & RCC_CR_MSIRGSEL) == 0U) in SystemCoreClockUpdate()
265 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; in SystemCoreClockUpdate()
269 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; in SystemCoreClockUpdate()
275 switch (RCC->CFGR & RCC_CFGR_SWS) in SystemCoreClockUpdate()
293 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); in SystemCoreClockUpdate()
294 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; in SystemCoreClockUpdate()
310 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); in SystemCoreClockUpdate()
311 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; in SystemCoreClockUpdate()
321 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/secure/
Dsystem_stm32l5xx.c249 if((RCC->CR & RCC_CR_MSIRGSEL) == 0U) in SystemCoreClockUpdate()
251 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; in SystemCoreClockUpdate()
255 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; in SystemCoreClockUpdate()
261 switch (RCC->CFGR & RCC_CFGR_SWS) in SystemCoreClockUpdate()
279 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); in SystemCoreClockUpdate()
280 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; in SystemCoreClockUpdate()
296 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); in SystemCoreClockUpdate()
297 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; in SystemCoreClockUpdate()
307 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/bl2/
Dstm32h5xx_hal_msp.c238 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U) in RCC_OscConfig()
255 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U) in RCC_OscConfig()
302 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) in RCC_OscConfig()
316 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) in RCC_OscConfig()
377 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); in RCCEx_PeriphCLKConfig()
382 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); in RCCEx_PeriphCLKConfig()
387 RCC->BDCR = tmpregister; in RCCEx_PeriphCLKConfig()
397 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) in RCCEx_PeriphCLKConfig()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/Device/Source/
Dstartup_stm32u5xx_ns.c392 RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; in Reset_Handler()
394 tmp = RCC->APB3ENR; in Reset_Handler()
Dstartup_stm32u5xx_s.c402 RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; in Reset_Handler()
404 tmp = RCC->APB3ENR; in Reset_Handler()
/trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/Device/Source/
Dstartup_stm32h5xx_ns.c517 RCC->APB3ENR |= RCC_APB3ENR_SBSEN; in Reset_Handler()
519 tmp = RCC->APB3ENR; in Reset_Handler()

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