1 /**************************************************************************//** 2 * @file otg_reg.h 3 * @version V1.00 4 * @brief OTG register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __OTG_REG_H__ 10 #define __OTG_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- USB On-The-Go Controller -------------------------*/ 19 /** 20 @addtogroup OTG USB On-The-Go Controller(OTG) 21 Memory Mapped Structure for OTG Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var OTG_T::CTL 31 * Offset: 0x00 OTG Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |VBUSDROP |Drop VBUS Control 36 * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS 37 * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. 38 * | | |0 = Not drop the VBUS. 39 * | | |1 = Drop the VBUS. 40 * |[1] |BUSREQ |OTG Bus Request 41 * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection 42 * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power 43 * | | |This bit will be cleared when A-device goes to A_wait_vfall state 44 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. 45 * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol 46 * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification) 47 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. 48 * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. 49 * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. 50 * |[2] |HNPREQEN |OTG HNP Request Enable Bit 51 * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral 52 * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state 53 * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host 54 * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. 55 * | | |0 = HNP request Disabled. 56 * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). 57 * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. 58 * |[4] |OTGEN |OTG Function Enable Bit 59 * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device 60 * | | |When USB frame is not configured as OTG device, this bit must be low. 61 * | | |0= OTG function Disabled. 62 * | | |1 = OTG function Enabled. 63 * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit 64 * | | |0 = OTG ID pin status change wake-up function Disabled. 65 * | | |1 = OTG ID pin status change wake-up function Enabled. 66 * @var OTG_T::PHYCTL 67 * Offset: 0x04 OTG PHY Control Register 68 * --------------------------------------------------------------------------------------------------- 69 * |Bits |Field |Descriptions 70 * | :----: | :----: | :---- | 71 * |[0] |OTGPHYEN |OTG PHY Enable Bit 72 * | | |When USB frame is configured as OTG device or ID dependent, user needs to set this bit before using OTG function 73 * | | |If device is not configured as OTG device nor ID dependent , this bit is "don't care". 74 * | | |0 = OTG PHY Disabled. 75 * | | |1 = OTG PHY Enabled. 76 * |[1] |IDDETEN |ID Detection Enable Bit 77 * | | |0 = Detect ID pin status Disabled. 78 * | | |1 = Detect ID pin status Enabled. 79 * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity 80 * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need 81 * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. 82 * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component 83 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. 84 * | | |0 = The off-chip USB VBUS power switch enable is active high. 85 * | | |1 = The off-chip USB VBUS power switch enable is active low. 86 * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity 87 * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component 88 * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch 89 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. 90 * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. 91 * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. 92 * @var OTG_T::INTEN 93 * Offset: 0x08 OTG Interrupt Enable Register 94 * --------------------------------------------------------------------------------------------------- 95 * |Bits |Field |Descriptions 96 * | :----: | :----: | :---- | 97 * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit 98 * | | |0 = Interrupt Disabled. 99 * | | |1 = Interrupt Enabled. 100 * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit 101 * | | |0 = Interrupt Disabled. 102 * | | |1 = Interrupt Enabled. 103 * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification. 104 * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit 105 * | | |0 = Interrupt Disabled. 106 * | | |1 = Interrupt Enabled. 107 * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit 108 * | | |0 = Interrupt Disabled. 109 * | | |1 = Interrupt Enabled. 110 * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit 111 * | | |0 = Interrupt Disabled. 112 * | | |1 = Interrupt Enabled. 113 * | | |Note: Going to idle state means going to a_idle or b_idle state 114 * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. 115 * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit 116 * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted. 117 * | | |0 = Interrupt Disabled. 118 * | | |1 = Interrupt Enabled. 119 * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit 120 * | | |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted. 121 * | | |0 = This device as a peripheral interrupt Disabled. 122 * | | |1 = This device as a peripheral interrupt Enabled. 123 * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit 124 * | | |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted. 125 * | | |0 = This device as a host interrupt Disabled. 126 * | | |1 = This device as a host interrupt Enabled. 127 * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit 128 * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted. 129 * | | |0 = Interrupt Disabled. 130 * | | |1 = Interrupt Enabled. 131 * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit 132 * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted. 133 * | | |0 = Interrupt Disabled. 134 * | | |1 = Interrupt Enabled. 135 * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit 136 * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted. 137 * | | |0 = Interrupt Disabled. 138 * | | |1 = Interrupt Enabled. 139 * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit 140 * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted. 141 * | | |0 = Interrupt Disabled. 142 * | | |1 = Interrupt Enabled. 143 * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit 144 * | | |0 = Interrupt Disabled. 145 * | | |1 = Interrupt Enabled. 146 * @var OTG_T::INTSTS 147 * Offset: 0x0C OTG Interrupt Status Register 148 * --------------------------------------------------------------------------------------------------- 149 * |Bits |Field |Descriptions 150 * | :----: | :----: | :---- | 151 * |[0] |ROLECHGIF |OTG Role Change Interrupt Status 152 * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. 153 * | | |0 = OTG device role not changed. 154 * | | |1 = OTG device role changed. 155 * | | |Note: Write 1 to clear this flag. 156 * |[1] |VBEIF |VBUS Error Interrupt Status 157 * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. 158 * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. 159 * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. 160 * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. 161 * |[2] |SRPFIF |SRP Fail Interrupt Status 162 * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification 163 * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. 164 * | | |0 = OTG B-device gets VBUS high before this interval. 165 * | | |1 = OTG B-device does not get VBUS high before this interval. 166 * | | |Note: Write 1 to clear this flag. 167 * |[3] |HNPFIF |HNP Fail Interrupt Status 168 * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. 169 * | | |0 = A-device connects to B-device before specified interval expires. 170 * | | |1 = A-device does not connect to B-device before specified interval expires. 171 * | | |Note: Write 1 to clear this flag. 172 * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status 173 * | | |Flag is set if the OTG device transfers from non-idle state to idle state 174 * | | |The OTG device will be neither a host nor a peripheral. 175 * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). 176 * | | |1 = OTG device goes back to idle state(a_idle or b_idle). 177 * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. 178 * | | |Note 2: Write 1 to clear this flag. 179 * |[5] |IDCHGIF |ID State Change Interrupt Status 180 * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. 181 * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. 182 * | | |Note: Write 1 to clear this flag. 183 * |[6] |PDEVIF |Act As Peripheral Interrupt Status 184 * | | |0= This device does not act as a peripheral. 185 * | | |1 = This device acts as a peripheral. 186 * | | |Note: Write 1 to clear this flag. 187 * |[7] |HOSTIF |Act As Host Interrupt Status 188 * | | |0= This device does not act as a host. 189 * | | |1 = This device acts as a host. 190 * | | |Note: Write 1 to clear this flag. 191 * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status 192 * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. 193 * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. 194 * | | |Note: Write 1 to clear this status. 195 * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status 196 * | | |0 = AVLD (OTG_STATUS[4]) not toggled. 197 * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. 198 * | | |Note: Write 1 to clear this status. 199 * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status 200 * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. 201 * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. 202 * | | |Note: Write 1 to clear this status. 203 * |[11] |SECHGIF |SESSEND State Change Interrupt Status 204 * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. 205 * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. 206 * | | |Note: Write 1 to clear this flag. 207 * |[13] |SRPDETIF |SRP Detected Interrupt Status 208 * | | |0 = SRP not detected. 209 * | | |1 = SRP detected. 210 * | | |Note: Write 1 to clear this status. 211 * @var OTG_T::STATUS 212 * Offset: 0x10 OTG Status Register 213 * --------------------------------------------------------------------------------------------------- 214 * |Bits |Field |Descriptions 215 * | :----: | :----: | :---- | 216 * |[0] |OVERCUR |Over Current Condition 217 * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. 218 * | | |0 = OTG A-device drives VBUS successfully. 219 * | | |1 = OTG A-device cannot drives VBUS high in this interval. 220 * |[1] |IDSTS |USB_ID Pin State of Mini-/Micro- Plug 221 * | | |0 = Mini-A/Micro-A plug is attached. 222 * | | |1 = Mini-B/Micro-B plug is attached. 223 * |[2] |SESSEND |Session End Status 224 * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 225 * | | |Session end means no meaningful power on VBUS. 226 * | | |0 = Session is not end. 227 * | | |1 = Session is end. 228 * |[3] |BVLD |B-device Session Valid Status 229 * | | |0 = B-device session is not valid. 230 * | | |1 = B-device session is valid. 231 * |[4] |AVLD |A-device Session Valid Status 232 * | | |0 = A-device session is not valid. 233 * | | |1 = A-device session is valid. 234 * |[5] |VBUSVLD |VBUS Valid Status 235 * | | |When VBUS is larger than 4.7V, this bit will be set to 1. 236 * | | |0 = VBUS is not valid. 237 * | | |1 = VBUS is valid. 238 * |[6] |ASPERI |As Peripheral Status 239 * | | |When OTG as peripheral, this bit is set. 240 * | | |0: OTG not as peripheral 241 * | | |1: OTG as peripheral 242 * |[7] |ASHOST |As Host Status 243 * | | |When OTG as Host, this bit is set. 244 * | | |0: OTG not as Host 245 * | | |1: OTG as Host 246 */ 247 __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */ 248 __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */ 249 __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */ 250 __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */ 251 __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */ 252 253 } OTG_T; 254 255 /** 256 @addtogroup OTG_CONST OTG Bit Field Definition 257 Constant Definitions for OTG Controller 258 @{ 259 */ 260 261 #define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */ 262 #define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */ 263 264 #define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */ 265 #define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */ 266 267 #define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */ 268 #define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */ 269 270 #define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */ 271 #define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */ 272 273 #define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */ 274 #define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */ 275 276 #define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */ 277 #define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */ 278 279 #define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */ 280 #define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */ 281 282 #define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */ 283 #define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */ 284 285 #define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */ 286 #define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */ 287 288 #define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */ 289 #define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */ 290 291 #define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */ 292 #define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */ 293 294 #define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */ 295 #define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */ 296 297 #define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */ 298 #define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */ 299 300 #define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */ 301 #define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */ 302 303 #define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */ 304 #define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */ 305 306 #define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */ 307 #define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */ 308 309 #define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */ 310 #define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */ 311 312 #define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */ 313 #define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */ 314 315 #define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */ 316 #define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */ 317 318 #define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */ 319 #define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */ 320 321 #define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */ 322 #define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */ 323 324 #define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */ 325 #define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */ 326 327 #define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */ 328 #define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */ 329 330 #define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */ 331 #define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */ 332 333 #define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */ 334 #define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */ 335 336 #define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */ 337 #define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */ 338 339 #define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */ 340 #define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */ 341 342 #define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */ 343 #define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */ 344 345 #define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */ 346 #define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */ 347 348 #define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */ 349 #define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */ 350 351 #define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */ 352 #define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */ 353 354 #define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */ 355 #define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */ 356 357 #define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */ 358 #define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */ 359 360 #define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */ 361 #define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */ 362 363 #define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */ 364 #define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */ 365 366 #define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */ 367 #define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */ 368 369 #define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */ 370 #define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */ 371 372 #define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */ 373 #define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */ 374 375 #define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */ 376 #define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */ 377 378 #define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */ 379 #define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */ 380 381 #define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */ 382 #define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */ 383 384 #define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */ 385 #define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */ 386 387 #define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */ 388 #define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */ 389 390 /**@}*/ /* OTG_CONST */ 391 /**@}*/ /* end of OTG register group */ 392 /**@}*/ /* end of REGISTER group */ 393 394 #endif /* __OTG_REG_H__ */ 395
