Searched refs:NRF_SPU (Results 1 – 5 of 5) sorted by relevance
| /trusted-firmware-m-3.7.0/platform/ext/target/nordic_nrf/common/core/native_drivers/ |
| D | spu.c | 62 nrf_spu_int_enable(NRF_SPU, in spu_enable_interrupts()
72 if (nrf_spu_event_check(NRF_SPU, NRF_SPU_EVENT_RAMACCERR)) { in spu_events_get()
75 if (nrf_spu_event_check(NRF_SPU, NRF_SPU_EVENT_FLASHACCERR)) { in spu_events_get()
78 if (nrf_spu_event_check(NRF_SPU, NRF_SPU_EVENT_PERIPHACCERR)) { in spu_events_get()
87 nrf_spu_event_clear(NRF_SPU, NRF_SPU_EVENT_RAMACCERR); in spu_clear_events()
88 nrf_spu_event_clear(NRF_SPU, NRF_SPU_EVENT_FLASHACCERR); in spu_clear_events()
89 nrf_spu_event_clear(NRF_SPU, NRF_SPU_EVENT_PERIPHACCERR); in spu_clear_events()
144 if (!spu_region_is_bootloader_region(NRF_SPU, i)) { in spu_regions_reset_unlocked_secure()
145 nrf_spu_flashregion_set(NRF_SPU, i, in spu_regions_reset_unlocked_secure()
155 if (!spu_region_is_pcd_region(NRF_SPU, i)) { in spu_regions_reset_unlocked_secure()
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| D | spu.h | 134 nrf_spu_dppi_config_set(NRF_SPU, 0, channels_mask, lock_conf); in spu_dppi_config_non_secure()
149 nrf_spu_gpio_config_set(NRF_SPU, port_number, gpio_mask, lock_conf); in spu_gpio_config_non_secure()
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| /trusted-firmware-m-3.7.0/platform/ext/target/nordic_nrf/common/core/ |
| D | target_cfg.c | 654 NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_SPU)); in nvic_interrupt_target_state_cfg()
670 NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU)); in nvic_interrupt_enable()
671 NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU)); in nvic_interrupt_enable()
934 nrf_spu_extdomain_set(NRF_SPU, 0, false, true); in spu_periph_init_cfg()
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| /trusted-firmware-m-3.7.0/platform/ext/target/nordic_nrf/common/nrf91/ |
| D | nrfx_config_nrf91.h | 102 #define NRF_SPU NRF_SPU_S macro
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| /trusted-firmware-m-3.7.0/platform/ext/target/nordic_nrf/common/nrf5340/ |
| D | nrfx_config_nrf5340_application.h | 120 #define NRF_SPU NRF_SPU_S macro
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